| Saeed Bishara | edabd38 | 2009-08-06 15:12:43 +0300 | [diff] [blame^] | 1 | /* |
| 2 | * arch/arm/mach-dove/include/mach/dove.h |
| 3 | * |
| 4 | * Generic definitions for Marvell Dove 88AP510 SoC |
| 5 | * |
| 6 | * This file is licensed under the terms of the GNU General Public |
| 7 | * License version 2. This program is licensed "as is" without any |
| 8 | * warranty of any kind, whether express or implied. |
| 9 | */ |
| 10 | |
| 11 | #ifndef __ASM_ARCH_DOVE_H |
| 12 | #define __ASM_ARCH_DOVE_H |
| 13 | |
| 14 | #include <mach/vmalloc.h> |
| 15 | |
| 16 | /* |
| 17 | * Marvell Dove address maps. |
| 18 | * |
| 19 | * phys virt size |
| 20 | * c8000000 fdb00000 1M Cryptographic SRAM |
| 21 | * e0000000 @runtime 128M PCIe-0 Memory space |
| 22 | * e8000000 @runtime 128M PCIe-1 Memory space |
| 23 | * f1000000 fde00000 8M on-chip south-bridge registers |
| 24 | * f1800000 fe600000 8M on-chip north-bridge registers |
| 25 | * f2000000 fee00000 1M PCIe-0 I/O space |
| 26 | * f2100000 fef00000 1M PCIe-1 I/O space |
| 27 | */ |
| 28 | |
| 29 | #define DOVE_CESA_PHYS_BASE 0xc8000000 |
| 30 | #define DOVE_CESA_VIRT_BASE 0xfdb00000 |
| 31 | #define DOVE_CESA_SIZE SZ_1M |
| 32 | |
| 33 | #define DOVE_PCIE0_MEM_PHYS_BASE 0xe0000000 |
| 34 | #define DOVE_PCIE0_MEM_SIZE SZ_128M |
| 35 | |
| 36 | #define DOVE_PCIE1_MEM_PHYS_BASE 0xe8000000 |
| 37 | #define DOVE_PCIE1_MEM_SIZE SZ_128M |
| 38 | |
| 39 | #define DOVE_BOOTROM_PHYS_BASE 0xf8000000 |
| 40 | #define DOVE_BOOTROM_SIZE SZ_128M |
| 41 | |
| 42 | #define DOVE_SCRATCHPAD_PHYS_BASE 0xf0000000 |
| 43 | #define DOVE_SCRATCHPAD_VIRT_BASE 0xfdd00000 |
| 44 | #define DOVE_SCRATCHPAD_SIZE SZ_1M |
| 45 | |
| 46 | #define DOVE_SB_REGS_PHYS_BASE 0xf1000000 |
| 47 | #define DOVE_SB_REGS_VIRT_BASE 0xfde00000 |
| 48 | #define DOVE_SB_REGS_SIZE SZ_8M |
| 49 | |
| 50 | #define DOVE_NB_REGS_PHYS_BASE 0xf1800000 |
| 51 | #define DOVE_NB_REGS_VIRT_BASE 0xfe600000 |
| 52 | #define DOVE_NB_REGS_SIZE SZ_8M |
| 53 | |
| 54 | #define DOVE_PCIE0_IO_PHYS_BASE 0xf2000000 |
| 55 | #define DOVE_PCIE0_IO_VIRT_BASE 0xfee00000 |
| 56 | #define DOVE_PCIE0_IO_BUS_BASE 0x00000000 |
| 57 | #define DOVE_PCIE0_IO_SIZE SZ_1M |
| 58 | |
| 59 | #define DOVE_PCIE1_IO_PHYS_BASE 0xf2100000 |
| 60 | #define DOVE_PCIE1_IO_VIRT_BASE 0xfef00000 |
| 61 | #define DOVE_PCIE1_IO_BUS_BASE 0x00100000 |
| 62 | #define DOVE_PCIE1_IO_SIZE SZ_1M |
| 63 | |
| 64 | /* |
| 65 | * Dove Core Registers Map |
| 66 | */ |
| 67 | |
| 68 | /* SPI, I2C, UART */ |
| 69 | #define DOVE_I2C_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x11000) |
| 70 | #define DOVE_UART0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x12000) |
| 71 | #define DOVE_UART0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x12000) |
| 72 | #define DOVE_UART1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x12100) |
| 73 | #define DOVE_UART1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x12100) |
| 74 | #define DOVE_UART2_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x12200) |
| 75 | #define DOVE_UART2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x12200) |
| 76 | #define DOVE_UART3_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x12300) |
| 77 | #define DOVE_UART3_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x12300) |
| 78 | #define DOVE_SPI0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x10600) |
| 79 | #define DOVE_SPI1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x14600) |
| 80 | |
| 81 | /* North-South Bridge */ |
| 82 | #define BRIDGE_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x20000) |
| 83 | |
| 84 | /* Cryptographic Engine */ |
| 85 | #define DOVE_CRYPT_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x30000) |
| 86 | |
| 87 | /* PCIe 0 */ |
| 88 | #define DOVE_PCIE0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x40000) |
| 89 | |
| 90 | /* USB */ |
| 91 | #define DOVE_USB0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x50000) |
| 92 | #define DOVE_USB1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x51000) |
| 93 | |
| 94 | /* XOR 0 Engine */ |
| 95 | #define DOVE_XOR0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x60800) |
| 96 | #define DOVE_XOR0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x60800) |
| 97 | #define DOVE_XOR0_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x60A00) |
| 98 | #define DOVE_XOR0_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x60A00) |
| 99 | |
| 100 | /* XOR 1 Engine */ |
| 101 | #define DOVE_XOR1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x60900) |
| 102 | #define DOVE_XOR1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x60900) |
| 103 | #define DOVE_XOR1_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x60B00) |
| 104 | #define DOVE_XOR1_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x60B00) |
| 105 | |
| 106 | /* Gigabit Ethernet */ |
| 107 | #define DOVE_GE00_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x70000) |
| 108 | |
| 109 | /* PCIe 1 */ |
| 110 | #define DOVE_PCIE1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x80000) |
| 111 | |
| 112 | /* CAFE */ |
| 113 | #define DOVE_SDIO0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x92000) |
| 114 | #define DOVE_SDIO1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x90000) |
| 115 | #define DOVE_CAM_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x94000) |
| 116 | #define DOVE_CAFE_WIN_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x98000) |
| 117 | |
| 118 | /* SATA */ |
| 119 | #define DOVE_SATA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xa0000) |
| 120 | |
| 121 | /* I2S/SPDIF */ |
| 122 | #define DOVE_AUD0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xb0000) |
| 123 | #define DOVE_AUD1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xb4000) |
| 124 | |
| 125 | /* NAND Flash Controller */ |
| 126 | #define DOVE_NFC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xc0000) |
| 127 | |
| 128 | /* MPP, GPIO, Reset Sampling */ |
| 129 | #define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0200) |
| 130 | #define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10) |
| 131 | #define DOVE_RESET_SAMPLE_LO (DOVE_MPP_VIRT_BASE | 0x014) |
| 132 | #define DOVE_RESET_SAMPLE_HI (DOVE_MPP_VIRT_BASE | 0x018) |
| 133 | #define DOVE_GPIO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0400) |
| 134 | #define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe803c) |
| 135 | #define DOVE_AU1_SPDIFO_GPIO_EN (1 << 1) |
| 136 | #define DOVE_NAND_GPIO_EN (1 << 0) |
| 137 | #define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_VIRT_BASE + 0x40) |
| 138 | |
| 139 | |
| 140 | /* Power Management */ |
| 141 | #define DOVE_PMU_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0000) |
| 142 | |
| 143 | /* Real Time Clock */ |
| 144 | #define DOVE_RTC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xd8500) |
| 145 | |
| 146 | /* AC97 */ |
| 147 | #define DOVE_AC97_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xe0000) |
| 148 | #define DOVE_AC97_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe0000) |
| 149 | |
| 150 | /* Peripheral DMA */ |
| 151 | #define DOVE_PDMA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xe4000) |
| 152 | #define DOVE_PDMA_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe4000) |
| 153 | |
| 154 | #define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE | 0xe802C) |
| 155 | #define DOVE_TWSI_ENABLE_OPTION1 (1 << 7) |
| 156 | #define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE | 0xe8030) |
| 157 | #define DOVE_TWSI_ENABLE_OPTION2 (1 << 20) |
| 158 | #define DOVE_TWSI_ENABLE_OPTION3 (1 << 21) |
| 159 | #define DOVE_TWSI_OPTION3_GPIO (1 << 22) |
| 160 | #define DOVE_SSP_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xec000) |
| 161 | #define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE | 0xe8034) |
| 162 | #define DOVE_SSP_ON_AU1 (1 << 0) |
| 163 | #define DOVE_SSP_CLOCK_ENABLE (1 << 1) |
| 164 | #define DOVE_SSP_BPB_CLOCK_SRC_SSP (1 << 11) |
| 165 | /* Memory Controller */ |
| 166 | #define DOVE_MC_VIRT_BASE (DOVE_NB_REGS_VIRT_BASE | 0x00000) |
| 167 | |
| 168 | /* LCD Controller */ |
| 169 | #define DOVE_LCD_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x10000) |
| 170 | #define DOVE_LCD1_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x20000) |
| 171 | #define DOVE_LCD2_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x10000) |
| 172 | #define DOVE_LCD_DCON_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x30000) |
| 173 | |
| 174 | /* Graphic Engine */ |
| 175 | #define DOVE_GPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x40000) |
| 176 | |
| 177 | /* Video Engine */ |
| 178 | #define DOVE_VPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x400000) |
| 179 | |
| 180 | #endif |