Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2012 Samsung Electronics Co., Ltd. |
| 3 | * http://www.samsung.com |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 4 | * |
| 5 | * Copyright (C) 2010 Samsung Electronics Co. Ltd. |
| 6 | * Jaswinder Singh <jassi.brar@samsung.com> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
| 12 | */ |
| 13 | |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 14 | #include <linux/kernel.h> |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 15 | #include <linux/io.h> |
| 16 | #include <linux/init.h> |
| 17 | #include <linux/slab.h> |
| 18 | #include <linux/module.h> |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 19 | #include <linux/string.h> |
| 20 | #include <linux/delay.h> |
| 21 | #include <linux/interrupt.h> |
| 22 | #include <linux/dma-mapping.h> |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 23 | #include <linux/dmaengine.h> |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 24 | #include <linux/amba/bus.h> |
| 25 | #include <linux/amba/pl330.h> |
Boojin Kim | 1b9bb71 | 2011-09-02 09:44:30 +0900 | [diff] [blame] | 26 | #include <linux/scatterlist.h> |
Thomas Abraham | 93ed554 | 2011-10-24 11:43:31 +0200 | [diff] [blame] | 27 | #include <linux/of.h> |
Padmavathi Venna | a80258f | 2013-02-14 09:10:06 +0530 | [diff] [blame] | 28 | #include <linux/of_dma.h> |
Sachin Kamat | bcc7fa9 | 2013-03-04 14:36:27 +0530 | [diff] [blame] | 29 | #include <linux/err.h> |
Krzysztof Kozlowski | ae43b32 | 2014-11-14 09:48:57 +0100 | [diff] [blame] | 30 | #include <linux/pm_runtime.h> |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 31 | |
Russell King - ARM Linux | d2ebfb3 | 2012-03-06 22:34:26 +0000 | [diff] [blame] | 32 | #include "dmaengine.h" |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 33 | #define PL330_MAX_CHAN 8 |
| 34 | #define PL330_MAX_IRQS 32 |
| 35 | #define PL330_MAX_PERI 32 |
Shawn Lin | 86a8ce7 | 2016-01-22 19:06:51 +0800 | [diff] [blame] | 36 | #define PL330_MAX_BURST 16 |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 37 | |
Addy Ke | 271e1b86 | 2016-01-22 19:06:46 +0800 | [diff] [blame] | 38 | #define PL330_QUIRK_BROKEN_NO_FLUSHP BIT(0) |
| 39 | |
Lars-Peter Clausen | f0564c7 | 2014-07-06 20:32:19 +0200 | [diff] [blame] | 40 | enum pl330_cachectrl { |
| 41 | CCTRL0, /* Noncacheable and nonbufferable */ |
| 42 | CCTRL1, /* Bufferable only */ |
| 43 | CCTRL2, /* Cacheable, but do not allocate */ |
| 44 | CCTRL3, /* Cacheable and bufferable, but do not allocate */ |
| 45 | INVALID1, /* AWCACHE = 0x1000 */ |
| 46 | INVALID2, |
| 47 | CCTRL6, /* Cacheable write-through, allocate on writes only */ |
| 48 | CCTRL7, /* Cacheable write-back, allocate on writes only */ |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 49 | }; |
| 50 | |
| 51 | enum pl330_byteswap { |
| 52 | SWAP_NO, |
| 53 | SWAP_2, |
| 54 | SWAP_4, |
| 55 | SWAP_8, |
| 56 | SWAP_16, |
| 57 | }; |
| 58 | |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 59 | /* Register and Bit field Definitions */ |
| 60 | #define DS 0x0 |
| 61 | #define DS_ST_STOP 0x0 |
| 62 | #define DS_ST_EXEC 0x1 |
| 63 | #define DS_ST_CMISS 0x2 |
| 64 | #define DS_ST_UPDTPC 0x3 |
| 65 | #define DS_ST_WFE 0x4 |
| 66 | #define DS_ST_ATBRR 0x5 |
| 67 | #define DS_ST_QBUSY 0x6 |
| 68 | #define DS_ST_WFP 0x7 |
| 69 | #define DS_ST_KILL 0x8 |
| 70 | #define DS_ST_CMPLT 0x9 |
| 71 | #define DS_ST_FLTCMP 0xe |
| 72 | #define DS_ST_FAULT 0xf |
| 73 | |
| 74 | #define DPC 0x4 |
| 75 | #define INTEN 0x20 |
| 76 | #define ES 0x24 |
| 77 | #define INTSTATUS 0x28 |
| 78 | #define INTCLR 0x2c |
| 79 | #define FSM 0x30 |
| 80 | #define FSC 0x34 |
| 81 | #define FTM 0x38 |
| 82 | |
| 83 | #define _FTC 0x40 |
| 84 | #define FTC(n) (_FTC + (n)*0x4) |
| 85 | |
| 86 | #define _CS 0x100 |
| 87 | #define CS(n) (_CS + (n)*0x8) |
| 88 | #define CS_CNS (1 << 21) |
| 89 | |
| 90 | #define _CPC 0x104 |
| 91 | #define CPC(n) (_CPC + (n)*0x8) |
| 92 | |
| 93 | #define _SA 0x400 |
| 94 | #define SA(n) (_SA + (n)*0x20) |
| 95 | |
| 96 | #define _DA 0x404 |
| 97 | #define DA(n) (_DA + (n)*0x20) |
| 98 | |
| 99 | #define _CC 0x408 |
| 100 | #define CC(n) (_CC + (n)*0x20) |
| 101 | |
| 102 | #define CC_SRCINC (1 << 0) |
| 103 | #define CC_DSTINC (1 << 14) |
| 104 | #define CC_SRCPRI (1 << 8) |
| 105 | #define CC_DSTPRI (1 << 22) |
| 106 | #define CC_SRCNS (1 << 9) |
| 107 | #define CC_DSTNS (1 << 23) |
| 108 | #define CC_SRCIA (1 << 10) |
| 109 | #define CC_DSTIA (1 << 24) |
| 110 | #define CC_SRCBRSTLEN_SHFT 4 |
| 111 | #define CC_DSTBRSTLEN_SHFT 18 |
| 112 | #define CC_SRCBRSTSIZE_SHFT 1 |
| 113 | #define CC_DSTBRSTSIZE_SHFT 15 |
| 114 | #define CC_SRCCCTRL_SHFT 11 |
| 115 | #define CC_SRCCCTRL_MASK 0x7 |
| 116 | #define CC_DSTCCTRL_SHFT 25 |
| 117 | #define CC_DRCCCTRL_MASK 0x7 |
| 118 | #define CC_SWAP_SHFT 28 |
| 119 | |
| 120 | #define _LC0 0x40c |
| 121 | #define LC0(n) (_LC0 + (n)*0x20) |
| 122 | |
| 123 | #define _LC1 0x410 |
| 124 | #define LC1(n) (_LC1 + (n)*0x20) |
| 125 | |
| 126 | #define DBGSTATUS 0xd00 |
| 127 | #define DBG_BUSY (1 << 0) |
| 128 | |
| 129 | #define DBGCMD 0xd04 |
| 130 | #define DBGINST0 0xd08 |
| 131 | #define DBGINST1 0xd0c |
| 132 | |
| 133 | #define CR0 0xe00 |
| 134 | #define CR1 0xe04 |
| 135 | #define CR2 0xe08 |
| 136 | #define CR3 0xe0c |
| 137 | #define CR4 0xe10 |
| 138 | #define CRD 0xe14 |
| 139 | |
| 140 | #define PERIPH_ID 0xfe0 |
Boojin Kim | 3ecf51a | 2011-12-26 18:55:47 +0900 | [diff] [blame] | 141 | #define PERIPH_REV_SHIFT 20 |
| 142 | #define PERIPH_REV_MASK 0xf |
| 143 | #define PERIPH_REV_R0P0 0 |
| 144 | #define PERIPH_REV_R1P0 1 |
| 145 | #define PERIPH_REV_R1P1 2 |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 146 | |
| 147 | #define CR0_PERIPH_REQ_SET (1 << 0) |
| 148 | #define CR0_BOOT_EN_SET (1 << 1) |
| 149 | #define CR0_BOOT_MAN_NS (1 << 2) |
| 150 | #define CR0_NUM_CHANS_SHIFT 4 |
| 151 | #define CR0_NUM_CHANS_MASK 0x7 |
| 152 | #define CR0_NUM_PERIPH_SHIFT 12 |
| 153 | #define CR0_NUM_PERIPH_MASK 0x1f |
| 154 | #define CR0_NUM_EVENTS_SHIFT 17 |
| 155 | #define CR0_NUM_EVENTS_MASK 0x1f |
| 156 | |
| 157 | #define CR1_ICACHE_LEN_SHIFT 0 |
| 158 | #define CR1_ICACHE_LEN_MASK 0x7 |
| 159 | #define CR1_NUM_ICACHELINES_SHIFT 4 |
| 160 | #define CR1_NUM_ICACHELINES_MASK 0xf |
| 161 | |
| 162 | #define CRD_DATA_WIDTH_SHIFT 0 |
| 163 | #define CRD_DATA_WIDTH_MASK 0x7 |
| 164 | #define CRD_WR_CAP_SHIFT 4 |
| 165 | #define CRD_WR_CAP_MASK 0x7 |
| 166 | #define CRD_WR_Q_DEP_SHIFT 8 |
| 167 | #define CRD_WR_Q_DEP_MASK 0xf |
| 168 | #define CRD_RD_CAP_SHIFT 12 |
| 169 | #define CRD_RD_CAP_MASK 0x7 |
| 170 | #define CRD_RD_Q_DEP_SHIFT 16 |
| 171 | #define CRD_RD_Q_DEP_MASK 0xf |
| 172 | #define CRD_DATA_BUFF_SHIFT 20 |
| 173 | #define CRD_DATA_BUFF_MASK 0x3ff |
| 174 | |
| 175 | #define PART 0x330 |
| 176 | #define DESIGNER 0x41 |
| 177 | #define REVISION 0x0 |
| 178 | #define INTEG_CFG 0x0 |
| 179 | #define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12)) |
| 180 | |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 181 | #define PL330_STATE_STOPPED (1 << 0) |
| 182 | #define PL330_STATE_EXECUTING (1 << 1) |
| 183 | #define PL330_STATE_WFE (1 << 2) |
| 184 | #define PL330_STATE_FAULTING (1 << 3) |
| 185 | #define PL330_STATE_COMPLETING (1 << 4) |
| 186 | #define PL330_STATE_WFP (1 << 5) |
| 187 | #define PL330_STATE_KILLING (1 << 6) |
| 188 | #define PL330_STATE_FAULT_COMPLETING (1 << 7) |
| 189 | #define PL330_STATE_CACHEMISS (1 << 8) |
| 190 | #define PL330_STATE_UPDTPC (1 << 9) |
| 191 | #define PL330_STATE_ATBARRIER (1 << 10) |
| 192 | #define PL330_STATE_QUEUEBUSY (1 << 11) |
| 193 | #define PL330_STATE_INVALID (1 << 15) |
| 194 | |
| 195 | #define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \ |
| 196 | | PL330_STATE_WFE | PL330_STATE_FAULTING) |
| 197 | |
| 198 | #define CMD_DMAADDH 0x54 |
| 199 | #define CMD_DMAEND 0x00 |
| 200 | #define CMD_DMAFLUSHP 0x35 |
| 201 | #define CMD_DMAGO 0xa0 |
| 202 | #define CMD_DMALD 0x04 |
| 203 | #define CMD_DMALDP 0x25 |
| 204 | #define CMD_DMALP 0x20 |
| 205 | #define CMD_DMALPEND 0x28 |
| 206 | #define CMD_DMAKILL 0x01 |
| 207 | #define CMD_DMAMOV 0xbc |
| 208 | #define CMD_DMANOP 0x18 |
| 209 | #define CMD_DMARMB 0x12 |
| 210 | #define CMD_DMASEV 0x34 |
| 211 | #define CMD_DMAST 0x08 |
| 212 | #define CMD_DMASTP 0x29 |
| 213 | #define CMD_DMASTZ 0x0c |
| 214 | #define CMD_DMAWFE 0x36 |
| 215 | #define CMD_DMAWFP 0x30 |
| 216 | #define CMD_DMAWMB 0x13 |
| 217 | |
| 218 | #define SZ_DMAADDH 3 |
| 219 | #define SZ_DMAEND 1 |
| 220 | #define SZ_DMAFLUSHP 2 |
| 221 | #define SZ_DMALD 1 |
| 222 | #define SZ_DMALDP 2 |
| 223 | #define SZ_DMALP 2 |
| 224 | #define SZ_DMALPEND 2 |
| 225 | #define SZ_DMAKILL 1 |
| 226 | #define SZ_DMAMOV 6 |
| 227 | #define SZ_DMANOP 1 |
| 228 | #define SZ_DMARMB 1 |
| 229 | #define SZ_DMASEV 2 |
| 230 | #define SZ_DMAST 1 |
| 231 | #define SZ_DMASTP 2 |
| 232 | #define SZ_DMASTZ 1 |
| 233 | #define SZ_DMAWFE 2 |
| 234 | #define SZ_DMAWFP 2 |
| 235 | #define SZ_DMAWMB 1 |
| 236 | #define SZ_DMAGO 6 |
| 237 | |
| 238 | #define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1) |
| 239 | #define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7)) |
| 240 | |
| 241 | #define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr)) |
| 242 | #define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr)) |
| 243 | |
| 244 | /* |
| 245 | * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req |
| 246 | * at 1byte/burst for P<->M and M<->M respectively. |
| 247 | * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req |
| 248 | * should be enough for P<->M and M<->M respectively. |
| 249 | */ |
| 250 | #define MCODE_BUFF_PER_REQ 256 |
| 251 | |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 252 | /* Use this _only_ to wait on transient states */ |
| 253 | #define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax(); |
| 254 | |
| 255 | #ifdef PL330_DEBUG_MCGEN |
| 256 | static unsigned cmd_line; |
| 257 | #define PL330_DBGCMD_DUMP(off, x...) do { \ |
| 258 | printk("%x:", cmd_line); \ |
| 259 | printk(x); \ |
| 260 | cmd_line += off; \ |
| 261 | } while (0) |
| 262 | #define PL330_DBGMC_START(addr) (cmd_line = addr) |
| 263 | #else |
| 264 | #define PL330_DBGCMD_DUMP(off, x...) do {} while (0) |
| 265 | #define PL330_DBGMC_START(addr) do {} while (0) |
| 266 | #endif |
| 267 | |
| 268 | /* The number of default descriptors */ |
Russell King - ARM Linux | d2ebfb3 | 2012-03-06 22:34:26 +0000 | [diff] [blame] | 269 | |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 270 | #define NR_DEFAULT_DESC 16 |
| 271 | |
Krzysztof Kozlowski | ae43b32 | 2014-11-14 09:48:57 +0100 | [diff] [blame] | 272 | /* Delay for runtime PM autosuspend, ms */ |
| 273 | #define PL330_AUTOSUSPEND_DELAY 20 |
| 274 | |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 275 | /* Populated by the PL330 core driver for DMA API driver's info */ |
| 276 | struct pl330_config { |
| 277 | u32 periph_id; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 278 | #define DMAC_MODE_NS (1 << 0) |
| 279 | unsigned int mode; |
| 280 | unsigned int data_bus_width:10; /* In number of bits */ |
Liviu Dudau | 1f0a5cb | 2014-11-06 17:20:12 +0000 | [diff] [blame] | 281 | unsigned int data_buf_dep:11; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 282 | unsigned int num_chan:4; |
| 283 | unsigned int num_peri:6; |
| 284 | u32 peri_ns; |
| 285 | unsigned int num_events:6; |
| 286 | u32 irq_ns; |
| 287 | }; |
| 288 | |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 289 | /** |
| 290 | * Request Configuration. |
| 291 | * The PL330 core does not modify this and uses the last |
| 292 | * working configuration if the request doesn't provide any. |
| 293 | * |
| 294 | * The Client may want to provide this info only for the |
| 295 | * first request and a request with new settings. |
| 296 | */ |
| 297 | struct pl330_reqcfg { |
| 298 | /* Address Incrementing */ |
| 299 | unsigned dst_inc:1; |
| 300 | unsigned src_inc:1; |
| 301 | |
| 302 | /* |
| 303 | * For now, the SRC & DST protection levels |
| 304 | * and burst size/length are assumed same. |
| 305 | */ |
| 306 | bool nonsecure; |
| 307 | bool privileged; |
| 308 | bool insnaccess; |
| 309 | unsigned brst_len:5; |
| 310 | unsigned brst_size:3; /* in power of 2 */ |
| 311 | |
Lars-Peter Clausen | f0564c7 | 2014-07-06 20:32:19 +0200 | [diff] [blame] | 312 | enum pl330_cachectrl dcctl; |
| 313 | enum pl330_cachectrl scctl; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 314 | enum pl330_byteswap swap; |
Boojin Kim | 3ecf51a | 2011-12-26 18:55:47 +0900 | [diff] [blame] | 315 | struct pl330_config *pcfg; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 316 | }; |
| 317 | |
| 318 | /* |
| 319 | * One cycle of DMAC operation. |
| 320 | * There may be more than one xfer in a request. |
| 321 | */ |
| 322 | struct pl330_xfer { |
| 323 | u32 src_addr; |
| 324 | u32 dst_addr; |
| 325 | /* Size to xfer */ |
| 326 | u32 bytes; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 327 | }; |
| 328 | |
| 329 | /* The xfer callbacks are made with one of these arguments. */ |
| 330 | enum pl330_op_err { |
| 331 | /* The all xfers in the request were success. */ |
| 332 | PL330_ERR_NONE, |
| 333 | /* If req aborted due to global error. */ |
| 334 | PL330_ERR_ABORT, |
| 335 | /* If req failed due to problem with Channel. */ |
| 336 | PL330_ERR_FAIL, |
| 337 | }; |
| 338 | |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 339 | enum dmamov_dst { |
| 340 | SAR = 0, |
| 341 | CCR, |
| 342 | DAR, |
| 343 | }; |
| 344 | |
| 345 | enum pl330_dst { |
| 346 | SRC = 0, |
| 347 | DST, |
| 348 | }; |
| 349 | |
| 350 | enum pl330_cond { |
| 351 | SINGLE, |
| 352 | BURST, |
| 353 | ALWAYS, |
| 354 | }; |
| 355 | |
Lars-Peter Clausen | 9dc5a31 | 2014-07-06 20:32:30 +0200 | [diff] [blame] | 356 | struct dma_pl330_desc; |
| 357 | |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 358 | struct _pl330_req { |
| 359 | u32 mc_bus; |
| 360 | void *mc_cpu; |
Lars-Peter Clausen | 9dc5a31 | 2014-07-06 20:32:30 +0200 | [diff] [blame] | 361 | struct dma_pl330_desc *desc; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 362 | }; |
| 363 | |
| 364 | /* ToBeDone for tasklet */ |
| 365 | struct _pl330_tbd { |
| 366 | bool reset_dmac; |
| 367 | bool reset_mngr; |
| 368 | u8 reset_chan; |
| 369 | }; |
| 370 | |
| 371 | /* A DMAC Thread */ |
| 372 | struct pl330_thread { |
| 373 | u8 id; |
| 374 | int ev; |
| 375 | /* If the channel is not yet acquired by any client */ |
| 376 | bool free; |
| 377 | /* Parent DMAC */ |
| 378 | struct pl330_dmac *dmac; |
| 379 | /* Only two at a time */ |
| 380 | struct _pl330_req req[2]; |
| 381 | /* Index of the last enqueued request */ |
| 382 | unsigned lstenq; |
| 383 | /* Index of the last submitted request or -1 if the DMA is stopped */ |
| 384 | int req_running; |
| 385 | }; |
| 386 | |
| 387 | enum pl330_dmac_state { |
| 388 | UNINIT, |
| 389 | INIT, |
| 390 | DYING, |
| 391 | }; |
| 392 | |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 393 | enum desc_status { |
| 394 | /* In the DMAC pool */ |
| 395 | FREE, |
| 396 | /* |
Masanari Iida | d73111c | 2012-08-04 23:37:53 +0900 | [diff] [blame] | 397 | * Allocated to some channel during prep_xxx |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 398 | * Also may be sitting on the work_list. |
| 399 | */ |
| 400 | PREP, |
| 401 | /* |
| 402 | * Sitting on the work_list and already submitted |
| 403 | * to the PL330 core. Not more than two descriptors |
| 404 | * of a channel can be BUSY at any time. |
| 405 | */ |
| 406 | BUSY, |
| 407 | /* |
| 408 | * Sitting on the channel work_list but xfer done |
| 409 | * by PL330 core |
| 410 | */ |
| 411 | DONE, |
| 412 | }; |
| 413 | |
| 414 | struct dma_pl330_chan { |
| 415 | /* Schedule desc completion */ |
| 416 | struct tasklet_struct task; |
| 417 | |
| 418 | /* DMA-Engine Channel */ |
| 419 | struct dma_chan chan; |
| 420 | |
Lars-Peter Clausen | 04abf5d | 2014-01-11 20:08:38 +0100 | [diff] [blame] | 421 | /* List of submitted descriptors */ |
| 422 | struct list_head submitted_list; |
| 423 | /* List of issued descriptors */ |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 424 | struct list_head work_list; |
Lars-Peter Clausen | 39ff861 | 2013-08-27 20:34:05 +0200 | [diff] [blame] | 425 | /* List of completed descriptors */ |
| 426 | struct list_head completed_list; |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 427 | |
| 428 | /* Pointer to the DMAC that manages this channel, |
| 429 | * NULL if the channel is available to be acquired. |
| 430 | * As the parent, this DMAC also provides descriptors |
| 431 | * to the channel. |
| 432 | */ |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 433 | struct pl330_dmac *dmac; |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 434 | |
| 435 | /* To protect channel manipulation */ |
| 436 | spinlock_t lock; |
| 437 | |
Lars-Peter Clausen | 65ad606 | 2014-07-06 20:32:26 +0200 | [diff] [blame] | 438 | /* |
| 439 | * Hardware channel thread of PL330 DMAC. NULL if the channel is |
| 440 | * available. |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 441 | */ |
Lars-Peter Clausen | 65ad606 | 2014-07-06 20:32:26 +0200 | [diff] [blame] | 442 | struct pl330_thread *thread; |
Boojin Kim | 1b9bb71 | 2011-09-02 09:44:30 +0900 | [diff] [blame] | 443 | |
| 444 | /* For D-to-M and M-to-D channels */ |
| 445 | int burst_sz; /* the peripheral fifo width */ |
Boojin Kim | 1d0c1d6 | 2011-09-02 09:44:31 +0900 | [diff] [blame] | 446 | int burst_len; /* the number of burst */ |
Boojin Kim | 1b9bb71 | 2011-09-02 09:44:30 +0900 | [diff] [blame] | 447 | dma_addr_t fifo_addr; |
Boojin Kim | 42bc9cf | 2011-09-02 09:44:33 +0900 | [diff] [blame] | 448 | |
| 449 | /* for cyclic capability */ |
| 450 | bool cyclic; |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 451 | }; |
| 452 | |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 453 | struct pl330_dmac { |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 454 | /* DMA-Engine Device */ |
| 455 | struct dma_device ddma; |
| 456 | |
Lars-Peter Clausen | b714b84 | 2013-11-25 16:07:46 +0100 | [diff] [blame] | 457 | /* Holds info about sg limitations */ |
| 458 | struct device_dma_parameters dma_parms; |
| 459 | |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 460 | /* Pool of descriptors available for the DMAC's channels */ |
| 461 | struct list_head desc_pool; |
| 462 | /* To protect desc_pool manipulation */ |
| 463 | spinlock_t pool_lock; |
| 464 | |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 465 | /* Size of MicroCode buffers for each channel. */ |
| 466 | unsigned mcbufsz; |
| 467 | /* ioremap'ed address of PL330 registers. */ |
| 468 | void __iomem *base; |
| 469 | /* Populated by the PL330 core driver during pl330_add */ |
| 470 | struct pl330_config pcfg; |
| 471 | |
| 472 | spinlock_t lock; |
| 473 | /* Maximum possible events/irqs */ |
| 474 | int events[32]; |
| 475 | /* BUS address of MicroCode buffer */ |
| 476 | dma_addr_t mcode_bus; |
| 477 | /* CPU address of MicroCode buffer */ |
| 478 | void *mcode_cpu; |
| 479 | /* List of all Channel threads */ |
| 480 | struct pl330_thread *channels; |
| 481 | /* Pointer to the MANAGER thread */ |
| 482 | struct pl330_thread *manager; |
| 483 | /* To handle bad news in interrupt */ |
| 484 | struct tasklet_struct tasks; |
| 485 | struct _pl330_tbd dmac_tbd; |
| 486 | /* State of DMAC operation */ |
| 487 | enum pl330_dmac_state state; |
| 488 | /* Holds list of reqs with due callbacks */ |
| 489 | struct list_head req_done; |
| 490 | |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 491 | /* Peripheral channels connected to this DMAC */ |
Lars-Peter Clausen | 70cbb16 | 2014-01-11 20:08:39 +0100 | [diff] [blame] | 492 | unsigned int num_peripherals; |
Rob Herring | 4e0e610 | 2011-07-25 16:05:04 -0500 | [diff] [blame] | 493 | struct dma_pl330_chan *peripherals; /* keep at end */ |
Addy Ke | 271e1b86 | 2016-01-22 19:06:46 +0800 | [diff] [blame] | 494 | int quirks; |
| 495 | }; |
| 496 | |
| 497 | static struct pl330_of_quirks { |
| 498 | char *quirk; |
| 499 | int id; |
| 500 | } of_quirks[] = { |
| 501 | { |
| 502 | .quirk = "arm,pl330-broken-no-flushp", |
| 503 | .id = PL330_QUIRK_BROKEN_NO_FLUSHP, |
| 504 | } |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 505 | }; |
| 506 | |
| 507 | struct dma_pl330_desc { |
| 508 | /* To attach to a queue as child */ |
| 509 | struct list_head node; |
| 510 | |
| 511 | /* Descriptor for the DMA Engine API */ |
| 512 | struct dma_async_tx_descriptor txd; |
| 513 | |
| 514 | /* Xfer for PL330 core */ |
| 515 | struct pl330_xfer px; |
| 516 | |
| 517 | struct pl330_reqcfg rqcfg; |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 518 | |
| 519 | enum desc_status status; |
| 520 | |
Robert Baldyga | aee4d1f | 2015-02-11 13:23:17 +0100 | [diff] [blame] | 521 | int bytes_requested; |
| 522 | bool last; |
| 523 | |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 524 | /* The channel which currently holds this desc */ |
| 525 | struct dma_pl330_chan *pchan; |
Lars-Peter Clausen | 9dc5a31 | 2014-07-06 20:32:30 +0200 | [diff] [blame] | 526 | |
| 527 | enum dma_transfer_direction rqtype; |
| 528 | /* Index of peripheral for the xfer. */ |
| 529 | unsigned peri:5; |
| 530 | /* Hook to attach to DMAC's list of reqs with due callback */ |
| 531 | struct list_head rqd; |
| 532 | }; |
| 533 | |
| 534 | struct _xfer_spec { |
| 535 | u32 ccr; |
| 536 | struct dma_pl330_desc *desc; |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 537 | }; |
| 538 | |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 539 | static inline bool _queue_empty(struct pl330_thread *thrd) |
| 540 | { |
Lars-Peter Clausen | 8ed30a1 | 2014-07-06 20:32:31 +0200 | [diff] [blame] | 541 | return thrd->req[0].desc == NULL && thrd->req[1].desc == NULL; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 542 | } |
| 543 | |
| 544 | static inline bool _queue_full(struct pl330_thread *thrd) |
| 545 | { |
Lars-Peter Clausen | 8ed30a1 | 2014-07-06 20:32:31 +0200 | [diff] [blame] | 546 | return thrd->req[0].desc != NULL && thrd->req[1].desc != NULL; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 547 | } |
| 548 | |
| 549 | static inline bool is_manager(struct pl330_thread *thrd) |
| 550 | { |
Lars-Peter Clausen | fbbcd9b | 2014-07-06 20:32:28 +0200 | [diff] [blame] | 551 | return thrd->dmac->manager == thrd; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 552 | } |
| 553 | |
| 554 | /* If manager of the thread is in Non-Secure mode */ |
| 555 | static inline bool _manager_ns(struct pl330_thread *thrd) |
| 556 | { |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 557 | return (thrd->dmac->pcfg.mode & DMAC_MODE_NS) ? true : false; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 558 | } |
| 559 | |
Boojin Kim | 3ecf51a | 2011-12-26 18:55:47 +0900 | [diff] [blame] | 560 | static inline u32 get_revision(u32 periph_id) |
| 561 | { |
| 562 | return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK; |
| 563 | } |
| 564 | |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 565 | static inline u32 _emit_ADDH(unsigned dry_run, u8 buf[], |
| 566 | enum pl330_dst da, u16 val) |
| 567 | { |
| 568 | if (dry_run) |
| 569 | return SZ_DMAADDH; |
| 570 | |
| 571 | buf[0] = CMD_DMAADDH; |
| 572 | buf[0] |= (da << 1); |
Ben Dooks | 3a2307f | 2015-03-16 11:52:43 +0000 | [diff] [blame] | 573 | *((__le16 *)&buf[1]) = cpu_to_le16(val); |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 574 | |
| 575 | PL330_DBGCMD_DUMP(SZ_DMAADDH, "\tDMAADDH %s %u\n", |
| 576 | da == 1 ? "DA" : "SA", val); |
| 577 | |
| 578 | return SZ_DMAADDH; |
| 579 | } |
| 580 | |
| 581 | static inline u32 _emit_END(unsigned dry_run, u8 buf[]) |
| 582 | { |
| 583 | if (dry_run) |
| 584 | return SZ_DMAEND; |
| 585 | |
| 586 | buf[0] = CMD_DMAEND; |
| 587 | |
| 588 | PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n"); |
| 589 | |
| 590 | return SZ_DMAEND; |
| 591 | } |
| 592 | |
| 593 | static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri) |
| 594 | { |
| 595 | if (dry_run) |
| 596 | return SZ_DMAFLUSHP; |
| 597 | |
| 598 | buf[0] = CMD_DMAFLUSHP; |
| 599 | |
| 600 | peri &= 0x1f; |
| 601 | peri <<= 3; |
| 602 | buf[1] = peri; |
| 603 | |
| 604 | PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3); |
| 605 | |
| 606 | return SZ_DMAFLUSHP; |
| 607 | } |
| 608 | |
| 609 | static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond) |
| 610 | { |
| 611 | if (dry_run) |
| 612 | return SZ_DMALD; |
| 613 | |
| 614 | buf[0] = CMD_DMALD; |
| 615 | |
| 616 | if (cond == SINGLE) |
| 617 | buf[0] |= (0 << 1) | (1 << 0); |
| 618 | else if (cond == BURST) |
| 619 | buf[0] |= (1 << 1) | (1 << 0); |
| 620 | |
| 621 | PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n", |
| 622 | cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A')); |
| 623 | |
| 624 | return SZ_DMALD; |
| 625 | } |
| 626 | |
| 627 | static inline u32 _emit_LDP(unsigned dry_run, u8 buf[], |
| 628 | enum pl330_cond cond, u8 peri) |
| 629 | { |
| 630 | if (dry_run) |
| 631 | return SZ_DMALDP; |
| 632 | |
| 633 | buf[0] = CMD_DMALDP; |
| 634 | |
| 635 | if (cond == BURST) |
| 636 | buf[0] |= (1 << 1); |
| 637 | |
| 638 | peri &= 0x1f; |
| 639 | peri <<= 3; |
| 640 | buf[1] = peri; |
| 641 | |
| 642 | PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n", |
| 643 | cond == SINGLE ? 'S' : 'B', peri >> 3); |
| 644 | |
| 645 | return SZ_DMALDP; |
| 646 | } |
| 647 | |
| 648 | static inline u32 _emit_LP(unsigned dry_run, u8 buf[], |
| 649 | unsigned loop, u8 cnt) |
| 650 | { |
| 651 | if (dry_run) |
| 652 | return SZ_DMALP; |
| 653 | |
| 654 | buf[0] = CMD_DMALP; |
| 655 | |
| 656 | if (loop) |
| 657 | buf[0] |= (1 << 1); |
| 658 | |
| 659 | cnt--; /* DMAC increments by 1 internally */ |
| 660 | buf[1] = cnt; |
| 661 | |
| 662 | PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt); |
| 663 | |
| 664 | return SZ_DMALP; |
| 665 | } |
| 666 | |
| 667 | struct _arg_LPEND { |
| 668 | enum pl330_cond cond; |
| 669 | bool forever; |
| 670 | unsigned loop; |
| 671 | u8 bjump; |
| 672 | }; |
| 673 | |
| 674 | static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[], |
| 675 | const struct _arg_LPEND *arg) |
| 676 | { |
| 677 | enum pl330_cond cond = arg->cond; |
| 678 | bool forever = arg->forever; |
| 679 | unsigned loop = arg->loop; |
| 680 | u8 bjump = arg->bjump; |
| 681 | |
| 682 | if (dry_run) |
| 683 | return SZ_DMALPEND; |
| 684 | |
| 685 | buf[0] = CMD_DMALPEND; |
| 686 | |
| 687 | if (loop) |
| 688 | buf[0] |= (1 << 2); |
| 689 | |
| 690 | if (!forever) |
| 691 | buf[0] |= (1 << 4); |
| 692 | |
| 693 | if (cond == SINGLE) |
| 694 | buf[0] |= (0 << 1) | (1 << 0); |
| 695 | else if (cond == BURST) |
| 696 | buf[0] |= (1 << 1) | (1 << 0); |
| 697 | |
| 698 | buf[1] = bjump; |
| 699 | |
| 700 | PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n", |
| 701 | forever ? "FE" : "END", |
| 702 | cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'), |
| 703 | loop ? '1' : '0', |
| 704 | bjump); |
| 705 | |
| 706 | return SZ_DMALPEND; |
| 707 | } |
| 708 | |
| 709 | static inline u32 _emit_KILL(unsigned dry_run, u8 buf[]) |
| 710 | { |
| 711 | if (dry_run) |
| 712 | return SZ_DMAKILL; |
| 713 | |
| 714 | buf[0] = CMD_DMAKILL; |
| 715 | |
| 716 | return SZ_DMAKILL; |
| 717 | } |
| 718 | |
| 719 | static inline u32 _emit_MOV(unsigned dry_run, u8 buf[], |
| 720 | enum dmamov_dst dst, u32 val) |
| 721 | { |
| 722 | if (dry_run) |
| 723 | return SZ_DMAMOV; |
| 724 | |
| 725 | buf[0] = CMD_DMAMOV; |
| 726 | buf[1] = dst; |
Ben Dooks | 3a2307f | 2015-03-16 11:52:43 +0000 | [diff] [blame] | 727 | *((__le32 *)&buf[2]) = cpu_to_le32(val); |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 728 | |
| 729 | PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n", |
| 730 | dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val); |
| 731 | |
| 732 | return SZ_DMAMOV; |
| 733 | } |
| 734 | |
| 735 | static inline u32 _emit_NOP(unsigned dry_run, u8 buf[]) |
| 736 | { |
| 737 | if (dry_run) |
| 738 | return SZ_DMANOP; |
| 739 | |
| 740 | buf[0] = CMD_DMANOP; |
| 741 | |
| 742 | PL330_DBGCMD_DUMP(SZ_DMANOP, "\tDMANOP\n"); |
| 743 | |
| 744 | return SZ_DMANOP; |
| 745 | } |
| 746 | |
| 747 | static inline u32 _emit_RMB(unsigned dry_run, u8 buf[]) |
| 748 | { |
| 749 | if (dry_run) |
| 750 | return SZ_DMARMB; |
| 751 | |
| 752 | buf[0] = CMD_DMARMB; |
| 753 | |
| 754 | PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n"); |
| 755 | |
| 756 | return SZ_DMARMB; |
| 757 | } |
| 758 | |
| 759 | static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev) |
| 760 | { |
| 761 | if (dry_run) |
| 762 | return SZ_DMASEV; |
| 763 | |
| 764 | buf[0] = CMD_DMASEV; |
| 765 | |
| 766 | ev &= 0x1f; |
| 767 | ev <<= 3; |
| 768 | buf[1] = ev; |
| 769 | |
| 770 | PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3); |
| 771 | |
| 772 | return SZ_DMASEV; |
| 773 | } |
| 774 | |
| 775 | static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond) |
| 776 | { |
| 777 | if (dry_run) |
| 778 | return SZ_DMAST; |
| 779 | |
| 780 | buf[0] = CMD_DMAST; |
| 781 | |
| 782 | if (cond == SINGLE) |
| 783 | buf[0] |= (0 << 1) | (1 << 0); |
| 784 | else if (cond == BURST) |
| 785 | buf[0] |= (1 << 1) | (1 << 0); |
| 786 | |
| 787 | PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n", |
| 788 | cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A')); |
| 789 | |
| 790 | return SZ_DMAST; |
| 791 | } |
| 792 | |
| 793 | static inline u32 _emit_STP(unsigned dry_run, u8 buf[], |
| 794 | enum pl330_cond cond, u8 peri) |
| 795 | { |
| 796 | if (dry_run) |
| 797 | return SZ_DMASTP; |
| 798 | |
| 799 | buf[0] = CMD_DMASTP; |
| 800 | |
| 801 | if (cond == BURST) |
| 802 | buf[0] |= (1 << 1); |
| 803 | |
| 804 | peri &= 0x1f; |
| 805 | peri <<= 3; |
| 806 | buf[1] = peri; |
| 807 | |
| 808 | PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n", |
| 809 | cond == SINGLE ? 'S' : 'B', peri >> 3); |
| 810 | |
| 811 | return SZ_DMASTP; |
| 812 | } |
| 813 | |
| 814 | static inline u32 _emit_STZ(unsigned dry_run, u8 buf[]) |
| 815 | { |
| 816 | if (dry_run) |
| 817 | return SZ_DMASTZ; |
| 818 | |
| 819 | buf[0] = CMD_DMASTZ; |
| 820 | |
| 821 | PL330_DBGCMD_DUMP(SZ_DMASTZ, "\tDMASTZ\n"); |
| 822 | |
| 823 | return SZ_DMASTZ; |
| 824 | } |
| 825 | |
| 826 | static inline u32 _emit_WFE(unsigned dry_run, u8 buf[], u8 ev, |
| 827 | unsigned invalidate) |
| 828 | { |
| 829 | if (dry_run) |
| 830 | return SZ_DMAWFE; |
| 831 | |
| 832 | buf[0] = CMD_DMAWFE; |
| 833 | |
| 834 | ev &= 0x1f; |
| 835 | ev <<= 3; |
| 836 | buf[1] = ev; |
| 837 | |
| 838 | if (invalidate) |
| 839 | buf[1] |= (1 << 1); |
| 840 | |
| 841 | PL330_DBGCMD_DUMP(SZ_DMAWFE, "\tDMAWFE %u%s\n", |
| 842 | ev >> 3, invalidate ? ", I" : ""); |
| 843 | |
| 844 | return SZ_DMAWFE; |
| 845 | } |
| 846 | |
| 847 | static inline u32 _emit_WFP(unsigned dry_run, u8 buf[], |
| 848 | enum pl330_cond cond, u8 peri) |
| 849 | { |
| 850 | if (dry_run) |
| 851 | return SZ_DMAWFP; |
| 852 | |
| 853 | buf[0] = CMD_DMAWFP; |
| 854 | |
| 855 | if (cond == SINGLE) |
| 856 | buf[0] |= (0 << 1) | (0 << 0); |
| 857 | else if (cond == BURST) |
| 858 | buf[0] |= (1 << 1) | (0 << 0); |
| 859 | else |
| 860 | buf[0] |= (0 << 1) | (1 << 0); |
| 861 | |
| 862 | peri &= 0x1f; |
| 863 | peri <<= 3; |
| 864 | buf[1] = peri; |
| 865 | |
| 866 | PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n", |
| 867 | cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3); |
| 868 | |
| 869 | return SZ_DMAWFP; |
| 870 | } |
| 871 | |
| 872 | static inline u32 _emit_WMB(unsigned dry_run, u8 buf[]) |
| 873 | { |
| 874 | if (dry_run) |
| 875 | return SZ_DMAWMB; |
| 876 | |
| 877 | buf[0] = CMD_DMAWMB; |
| 878 | |
| 879 | PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n"); |
| 880 | |
| 881 | return SZ_DMAWMB; |
| 882 | } |
| 883 | |
| 884 | struct _arg_GO { |
| 885 | u8 chan; |
| 886 | u32 addr; |
| 887 | unsigned ns; |
| 888 | }; |
| 889 | |
| 890 | static inline u32 _emit_GO(unsigned dry_run, u8 buf[], |
| 891 | const struct _arg_GO *arg) |
| 892 | { |
| 893 | u8 chan = arg->chan; |
| 894 | u32 addr = arg->addr; |
| 895 | unsigned ns = arg->ns; |
| 896 | |
| 897 | if (dry_run) |
| 898 | return SZ_DMAGO; |
| 899 | |
| 900 | buf[0] = CMD_DMAGO; |
| 901 | buf[0] |= (ns << 1); |
| 902 | |
| 903 | buf[1] = chan & 0x7; |
| 904 | |
Ben Dooks | 3a2307f | 2015-03-16 11:52:43 +0000 | [diff] [blame] | 905 | *((__le32 *)&buf[2]) = cpu_to_le32(addr); |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 906 | |
| 907 | return SZ_DMAGO; |
| 908 | } |
| 909 | |
| 910 | #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) |
| 911 | |
| 912 | /* Returns Time-Out */ |
| 913 | static bool _until_dmac_idle(struct pl330_thread *thrd) |
| 914 | { |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 915 | void __iomem *regs = thrd->dmac->base; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 916 | unsigned long loops = msecs_to_loops(5); |
| 917 | |
| 918 | do { |
| 919 | /* Until Manager is Idle */ |
| 920 | if (!(readl(regs + DBGSTATUS) & DBG_BUSY)) |
| 921 | break; |
| 922 | |
| 923 | cpu_relax(); |
| 924 | } while (--loops); |
| 925 | |
| 926 | if (!loops) |
| 927 | return true; |
| 928 | |
| 929 | return false; |
| 930 | } |
| 931 | |
| 932 | static inline void _execute_DBGINSN(struct pl330_thread *thrd, |
| 933 | u8 insn[], bool as_manager) |
| 934 | { |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 935 | void __iomem *regs = thrd->dmac->base; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 936 | u32 val; |
| 937 | |
| 938 | val = (insn[0] << 16) | (insn[1] << 24); |
| 939 | if (!as_manager) { |
| 940 | val |= (1 << 0); |
| 941 | val |= (thrd->id << 8); /* Channel Number */ |
| 942 | } |
| 943 | writel(val, regs + DBGINST0); |
| 944 | |
Ben Dooks | 3a2307f | 2015-03-16 11:52:43 +0000 | [diff] [blame] | 945 | val = le32_to_cpu(*((__le32 *)&insn[2])); |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 946 | writel(val, regs + DBGINST1); |
| 947 | |
| 948 | /* If timed out due to halted state-machine */ |
| 949 | if (_until_dmac_idle(thrd)) { |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 950 | dev_err(thrd->dmac->ddma.dev, "DMAC halted!\n"); |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 951 | return; |
| 952 | } |
| 953 | |
| 954 | /* Get going */ |
| 955 | writel(0, regs + DBGCMD); |
| 956 | } |
| 957 | |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 958 | static inline u32 _state(struct pl330_thread *thrd) |
| 959 | { |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 960 | void __iomem *regs = thrd->dmac->base; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 961 | u32 val; |
| 962 | |
| 963 | if (is_manager(thrd)) |
| 964 | val = readl(regs + DS) & 0xf; |
| 965 | else |
| 966 | val = readl(regs + CS(thrd->id)) & 0xf; |
| 967 | |
| 968 | switch (val) { |
| 969 | case DS_ST_STOP: |
| 970 | return PL330_STATE_STOPPED; |
| 971 | case DS_ST_EXEC: |
| 972 | return PL330_STATE_EXECUTING; |
| 973 | case DS_ST_CMISS: |
| 974 | return PL330_STATE_CACHEMISS; |
| 975 | case DS_ST_UPDTPC: |
| 976 | return PL330_STATE_UPDTPC; |
| 977 | case DS_ST_WFE: |
| 978 | return PL330_STATE_WFE; |
| 979 | case DS_ST_FAULT: |
| 980 | return PL330_STATE_FAULTING; |
| 981 | case DS_ST_ATBRR: |
| 982 | if (is_manager(thrd)) |
| 983 | return PL330_STATE_INVALID; |
| 984 | else |
| 985 | return PL330_STATE_ATBARRIER; |
| 986 | case DS_ST_QBUSY: |
| 987 | if (is_manager(thrd)) |
| 988 | return PL330_STATE_INVALID; |
| 989 | else |
| 990 | return PL330_STATE_QUEUEBUSY; |
| 991 | case DS_ST_WFP: |
| 992 | if (is_manager(thrd)) |
| 993 | return PL330_STATE_INVALID; |
| 994 | else |
| 995 | return PL330_STATE_WFP; |
| 996 | case DS_ST_KILL: |
| 997 | if (is_manager(thrd)) |
| 998 | return PL330_STATE_INVALID; |
| 999 | else |
| 1000 | return PL330_STATE_KILLING; |
| 1001 | case DS_ST_CMPLT: |
| 1002 | if (is_manager(thrd)) |
| 1003 | return PL330_STATE_INVALID; |
| 1004 | else |
| 1005 | return PL330_STATE_COMPLETING; |
| 1006 | case DS_ST_FLTCMP: |
| 1007 | if (is_manager(thrd)) |
| 1008 | return PL330_STATE_INVALID; |
| 1009 | else |
| 1010 | return PL330_STATE_FAULT_COMPLETING; |
| 1011 | default: |
| 1012 | return PL330_STATE_INVALID; |
| 1013 | } |
| 1014 | } |
| 1015 | |
| 1016 | static void _stop(struct pl330_thread *thrd) |
| 1017 | { |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1018 | void __iomem *regs = thrd->dmac->base; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1019 | u8 insn[6] = {0, 0, 0, 0, 0, 0}; |
| 1020 | |
| 1021 | if (_state(thrd) == PL330_STATE_FAULT_COMPLETING) |
| 1022 | UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING); |
| 1023 | |
| 1024 | /* Return if nothing needs to be done */ |
| 1025 | if (_state(thrd) == PL330_STATE_COMPLETING |
| 1026 | || _state(thrd) == PL330_STATE_KILLING |
| 1027 | || _state(thrd) == PL330_STATE_STOPPED) |
| 1028 | return; |
| 1029 | |
| 1030 | _emit_KILL(0, insn); |
| 1031 | |
| 1032 | /* Stop generating interrupts for SEV */ |
| 1033 | writel(readl(regs + INTEN) & ~(1 << thrd->ev), regs + INTEN); |
| 1034 | |
| 1035 | _execute_DBGINSN(thrd, insn, is_manager(thrd)); |
| 1036 | } |
| 1037 | |
| 1038 | /* Start doing req 'idx' of thread 'thrd' */ |
| 1039 | static bool _trigger(struct pl330_thread *thrd) |
| 1040 | { |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1041 | void __iomem *regs = thrd->dmac->base; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1042 | struct _pl330_req *req; |
Lars-Peter Clausen | 9dc5a31 | 2014-07-06 20:32:30 +0200 | [diff] [blame] | 1043 | struct dma_pl330_desc *desc; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1044 | struct _arg_GO go; |
| 1045 | unsigned ns; |
| 1046 | u8 insn[6] = {0, 0, 0, 0, 0, 0}; |
| 1047 | int idx; |
| 1048 | |
| 1049 | /* Return if already ACTIVE */ |
| 1050 | if (_state(thrd) != PL330_STATE_STOPPED) |
| 1051 | return true; |
| 1052 | |
| 1053 | idx = 1 - thrd->lstenq; |
Lars-Peter Clausen | 8ed30a1 | 2014-07-06 20:32:31 +0200 | [diff] [blame] | 1054 | if (thrd->req[idx].desc != NULL) { |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1055 | req = &thrd->req[idx]; |
Lars-Peter Clausen | 8ed30a1 | 2014-07-06 20:32:31 +0200 | [diff] [blame] | 1056 | } else { |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1057 | idx = thrd->lstenq; |
Lars-Peter Clausen | 8ed30a1 | 2014-07-06 20:32:31 +0200 | [diff] [blame] | 1058 | if (thrd->req[idx].desc != NULL) |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1059 | req = &thrd->req[idx]; |
| 1060 | else |
| 1061 | req = NULL; |
| 1062 | } |
| 1063 | |
| 1064 | /* Return if no request */ |
Lars-Peter Clausen | 8ed30a1 | 2014-07-06 20:32:31 +0200 | [diff] [blame] | 1065 | if (!req) |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1066 | return true; |
| 1067 | |
Addy Ke | 0091b9d | 2014-12-08 19:28:20 +0800 | [diff] [blame] | 1068 | /* Return if req is running */ |
| 1069 | if (idx == thrd->req_running) |
| 1070 | return true; |
| 1071 | |
Lars-Peter Clausen | 9dc5a31 | 2014-07-06 20:32:30 +0200 | [diff] [blame] | 1072 | desc = req->desc; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1073 | |
Lars-Peter Clausen | 9dc5a31 | 2014-07-06 20:32:30 +0200 | [diff] [blame] | 1074 | ns = desc->rqcfg.nonsecure ? 1 : 0; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1075 | |
| 1076 | /* See 'Abort Sources' point-4 at Page 2-25 */ |
| 1077 | if (_manager_ns(thrd) && !ns) |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1078 | dev_info(thrd->dmac->ddma.dev, "%s:%d Recipe for ABORT!\n", |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1079 | __func__, __LINE__); |
| 1080 | |
| 1081 | go.chan = thrd->id; |
| 1082 | go.addr = req->mc_bus; |
| 1083 | go.ns = ns; |
| 1084 | _emit_GO(0, insn, &go); |
| 1085 | |
| 1086 | /* Set to generate interrupts for SEV */ |
| 1087 | writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN); |
| 1088 | |
| 1089 | /* Only manager can execute GO */ |
| 1090 | _execute_DBGINSN(thrd, insn, true); |
| 1091 | |
| 1092 | thrd->req_running = idx; |
| 1093 | |
| 1094 | return true; |
| 1095 | } |
| 1096 | |
| 1097 | static bool _start(struct pl330_thread *thrd) |
| 1098 | { |
| 1099 | switch (_state(thrd)) { |
| 1100 | case PL330_STATE_FAULT_COMPLETING: |
| 1101 | UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING); |
| 1102 | |
| 1103 | if (_state(thrd) == PL330_STATE_KILLING) |
| 1104 | UNTIL(thrd, PL330_STATE_STOPPED) |
| 1105 | |
| 1106 | case PL330_STATE_FAULTING: |
| 1107 | _stop(thrd); |
| 1108 | |
| 1109 | case PL330_STATE_KILLING: |
| 1110 | case PL330_STATE_COMPLETING: |
| 1111 | UNTIL(thrd, PL330_STATE_STOPPED) |
| 1112 | |
| 1113 | case PL330_STATE_STOPPED: |
| 1114 | return _trigger(thrd); |
| 1115 | |
| 1116 | case PL330_STATE_WFP: |
| 1117 | case PL330_STATE_QUEUEBUSY: |
| 1118 | case PL330_STATE_ATBARRIER: |
| 1119 | case PL330_STATE_UPDTPC: |
| 1120 | case PL330_STATE_CACHEMISS: |
| 1121 | case PL330_STATE_EXECUTING: |
| 1122 | return true; |
| 1123 | |
| 1124 | case PL330_STATE_WFE: /* For RESUME, nothing yet */ |
| 1125 | default: |
| 1126 | return false; |
| 1127 | } |
| 1128 | } |
| 1129 | |
| 1130 | static inline int _ldst_memtomem(unsigned dry_run, u8 buf[], |
| 1131 | const struct _xfer_spec *pxs, int cyc) |
| 1132 | { |
| 1133 | int off = 0; |
Lars-Peter Clausen | 9dc5a31 | 2014-07-06 20:32:30 +0200 | [diff] [blame] | 1134 | struct pl330_config *pcfg = pxs->desc->rqcfg.pcfg; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1135 | |
Boojin Kim | 3ecf51a | 2011-12-26 18:55:47 +0900 | [diff] [blame] | 1136 | /* check lock-up free version */ |
| 1137 | if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) { |
| 1138 | while (cyc--) { |
| 1139 | off += _emit_LD(dry_run, &buf[off], ALWAYS); |
| 1140 | off += _emit_ST(dry_run, &buf[off], ALWAYS); |
| 1141 | } |
| 1142 | } else { |
| 1143 | while (cyc--) { |
| 1144 | off += _emit_LD(dry_run, &buf[off], ALWAYS); |
| 1145 | off += _emit_RMB(dry_run, &buf[off]); |
| 1146 | off += _emit_ST(dry_run, &buf[off], ALWAYS); |
| 1147 | off += _emit_WMB(dry_run, &buf[off]); |
| 1148 | } |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1149 | } |
| 1150 | |
| 1151 | return off; |
| 1152 | } |
| 1153 | |
Addy Ke | 271e1b86 | 2016-01-22 19:06:46 +0800 | [diff] [blame] | 1154 | static inline int _ldst_devtomem(struct pl330_dmac *pl330, unsigned dry_run, |
| 1155 | u8 buf[], const struct _xfer_spec *pxs, |
| 1156 | int cyc) |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1157 | { |
| 1158 | int off = 0; |
Boojin Kim | 848e977 | 2016-01-22 19:06:44 +0800 | [diff] [blame] | 1159 | enum pl330_cond cond; |
| 1160 | |
Addy Ke | 271e1b86 | 2016-01-22 19:06:46 +0800 | [diff] [blame] | 1161 | if (pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP) |
| 1162 | cond = BURST; |
| 1163 | else |
Caesar Wang | 0a18f9b | 2016-02-25 09:00:53 +0800 | [diff] [blame] | 1164 | cond = SINGLE; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1165 | |
| 1166 | while (cyc--) { |
Boojin Kim | 848e977 | 2016-01-22 19:06:44 +0800 | [diff] [blame] | 1167 | off += _emit_WFP(dry_run, &buf[off], cond, pxs->desc->peri); |
| 1168 | off += _emit_LDP(dry_run, &buf[off], cond, pxs->desc->peri); |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1169 | off += _emit_ST(dry_run, &buf[off], ALWAYS); |
Addy Ke | 271e1b86 | 2016-01-22 19:06:46 +0800 | [diff] [blame] | 1170 | |
| 1171 | if (!(pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP)) |
| 1172 | off += _emit_FLUSHP(dry_run, &buf[off], |
| 1173 | pxs->desc->peri); |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1174 | } |
| 1175 | |
| 1176 | return off; |
| 1177 | } |
| 1178 | |
Addy Ke | 271e1b86 | 2016-01-22 19:06:46 +0800 | [diff] [blame] | 1179 | static inline int _ldst_memtodev(struct pl330_dmac *pl330, |
| 1180 | unsigned dry_run, u8 buf[], |
| 1181 | const struct _xfer_spec *pxs, int cyc) |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1182 | { |
| 1183 | int off = 0; |
Boojin Kim | 848e977 | 2016-01-22 19:06:44 +0800 | [diff] [blame] | 1184 | enum pl330_cond cond; |
| 1185 | |
Addy Ke | 271e1b86 | 2016-01-22 19:06:46 +0800 | [diff] [blame] | 1186 | if (pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP) |
| 1187 | cond = BURST; |
| 1188 | else |
Caesar Wang | 0a18f9b | 2016-02-25 09:00:53 +0800 | [diff] [blame] | 1189 | cond = SINGLE; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1190 | |
| 1191 | while (cyc--) { |
Boojin Kim | 848e977 | 2016-01-22 19:06:44 +0800 | [diff] [blame] | 1192 | off += _emit_WFP(dry_run, &buf[off], cond, pxs->desc->peri); |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1193 | off += _emit_LD(dry_run, &buf[off], ALWAYS); |
Boojin Kim | 848e977 | 2016-01-22 19:06:44 +0800 | [diff] [blame] | 1194 | off += _emit_STP(dry_run, &buf[off], cond, pxs->desc->peri); |
Addy Ke | 271e1b86 | 2016-01-22 19:06:46 +0800 | [diff] [blame] | 1195 | |
| 1196 | if (!(pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP)) |
| 1197 | off += _emit_FLUSHP(dry_run, &buf[off], |
| 1198 | pxs->desc->peri); |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1199 | } |
| 1200 | |
| 1201 | return off; |
| 1202 | } |
| 1203 | |
Addy Ke | 271e1b86 | 2016-01-22 19:06:46 +0800 | [diff] [blame] | 1204 | static int _bursts(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[], |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1205 | const struct _xfer_spec *pxs, int cyc) |
| 1206 | { |
| 1207 | int off = 0; |
| 1208 | |
Lars-Peter Clausen | 9dc5a31 | 2014-07-06 20:32:30 +0200 | [diff] [blame] | 1209 | switch (pxs->desc->rqtype) { |
Lars-Peter Clausen | 585a9d0 | 2014-07-06 20:32:18 +0200 | [diff] [blame] | 1210 | case DMA_MEM_TO_DEV: |
Addy Ke | 271e1b86 | 2016-01-22 19:06:46 +0800 | [diff] [blame] | 1211 | off += _ldst_memtodev(pl330, dry_run, &buf[off], pxs, cyc); |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1212 | break; |
Lars-Peter Clausen | 585a9d0 | 2014-07-06 20:32:18 +0200 | [diff] [blame] | 1213 | case DMA_DEV_TO_MEM: |
Addy Ke | 271e1b86 | 2016-01-22 19:06:46 +0800 | [diff] [blame] | 1214 | off += _ldst_devtomem(pl330, dry_run, &buf[off], pxs, cyc); |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1215 | break; |
Lars-Peter Clausen | 585a9d0 | 2014-07-06 20:32:18 +0200 | [diff] [blame] | 1216 | case DMA_MEM_TO_MEM: |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1217 | off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc); |
| 1218 | break; |
| 1219 | default: |
| 1220 | off += 0x40000000; /* Scare off the Client */ |
| 1221 | break; |
| 1222 | } |
| 1223 | |
| 1224 | return off; |
| 1225 | } |
| 1226 | |
| 1227 | /* Returns bytes consumed and updates bursts */ |
Addy Ke | 271e1b86 | 2016-01-22 19:06:46 +0800 | [diff] [blame] | 1228 | static inline int _loop(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[], |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1229 | unsigned long *bursts, const struct _xfer_spec *pxs) |
| 1230 | { |
| 1231 | int cyc, cycmax, szlp, szlpend, szbrst, off; |
| 1232 | unsigned lcnt0, lcnt1, ljmp0, ljmp1; |
| 1233 | struct _arg_LPEND lpend; |
| 1234 | |
Michal Suchanek | 31495d6 | 2015-07-23 18:04:49 +0200 | [diff] [blame] | 1235 | if (*bursts == 1) |
Boojin Kim | 848e977 | 2016-01-22 19:06:44 +0800 | [diff] [blame] | 1236 | return _bursts(pl330, dry_run, buf, pxs, 1); |
Michal Suchanek | 31495d6 | 2015-07-23 18:04:49 +0200 | [diff] [blame] | 1237 | |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1238 | /* Max iterations possible in DMALP is 256 */ |
| 1239 | if (*bursts >= 256*256) { |
| 1240 | lcnt1 = 256; |
| 1241 | lcnt0 = 256; |
| 1242 | cyc = *bursts / lcnt1 / lcnt0; |
| 1243 | } else if (*bursts > 256) { |
| 1244 | lcnt1 = 256; |
| 1245 | lcnt0 = *bursts / lcnt1; |
| 1246 | cyc = 1; |
| 1247 | } else { |
| 1248 | lcnt1 = *bursts; |
| 1249 | lcnt0 = 0; |
| 1250 | cyc = 1; |
| 1251 | } |
| 1252 | |
| 1253 | szlp = _emit_LP(1, buf, 0, 0); |
Addy Ke | 271e1b86 | 2016-01-22 19:06:46 +0800 | [diff] [blame] | 1254 | szbrst = _bursts(pl330, 1, buf, pxs, 1); |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1255 | |
| 1256 | lpend.cond = ALWAYS; |
| 1257 | lpend.forever = false; |
| 1258 | lpend.loop = 0; |
| 1259 | lpend.bjump = 0; |
| 1260 | szlpend = _emit_LPEND(1, buf, &lpend); |
| 1261 | |
| 1262 | if (lcnt0) { |
| 1263 | szlp *= 2; |
| 1264 | szlpend *= 2; |
| 1265 | } |
| 1266 | |
| 1267 | /* |
| 1268 | * Max bursts that we can unroll due to limit on the |
| 1269 | * size of backward jump that can be encoded in DMALPEND |
| 1270 | * which is 8-bits and hence 255 |
| 1271 | */ |
| 1272 | cycmax = (255 - (szlp + szlpend)) / szbrst; |
| 1273 | |
| 1274 | cyc = (cycmax < cyc) ? cycmax : cyc; |
| 1275 | |
| 1276 | off = 0; |
| 1277 | |
| 1278 | if (lcnt0) { |
| 1279 | off += _emit_LP(dry_run, &buf[off], 0, lcnt0); |
| 1280 | ljmp0 = off; |
| 1281 | } |
| 1282 | |
| 1283 | off += _emit_LP(dry_run, &buf[off], 1, lcnt1); |
| 1284 | ljmp1 = off; |
| 1285 | |
Addy Ke | 271e1b86 | 2016-01-22 19:06:46 +0800 | [diff] [blame] | 1286 | off += _bursts(pl330, dry_run, &buf[off], pxs, cyc); |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1287 | |
| 1288 | lpend.cond = ALWAYS; |
| 1289 | lpend.forever = false; |
| 1290 | lpend.loop = 1; |
| 1291 | lpend.bjump = off - ljmp1; |
| 1292 | off += _emit_LPEND(dry_run, &buf[off], &lpend); |
| 1293 | |
| 1294 | if (lcnt0) { |
| 1295 | lpend.cond = ALWAYS; |
| 1296 | lpend.forever = false; |
| 1297 | lpend.loop = 0; |
| 1298 | lpend.bjump = off - ljmp0; |
| 1299 | off += _emit_LPEND(dry_run, &buf[off], &lpend); |
| 1300 | } |
| 1301 | |
| 1302 | *bursts = lcnt1 * cyc; |
| 1303 | if (lcnt0) |
| 1304 | *bursts *= lcnt0; |
| 1305 | |
| 1306 | return off; |
| 1307 | } |
| 1308 | |
Addy Ke | 271e1b86 | 2016-01-22 19:06:46 +0800 | [diff] [blame] | 1309 | static inline int _setup_loops(struct pl330_dmac *pl330, |
| 1310 | unsigned dry_run, u8 buf[], |
| 1311 | const struct _xfer_spec *pxs) |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1312 | { |
Lars-Peter Clausen | 9dc5a31 | 2014-07-06 20:32:30 +0200 | [diff] [blame] | 1313 | struct pl330_xfer *x = &pxs->desc->px; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1314 | u32 ccr = pxs->ccr; |
| 1315 | unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr); |
| 1316 | int off = 0; |
| 1317 | |
| 1318 | while (bursts) { |
| 1319 | c = bursts; |
Addy Ke | 271e1b86 | 2016-01-22 19:06:46 +0800 | [diff] [blame] | 1320 | off += _loop(pl330, dry_run, &buf[off], &c, pxs); |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1321 | bursts -= c; |
| 1322 | } |
| 1323 | |
| 1324 | return off; |
| 1325 | } |
| 1326 | |
Addy Ke | 271e1b86 | 2016-01-22 19:06:46 +0800 | [diff] [blame] | 1327 | static inline int _setup_xfer(struct pl330_dmac *pl330, |
| 1328 | unsigned dry_run, u8 buf[], |
| 1329 | const struct _xfer_spec *pxs) |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1330 | { |
Lars-Peter Clausen | 9dc5a31 | 2014-07-06 20:32:30 +0200 | [diff] [blame] | 1331 | struct pl330_xfer *x = &pxs->desc->px; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1332 | int off = 0; |
| 1333 | |
| 1334 | /* DMAMOV SAR, x->src_addr */ |
| 1335 | off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr); |
| 1336 | /* DMAMOV DAR, x->dst_addr */ |
| 1337 | off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr); |
| 1338 | |
| 1339 | /* Setup Loop(s) */ |
Addy Ke | 271e1b86 | 2016-01-22 19:06:46 +0800 | [diff] [blame] | 1340 | off += _setup_loops(pl330, dry_run, &buf[off], pxs); |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1341 | |
| 1342 | return off; |
| 1343 | } |
| 1344 | |
| 1345 | /* |
| 1346 | * A req is a sequence of one or more xfer units. |
| 1347 | * Returns the number of bytes taken to setup the MC for the req. |
| 1348 | */ |
Addy Ke | 271e1b86 | 2016-01-22 19:06:46 +0800 | [diff] [blame] | 1349 | static int _setup_req(struct pl330_dmac *pl330, unsigned dry_run, |
| 1350 | struct pl330_thread *thrd, unsigned index, |
| 1351 | struct _xfer_spec *pxs) |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1352 | { |
| 1353 | struct _pl330_req *req = &thrd->req[index]; |
| 1354 | struct pl330_xfer *x; |
| 1355 | u8 *buf = req->mc_cpu; |
| 1356 | int off = 0; |
| 1357 | |
| 1358 | PL330_DBGMC_START(req->mc_bus); |
| 1359 | |
| 1360 | /* DMAMOV CCR, ccr */ |
| 1361 | off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr); |
| 1362 | |
Lars-Peter Clausen | 9dc5a31 | 2014-07-06 20:32:30 +0200 | [diff] [blame] | 1363 | x = &pxs->desc->px; |
Lars-Peter Clausen | d5cef12 | 2014-07-06 20:32:23 +0200 | [diff] [blame] | 1364 | /* Error if xfer length is not aligned at burst size */ |
| 1365 | if (x->bytes % (BRST_SIZE(pxs->ccr) * BRST_LEN(pxs->ccr))) |
| 1366 | return -EINVAL; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1367 | |
Addy Ke | 271e1b86 | 2016-01-22 19:06:46 +0800 | [diff] [blame] | 1368 | off += _setup_xfer(pl330, dry_run, &buf[off], pxs); |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1369 | |
| 1370 | /* DMASEV peripheral/event */ |
| 1371 | off += _emit_SEV(dry_run, &buf[off], thrd->ev); |
| 1372 | /* DMAEND */ |
| 1373 | off += _emit_END(dry_run, &buf[off]); |
| 1374 | |
| 1375 | return off; |
| 1376 | } |
| 1377 | |
| 1378 | static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc) |
| 1379 | { |
| 1380 | u32 ccr = 0; |
| 1381 | |
| 1382 | if (rqc->src_inc) |
| 1383 | ccr |= CC_SRCINC; |
| 1384 | |
| 1385 | if (rqc->dst_inc) |
| 1386 | ccr |= CC_DSTINC; |
| 1387 | |
| 1388 | /* We set same protection levels for Src and DST for now */ |
| 1389 | if (rqc->privileged) |
| 1390 | ccr |= CC_SRCPRI | CC_DSTPRI; |
| 1391 | if (rqc->nonsecure) |
| 1392 | ccr |= CC_SRCNS | CC_DSTNS; |
| 1393 | if (rqc->insnaccess) |
| 1394 | ccr |= CC_SRCIA | CC_DSTIA; |
| 1395 | |
| 1396 | ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT); |
| 1397 | ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT); |
| 1398 | |
| 1399 | ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT); |
| 1400 | ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT); |
| 1401 | |
| 1402 | ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT); |
| 1403 | ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT); |
| 1404 | |
| 1405 | ccr |= (rqc->swap << CC_SWAP_SHFT); |
| 1406 | |
| 1407 | return ccr; |
| 1408 | } |
| 1409 | |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1410 | /* |
| 1411 | * Submit a list of xfers after which the client wants notification. |
| 1412 | * Client is not notified after each xfer unit, just once after all |
| 1413 | * xfer units are done or some error occurs. |
| 1414 | */ |
Lars-Peter Clausen | 9dc5a31 | 2014-07-06 20:32:30 +0200 | [diff] [blame] | 1415 | static int pl330_submit_req(struct pl330_thread *thrd, |
| 1416 | struct dma_pl330_desc *desc) |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1417 | { |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1418 | struct pl330_dmac *pl330 = thrd->dmac; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1419 | struct _xfer_spec xs; |
| 1420 | unsigned long flags; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1421 | unsigned idx; |
| 1422 | u32 ccr; |
| 1423 | int ret = 0; |
| 1424 | |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1425 | if (pl330->state == DYING |
| 1426 | || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) { |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1427 | dev_info(thrd->dmac->ddma.dev, "%s:%d\n", |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1428 | __func__, __LINE__); |
| 1429 | return -EAGAIN; |
| 1430 | } |
| 1431 | |
| 1432 | /* If request for non-existing peripheral */ |
Lars-Peter Clausen | 9dc5a31 | 2014-07-06 20:32:30 +0200 | [diff] [blame] | 1433 | if (desc->rqtype != DMA_MEM_TO_MEM && |
| 1434 | desc->peri >= pl330->pcfg.num_peri) { |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1435 | dev_info(thrd->dmac->ddma.dev, |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1436 | "%s:%d Invalid peripheral(%u)!\n", |
Lars-Peter Clausen | 9dc5a31 | 2014-07-06 20:32:30 +0200 | [diff] [blame] | 1437 | __func__, __LINE__, desc->peri); |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1438 | return -EINVAL; |
| 1439 | } |
| 1440 | |
| 1441 | spin_lock_irqsave(&pl330->lock, flags); |
| 1442 | |
| 1443 | if (_queue_full(thrd)) { |
| 1444 | ret = -EAGAIN; |
| 1445 | goto xfer_exit; |
| 1446 | } |
| 1447 | |
Lars-Peter Clausen | 9dc5a31 | 2014-07-06 20:32:30 +0200 | [diff] [blame] | 1448 | /* Prefer Secure Channel */ |
| 1449 | if (!_manager_ns(thrd)) |
| 1450 | desc->rqcfg.nonsecure = 0; |
| 1451 | else |
| 1452 | desc->rqcfg.nonsecure = 1; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1453 | |
Lars-Peter Clausen | 9dc5a31 | 2014-07-06 20:32:30 +0200 | [diff] [blame] | 1454 | ccr = _prepare_ccr(&desc->rqcfg); |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1455 | |
Lars-Peter Clausen | 8ed30a1 | 2014-07-06 20:32:31 +0200 | [diff] [blame] | 1456 | idx = thrd->req[0].desc == NULL ? 0 : 1; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1457 | |
| 1458 | xs.ccr = ccr; |
Lars-Peter Clausen | 9dc5a31 | 2014-07-06 20:32:30 +0200 | [diff] [blame] | 1459 | xs.desc = desc; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1460 | |
| 1461 | /* First dry run to check if req is acceptable */ |
Addy Ke | 271e1b86 | 2016-01-22 19:06:46 +0800 | [diff] [blame] | 1462 | ret = _setup_req(pl330, 1, thrd, idx, &xs); |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1463 | if (ret < 0) |
| 1464 | goto xfer_exit; |
| 1465 | |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1466 | if (ret > pl330->mcbufsz / 2) { |
Michal Suchanek | e5489d5 | 2015-06-03 21:26:41 +0000 | [diff] [blame] | 1467 | dev_info(pl330->ddma.dev, "%s:%d Try increasing mcbufsz (%i/%i)\n", |
| 1468 | __func__, __LINE__, ret, pl330->mcbufsz / 2); |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1469 | ret = -ENOMEM; |
| 1470 | goto xfer_exit; |
| 1471 | } |
| 1472 | |
| 1473 | /* Hook the request */ |
| 1474 | thrd->lstenq = idx; |
Lars-Peter Clausen | 9dc5a31 | 2014-07-06 20:32:30 +0200 | [diff] [blame] | 1475 | thrd->req[idx].desc = desc; |
Addy Ke | 271e1b86 | 2016-01-22 19:06:46 +0800 | [diff] [blame] | 1476 | _setup_req(pl330, 0, thrd, idx, &xs); |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1477 | |
| 1478 | ret = 0; |
| 1479 | |
| 1480 | xfer_exit: |
| 1481 | spin_unlock_irqrestore(&pl330->lock, flags); |
| 1482 | |
| 1483 | return ret; |
| 1484 | } |
| 1485 | |
Lars-Peter Clausen | 9dc5a31 | 2014-07-06 20:32:30 +0200 | [diff] [blame] | 1486 | static void dma_pl330_rqcb(struct dma_pl330_desc *desc, enum pl330_op_err err) |
Lars-Peter Clausen | 6079d38 | 2014-07-06 20:32:25 +0200 | [diff] [blame] | 1487 | { |
Javier Martinez Canillas | b1e51d7 | 2014-07-19 03:21:47 +0200 | [diff] [blame] | 1488 | struct dma_pl330_chan *pch; |
Lars-Peter Clausen | 6079d38 | 2014-07-06 20:32:25 +0200 | [diff] [blame] | 1489 | unsigned long flags; |
| 1490 | |
Javier Martinez Canillas | b1e51d7 | 2014-07-19 03:21:47 +0200 | [diff] [blame] | 1491 | if (!desc) |
| 1492 | return; |
| 1493 | |
| 1494 | pch = desc->pchan; |
| 1495 | |
Lars-Peter Clausen | 6079d38 | 2014-07-06 20:32:25 +0200 | [diff] [blame] | 1496 | /* If desc aborted */ |
| 1497 | if (!pch) |
| 1498 | return; |
| 1499 | |
| 1500 | spin_lock_irqsave(&pch->lock, flags); |
| 1501 | |
| 1502 | desc->status = DONE; |
| 1503 | |
| 1504 | spin_unlock_irqrestore(&pch->lock, flags); |
| 1505 | |
| 1506 | tasklet_schedule(&pch->task); |
| 1507 | } |
| 1508 | |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1509 | static void pl330_dotask(unsigned long data) |
| 1510 | { |
| 1511 | struct pl330_dmac *pl330 = (struct pl330_dmac *) data; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1512 | unsigned long flags; |
| 1513 | int i; |
| 1514 | |
| 1515 | spin_lock_irqsave(&pl330->lock, flags); |
| 1516 | |
| 1517 | /* The DMAC itself gone nuts */ |
| 1518 | if (pl330->dmac_tbd.reset_dmac) { |
| 1519 | pl330->state = DYING; |
| 1520 | /* Reset the manager too */ |
| 1521 | pl330->dmac_tbd.reset_mngr = true; |
| 1522 | /* Clear the reset flag */ |
| 1523 | pl330->dmac_tbd.reset_dmac = false; |
| 1524 | } |
| 1525 | |
| 1526 | if (pl330->dmac_tbd.reset_mngr) { |
| 1527 | _stop(pl330->manager); |
| 1528 | /* Reset all channels */ |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1529 | pl330->dmac_tbd.reset_chan = (1 << pl330->pcfg.num_chan) - 1; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1530 | /* Clear the reset flag */ |
| 1531 | pl330->dmac_tbd.reset_mngr = false; |
| 1532 | } |
| 1533 | |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1534 | for (i = 0; i < pl330->pcfg.num_chan; i++) { |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1535 | |
| 1536 | if (pl330->dmac_tbd.reset_chan & (1 << i)) { |
| 1537 | struct pl330_thread *thrd = &pl330->channels[i]; |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1538 | void __iomem *regs = pl330->base; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1539 | enum pl330_op_err err; |
| 1540 | |
| 1541 | _stop(thrd); |
| 1542 | |
| 1543 | if (readl(regs + FSC) & (1 << thrd->id)) |
| 1544 | err = PL330_ERR_FAIL; |
| 1545 | else |
| 1546 | err = PL330_ERR_ABORT; |
| 1547 | |
| 1548 | spin_unlock_irqrestore(&pl330->lock, flags); |
Lars-Peter Clausen | 9dc5a31 | 2014-07-06 20:32:30 +0200 | [diff] [blame] | 1549 | dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, err); |
| 1550 | dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, err); |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1551 | spin_lock_irqsave(&pl330->lock, flags); |
| 1552 | |
Lars-Peter Clausen | 9dc5a31 | 2014-07-06 20:32:30 +0200 | [diff] [blame] | 1553 | thrd->req[0].desc = NULL; |
| 1554 | thrd->req[1].desc = NULL; |
Lars-Peter Clausen | 8ed30a1 | 2014-07-06 20:32:31 +0200 | [diff] [blame] | 1555 | thrd->req_running = -1; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1556 | |
| 1557 | /* Clear the reset flag */ |
| 1558 | pl330->dmac_tbd.reset_chan &= ~(1 << i); |
| 1559 | } |
| 1560 | } |
| 1561 | |
| 1562 | spin_unlock_irqrestore(&pl330->lock, flags); |
| 1563 | |
| 1564 | return; |
| 1565 | } |
| 1566 | |
| 1567 | /* Returns 1 if state was updated, 0 otherwise */ |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1568 | static int pl330_update(struct pl330_dmac *pl330) |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1569 | { |
Lars-Peter Clausen | 9dc5a31 | 2014-07-06 20:32:30 +0200 | [diff] [blame] | 1570 | struct dma_pl330_desc *descdone, *tmp; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1571 | unsigned long flags; |
| 1572 | void __iomem *regs; |
| 1573 | u32 val; |
| 1574 | int id, ev, ret = 0; |
| 1575 | |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1576 | regs = pl330->base; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1577 | |
| 1578 | spin_lock_irqsave(&pl330->lock, flags); |
| 1579 | |
| 1580 | val = readl(regs + FSM) & 0x1; |
| 1581 | if (val) |
| 1582 | pl330->dmac_tbd.reset_mngr = true; |
| 1583 | else |
| 1584 | pl330->dmac_tbd.reset_mngr = false; |
| 1585 | |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1586 | val = readl(regs + FSC) & ((1 << pl330->pcfg.num_chan) - 1); |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1587 | pl330->dmac_tbd.reset_chan |= val; |
| 1588 | if (val) { |
| 1589 | int i = 0; |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1590 | while (i < pl330->pcfg.num_chan) { |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1591 | if (val & (1 << i)) { |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1592 | dev_info(pl330->ddma.dev, |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1593 | "Reset Channel-%d\t CS-%x FTC-%x\n", |
| 1594 | i, readl(regs + CS(i)), |
| 1595 | readl(regs + FTC(i))); |
| 1596 | _stop(&pl330->channels[i]); |
| 1597 | } |
| 1598 | i++; |
| 1599 | } |
| 1600 | } |
| 1601 | |
| 1602 | /* Check which event happened i.e, thread notified */ |
| 1603 | val = readl(regs + ES); |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1604 | if (pl330->pcfg.num_events < 32 |
| 1605 | && val & ~((1 << pl330->pcfg.num_events) - 1)) { |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1606 | pl330->dmac_tbd.reset_dmac = true; |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1607 | dev_err(pl330->ddma.dev, "%s:%d Unexpected!\n", __func__, |
| 1608 | __LINE__); |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1609 | ret = 1; |
| 1610 | goto updt_exit; |
| 1611 | } |
| 1612 | |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1613 | for (ev = 0; ev < pl330->pcfg.num_events; ev++) { |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1614 | if (val & (1 << ev)) { /* Event occurred */ |
| 1615 | struct pl330_thread *thrd; |
| 1616 | u32 inten = readl(regs + INTEN); |
| 1617 | int active; |
| 1618 | |
| 1619 | /* Clear the event */ |
| 1620 | if (inten & (1 << ev)) |
| 1621 | writel(1 << ev, regs + INTCLR); |
| 1622 | |
| 1623 | ret = 1; |
| 1624 | |
| 1625 | id = pl330->events[ev]; |
| 1626 | |
| 1627 | thrd = &pl330->channels[id]; |
| 1628 | |
| 1629 | active = thrd->req_running; |
| 1630 | if (active == -1) /* Aborted */ |
| 1631 | continue; |
| 1632 | |
Javi Merino | fdec53d | 2012-06-13 15:07:00 +0100 | [diff] [blame] | 1633 | /* Detach the req */ |
Lars-Peter Clausen | 9dc5a31 | 2014-07-06 20:32:30 +0200 | [diff] [blame] | 1634 | descdone = thrd->req[active].desc; |
| 1635 | thrd->req[active].desc = NULL; |
Javi Merino | fdec53d | 2012-06-13 15:07:00 +0100 | [diff] [blame] | 1636 | |
Addy Ke | 0091b9d | 2014-12-08 19:28:20 +0800 | [diff] [blame] | 1637 | thrd->req_running = -1; |
| 1638 | |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1639 | /* Get going again ASAP */ |
| 1640 | _start(thrd); |
| 1641 | |
| 1642 | /* For now, just make a list of callbacks to be done */ |
Lars-Peter Clausen | 9dc5a31 | 2014-07-06 20:32:30 +0200 | [diff] [blame] | 1643 | list_add_tail(&descdone->rqd, &pl330->req_done); |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1644 | } |
| 1645 | } |
| 1646 | |
| 1647 | /* Now that we are in no hurry, do the callbacks */ |
Lars-Peter Clausen | 9dc5a31 | 2014-07-06 20:32:30 +0200 | [diff] [blame] | 1648 | list_for_each_entry_safe(descdone, tmp, &pl330->req_done, rqd) { |
| 1649 | list_del(&descdone->rqd); |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1650 | spin_unlock_irqrestore(&pl330->lock, flags); |
Lars-Peter Clausen | 9dc5a31 | 2014-07-06 20:32:30 +0200 | [diff] [blame] | 1651 | dma_pl330_rqcb(descdone, PL330_ERR_NONE); |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1652 | spin_lock_irqsave(&pl330->lock, flags); |
| 1653 | } |
| 1654 | |
| 1655 | updt_exit: |
| 1656 | spin_unlock_irqrestore(&pl330->lock, flags); |
| 1657 | |
| 1658 | if (pl330->dmac_tbd.reset_dmac |
| 1659 | || pl330->dmac_tbd.reset_mngr |
| 1660 | || pl330->dmac_tbd.reset_chan) { |
| 1661 | ret = 1; |
| 1662 | tasklet_schedule(&pl330->tasks); |
| 1663 | } |
| 1664 | |
| 1665 | return ret; |
| 1666 | } |
| 1667 | |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1668 | /* Reserve an event */ |
| 1669 | static inline int _alloc_event(struct pl330_thread *thrd) |
| 1670 | { |
| 1671 | struct pl330_dmac *pl330 = thrd->dmac; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1672 | int ev; |
| 1673 | |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1674 | for (ev = 0; ev < pl330->pcfg.num_events; ev++) |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1675 | if (pl330->events[ev] == -1) { |
| 1676 | pl330->events[ev] = thrd->id; |
| 1677 | return ev; |
| 1678 | } |
| 1679 | |
| 1680 | return -1; |
| 1681 | } |
| 1682 | |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1683 | static bool _chan_ns(const struct pl330_dmac *pl330, int i) |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1684 | { |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1685 | return pl330->pcfg.irq_ns & (1 << i); |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1686 | } |
| 1687 | |
| 1688 | /* Upon success, returns IdentityToken for the |
| 1689 | * allocated channel, NULL otherwise. |
| 1690 | */ |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1691 | static struct pl330_thread *pl330_request_channel(struct pl330_dmac *pl330) |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1692 | { |
| 1693 | struct pl330_thread *thrd = NULL; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1694 | unsigned long flags; |
| 1695 | int chans, i; |
| 1696 | |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1697 | if (pl330->state == DYING) |
| 1698 | return NULL; |
| 1699 | |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1700 | chans = pl330->pcfg.num_chan; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1701 | |
| 1702 | spin_lock_irqsave(&pl330->lock, flags); |
| 1703 | |
| 1704 | for (i = 0; i < chans; i++) { |
| 1705 | thrd = &pl330->channels[i]; |
| 1706 | if ((thrd->free) && (!_manager_ns(thrd) || |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1707 | _chan_ns(pl330, i))) { |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1708 | thrd->ev = _alloc_event(thrd); |
| 1709 | if (thrd->ev >= 0) { |
| 1710 | thrd->free = false; |
| 1711 | thrd->lstenq = 1; |
Lars-Peter Clausen | 9dc5a31 | 2014-07-06 20:32:30 +0200 | [diff] [blame] | 1712 | thrd->req[0].desc = NULL; |
Lars-Peter Clausen | 9dc5a31 | 2014-07-06 20:32:30 +0200 | [diff] [blame] | 1713 | thrd->req[1].desc = NULL; |
Lars-Peter Clausen | 8ed30a1 | 2014-07-06 20:32:31 +0200 | [diff] [blame] | 1714 | thrd->req_running = -1; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1715 | break; |
| 1716 | } |
| 1717 | } |
| 1718 | thrd = NULL; |
| 1719 | } |
| 1720 | |
| 1721 | spin_unlock_irqrestore(&pl330->lock, flags); |
| 1722 | |
| 1723 | return thrd; |
| 1724 | } |
| 1725 | |
| 1726 | /* Release an event */ |
| 1727 | static inline void _free_event(struct pl330_thread *thrd, int ev) |
| 1728 | { |
| 1729 | struct pl330_dmac *pl330 = thrd->dmac; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1730 | |
| 1731 | /* If the event is valid and was held by the thread */ |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1732 | if (ev >= 0 && ev < pl330->pcfg.num_events |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1733 | && pl330->events[ev] == thrd->id) |
| 1734 | pl330->events[ev] = -1; |
| 1735 | } |
| 1736 | |
Lars-Peter Clausen | 65ad606 | 2014-07-06 20:32:26 +0200 | [diff] [blame] | 1737 | static void pl330_release_channel(struct pl330_thread *thrd) |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1738 | { |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1739 | struct pl330_dmac *pl330; |
| 1740 | unsigned long flags; |
| 1741 | |
| 1742 | if (!thrd || thrd->free) |
| 1743 | return; |
| 1744 | |
| 1745 | _stop(thrd); |
| 1746 | |
Lars-Peter Clausen | 9dc5a31 | 2014-07-06 20:32:30 +0200 | [diff] [blame] | 1747 | dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, PL330_ERR_ABORT); |
| 1748 | dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, PL330_ERR_ABORT); |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1749 | |
| 1750 | pl330 = thrd->dmac; |
| 1751 | |
| 1752 | spin_lock_irqsave(&pl330->lock, flags); |
| 1753 | _free_event(thrd, thrd->ev); |
| 1754 | thrd->free = true; |
| 1755 | spin_unlock_irqrestore(&pl330->lock, flags); |
| 1756 | } |
| 1757 | |
| 1758 | /* Initialize the structure for PL330 configuration, that can be used |
| 1759 | * by the client driver the make best use of the DMAC |
| 1760 | */ |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1761 | static void read_dmac_config(struct pl330_dmac *pl330) |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1762 | { |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1763 | void __iomem *regs = pl330->base; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1764 | u32 val; |
| 1765 | |
| 1766 | val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT; |
| 1767 | val &= CRD_DATA_WIDTH_MASK; |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1768 | pl330->pcfg.data_bus_width = 8 * (1 << val); |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1769 | |
| 1770 | val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT; |
| 1771 | val &= CRD_DATA_BUFF_MASK; |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1772 | pl330->pcfg.data_buf_dep = val + 1; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1773 | |
| 1774 | val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT; |
| 1775 | val &= CR0_NUM_CHANS_MASK; |
| 1776 | val += 1; |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1777 | pl330->pcfg.num_chan = val; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1778 | |
| 1779 | val = readl(regs + CR0); |
| 1780 | if (val & CR0_PERIPH_REQ_SET) { |
| 1781 | val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK; |
| 1782 | val += 1; |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1783 | pl330->pcfg.num_peri = val; |
| 1784 | pl330->pcfg.peri_ns = readl(regs + CR4); |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1785 | } else { |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1786 | pl330->pcfg.num_peri = 0; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1787 | } |
| 1788 | |
| 1789 | val = readl(regs + CR0); |
| 1790 | if (val & CR0_BOOT_MAN_NS) |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1791 | pl330->pcfg.mode |= DMAC_MODE_NS; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1792 | else |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1793 | pl330->pcfg.mode &= ~DMAC_MODE_NS; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1794 | |
| 1795 | val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT; |
| 1796 | val &= CR0_NUM_EVENTS_MASK; |
| 1797 | val += 1; |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1798 | pl330->pcfg.num_events = val; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1799 | |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1800 | pl330->pcfg.irq_ns = readl(regs + CR3); |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1801 | } |
| 1802 | |
| 1803 | static inline void _reset_thread(struct pl330_thread *thrd) |
| 1804 | { |
| 1805 | struct pl330_dmac *pl330 = thrd->dmac; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1806 | |
| 1807 | thrd->req[0].mc_cpu = pl330->mcode_cpu |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1808 | + (thrd->id * pl330->mcbufsz); |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1809 | thrd->req[0].mc_bus = pl330->mcode_bus |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1810 | + (thrd->id * pl330->mcbufsz); |
Lars-Peter Clausen | 9dc5a31 | 2014-07-06 20:32:30 +0200 | [diff] [blame] | 1811 | thrd->req[0].desc = NULL; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1812 | |
| 1813 | thrd->req[1].mc_cpu = thrd->req[0].mc_cpu |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1814 | + pl330->mcbufsz / 2; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1815 | thrd->req[1].mc_bus = thrd->req[0].mc_bus |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1816 | + pl330->mcbufsz / 2; |
Lars-Peter Clausen | 9dc5a31 | 2014-07-06 20:32:30 +0200 | [diff] [blame] | 1817 | thrd->req[1].desc = NULL; |
Lars-Peter Clausen | 8ed30a1 | 2014-07-06 20:32:31 +0200 | [diff] [blame] | 1818 | |
| 1819 | thrd->req_running = -1; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1820 | } |
| 1821 | |
| 1822 | static int dmac_alloc_threads(struct pl330_dmac *pl330) |
| 1823 | { |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1824 | int chans = pl330->pcfg.num_chan; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1825 | struct pl330_thread *thrd; |
| 1826 | int i; |
| 1827 | |
| 1828 | /* Allocate 1 Manager and 'chans' Channel threads */ |
| 1829 | pl330->channels = kzalloc((1 + chans) * sizeof(*thrd), |
| 1830 | GFP_KERNEL); |
| 1831 | if (!pl330->channels) |
| 1832 | return -ENOMEM; |
| 1833 | |
| 1834 | /* Init Channel threads */ |
| 1835 | for (i = 0; i < chans; i++) { |
| 1836 | thrd = &pl330->channels[i]; |
| 1837 | thrd->id = i; |
| 1838 | thrd->dmac = pl330; |
| 1839 | _reset_thread(thrd); |
| 1840 | thrd->free = true; |
| 1841 | } |
| 1842 | |
| 1843 | /* MANAGER is indexed at the end */ |
| 1844 | thrd = &pl330->channels[chans]; |
| 1845 | thrd->id = chans; |
| 1846 | thrd->dmac = pl330; |
| 1847 | thrd->free = false; |
| 1848 | pl330->manager = thrd; |
| 1849 | |
| 1850 | return 0; |
| 1851 | } |
| 1852 | |
| 1853 | static int dmac_alloc_resources(struct pl330_dmac *pl330) |
| 1854 | { |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1855 | int chans = pl330->pcfg.num_chan; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1856 | int ret; |
| 1857 | |
| 1858 | /* |
| 1859 | * Alloc MicroCode buffer for 'chans' Channel threads. |
| 1860 | * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN) |
| 1861 | */ |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1862 | pl330->mcode_cpu = dma_alloc_coherent(pl330->ddma.dev, |
| 1863 | chans * pl330->mcbufsz, |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1864 | &pl330->mcode_bus, GFP_KERNEL); |
| 1865 | if (!pl330->mcode_cpu) { |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1866 | dev_err(pl330->ddma.dev, "%s:%d Can't allocate memory!\n", |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1867 | __func__, __LINE__); |
| 1868 | return -ENOMEM; |
| 1869 | } |
| 1870 | |
| 1871 | ret = dmac_alloc_threads(pl330); |
| 1872 | if (ret) { |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1873 | dev_err(pl330->ddma.dev, "%s:%d Can't to create channels for DMAC!\n", |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1874 | __func__, __LINE__); |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1875 | dma_free_coherent(pl330->ddma.dev, |
| 1876 | chans * pl330->mcbufsz, |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1877 | pl330->mcode_cpu, pl330->mcode_bus); |
| 1878 | return ret; |
| 1879 | } |
| 1880 | |
| 1881 | return 0; |
| 1882 | } |
| 1883 | |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1884 | static int pl330_add(struct pl330_dmac *pl330) |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1885 | { |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1886 | void __iomem *regs; |
| 1887 | int i, ret; |
| 1888 | |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1889 | regs = pl330->base; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1890 | |
| 1891 | /* Check if we can handle this DMAC */ |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1892 | if ((pl330->pcfg.periph_id & 0xfffff) != PERIPH_ID_VAL) { |
| 1893 | dev_err(pl330->ddma.dev, "PERIPH_ID 0x%x !\n", |
| 1894 | pl330->pcfg.periph_id); |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1895 | return -EINVAL; |
| 1896 | } |
| 1897 | |
| 1898 | /* Read the configuration of the DMAC */ |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1899 | read_dmac_config(pl330); |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1900 | |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1901 | if (pl330->pcfg.num_events == 0) { |
| 1902 | dev_err(pl330->ddma.dev, "%s:%d Can't work without events!\n", |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1903 | __func__, __LINE__); |
| 1904 | return -EINVAL; |
| 1905 | } |
| 1906 | |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1907 | spin_lock_init(&pl330->lock); |
| 1908 | |
| 1909 | INIT_LIST_HEAD(&pl330->req_done); |
| 1910 | |
| 1911 | /* Use default MC buffer size if not provided */ |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1912 | if (!pl330->mcbufsz) |
| 1913 | pl330->mcbufsz = MCODE_BUFF_PER_REQ * 2; |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1914 | |
| 1915 | /* Mark all events as free */ |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1916 | for (i = 0; i < pl330->pcfg.num_events; i++) |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1917 | pl330->events[i] = -1; |
| 1918 | |
| 1919 | /* Allocate resources needed by the DMAC */ |
| 1920 | ret = dmac_alloc_resources(pl330); |
| 1921 | if (ret) { |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1922 | dev_err(pl330->ddma.dev, "Unable to create channels for DMAC\n"); |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1923 | return ret; |
| 1924 | } |
| 1925 | |
| 1926 | tasklet_init(&pl330->tasks, pl330_dotask, (unsigned long) pl330); |
| 1927 | |
| 1928 | pl330->state = INIT; |
| 1929 | |
| 1930 | return 0; |
| 1931 | } |
| 1932 | |
| 1933 | static int dmac_free_threads(struct pl330_dmac *pl330) |
| 1934 | { |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1935 | struct pl330_thread *thrd; |
| 1936 | int i; |
| 1937 | |
| 1938 | /* Release Channel threads */ |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1939 | for (i = 0; i < pl330->pcfg.num_chan; i++) { |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1940 | thrd = &pl330->channels[i]; |
Lars-Peter Clausen | 65ad606 | 2014-07-06 20:32:26 +0200 | [diff] [blame] | 1941 | pl330_release_channel(thrd); |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1942 | } |
| 1943 | |
| 1944 | /* Free memory */ |
| 1945 | kfree(pl330->channels); |
| 1946 | |
| 1947 | return 0; |
| 1948 | } |
| 1949 | |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1950 | static void pl330_del(struct pl330_dmac *pl330) |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1951 | { |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1952 | pl330->state = UNINIT; |
| 1953 | |
| 1954 | tasklet_kill(&pl330->tasks); |
| 1955 | |
| 1956 | /* Free DMAC resources */ |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1957 | dmac_free_threads(pl330); |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1958 | |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 1959 | dma_free_coherent(pl330->ddma.dev, |
| 1960 | pl330->pcfg.num_chan * pl330->mcbufsz, pl330->mcode_cpu, |
| 1961 | pl330->mcode_bus); |
Boojin Kim | b7d861d | 2011-12-26 18:49:52 +0900 | [diff] [blame] | 1962 | } |
| 1963 | |
Thomas Abraham | 3e2ec13 | 2011-10-24 11:43:02 +0200 | [diff] [blame] | 1964 | /* forward declaration */ |
| 1965 | static struct amba_driver pl330_driver; |
| 1966 | |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 1967 | static inline struct dma_pl330_chan * |
| 1968 | to_pchan(struct dma_chan *ch) |
| 1969 | { |
| 1970 | if (!ch) |
| 1971 | return NULL; |
| 1972 | |
| 1973 | return container_of(ch, struct dma_pl330_chan, chan); |
| 1974 | } |
| 1975 | |
| 1976 | static inline struct dma_pl330_desc * |
| 1977 | to_desc(struct dma_async_tx_descriptor *tx) |
| 1978 | { |
| 1979 | return container_of(tx, struct dma_pl330_desc, txd); |
| 1980 | } |
| 1981 | |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 1982 | static inline void fill_queue(struct dma_pl330_chan *pch) |
| 1983 | { |
| 1984 | struct dma_pl330_desc *desc; |
| 1985 | int ret; |
| 1986 | |
| 1987 | list_for_each_entry(desc, &pch->work_list, node) { |
| 1988 | |
| 1989 | /* If already submitted */ |
| 1990 | if (desc->status == BUSY) |
Jassi Brar | 30fb980 | 2013-02-13 16:13:14 +0530 | [diff] [blame] | 1991 | continue; |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 1992 | |
Lars-Peter Clausen | 9dc5a31 | 2014-07-06 20:32:30 +0200 | [diff] [blame] | 1993 | ret = pl330_submit_req(pch->thread, desc); |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 1994 | if (!ret) { |
| 1995 | desc->status = BUSY; |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 1996 | } else if (ret == -EAGAIN) { |
| 1997 | /* QFull or DMAC Dying */ |
| 1998 | break; |
| 1999 | } else { |
| 2000 | /* Unacceptable request */ |
| 2001 | desc->status = DONE; |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2002 | dev_err(pch->dmac->ddma.dev, "%s:%d Bad Desc(%d)\n", |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2003 | __func__, __LINE__, desc->txd.cookie); |
| 2004 | tasklet_schedule(&pch->task); |
| 2005 | } |
| 2006 | } |
| 2007 | } |
| 2008 | |
| 2009 | static void pl330_tasklet(unsigned long data) |
| 2010 | { |
| 2011 | struct dma_pl330_chan *pch = (struct dma_pl330_chan *)data; |
| 2012 | struct dma_pl330_desc *desc, *_dt; |
| 2013 | unsigned long flags; |
Krzysztof Kozlowski | ae43b32 | 2014-11-14 09:48:57 +0100 | [diff] [blame] | 2014 | bool power_down = false; |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2015 | |
| 2016 | spin_lock_irqsave(&pch->lock, flags); |
| 2017 | |
| 2018 | /* Pick up ripe tomatoes */ |
| 2019 | list_for_each_entry_safe(desc, _dt, &pch->work_list, node) |
| 2020 | if (desc->status == DONE) { |
Tushar Behera | 30c1dc0 | 2012-05-23 16:47:31 +0530 | [diff] [blame] | 2021 | if (!pch->cyclic) |
Vinod Koul | eab2158 | 2012-05-11 11:24:41 +0530 | [diff] [blame] | 2022 | dma_cookie_complete(&desc->txd); |
Lars-Peter Clausen | 39ff861 | 2013-08-27 20:34:05 +0200 | [diff] [blame] | 2023 | list_move_tail(&desc->node, &pch->completed_list); |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2024 | } |
| 2025 | |
| 2026 | /* Try to submit a req imm. next to the last completed cookie */ |
| 2027 | fill_queue(pch); |
| 2028 | |
Krzysztof Kozlowski | ae43b32 | 2014-11-14 09:48:57 +0100 | [diff] [blame] | 2029 | if (list_empty(&pch->work_list)) { |
| 2030 | spin_lock(&pch->thread->dmac->lock); |
| 2031 | _stop(pch->thread); |
| 2032 | spin_unlock(&pch->thread->dmac->lock); |
| 2033 | power_down = true; |
| 2034 | } else { |
| 2035 | /* Make sure the PL330 Channel thread is active */ |
| 2036 | spin_lock(&pch->thread->dmac->lock); |
| 2037 | _start(pch->thread); |
| 2038 | spin_unlock(&pch->thread->dmac->lock); |
| 2039 | } |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2040 | |
Lars-Peter Clausen | 39ff861 | 2013-08-27 20:34:05 +0200 | [diff] [blame] | 2041 | while (!list_empty(&pch->completed_list)) { |
| 2042 | dma_async_tx_callback callback; |
| 2043 | void *callback_param; |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2044 | |
Lars-Peter Clausen | 39ff861 | 2013-08-27 20:34:05 +0200 | [diff] [blame] | 2045 | desc = list_first_entry(&pch->completed_list, |
| 2046 | struct dma_pl330_desc, node); |
| 2047 | |
| 2048 | callback = desc->txd.callback; |
| 2049 | callback_param = desc->txd.callback_param; |
| 2050 | |
| 2051 | if (pch->cyclic) { |
| 2052 | desc->status = PREP; |
| 2053 | list_move_tail(&desc->node, &pch->work_list); |
Krzysztof Kozlowski | ae43b32 | 2014-11-14 09:48:57 +0100 | [diff] [blame] | 2054 | if (power_down) { |
| 2055 | spin_lock(&pch->thread->dmac->lock); |
| 2056 | _start(pch->thread); |
| 2057 | spin_unlock(&pch->thread->dmac->lock); |
| 2058 | power_down = false; |
| 2059 | } |
Lars-Peter Clausen | 39ff861 | 2013-08-27 20:34:05 +0200 | [diff] [blame] | 2060 | } else { |
| 2061 | desc->status = FREE; |
| 2062 | list_move_tail(&desc->node, &pch->dmac->desc_pool); |
| 2063 | } |
| 2064 | |
Dan Williams | d38a8c6 | 2013-10-18 19:35:23 +0200 | [diff] [blame] | 2065 | dma_descriptor_unmap(&desc->txd); |
| 2066 | |
Lars-Peter Clausen | 39ff861 | 2013-08-27 20:34:05 +0200 | [diff] [blame] | 2067 | if (callback) { |
| 2068 | spin_unlock_irqrestore(&pch->lock, flags); |
| 2069 | callback(callback_param); |
| 2070 | spin_lock_irqsave(&pch->lock, flags); |
| 2071 | } |
| 2072 | } |
| 2073 | spin_unlock_irqrestore(&pch->lock, flags); |
Krzysztof Kozlowski | ae43b32 | 2014-11-14 09:48:57 +0100 | [diff] [blame] | 2074 | |
| 2075 | /* If work list empty, power down */ |
| 2076 | if (power_down) { |
| 2077 | pm_runtime_mark_last_busy(pch->dmac->ddma.dev); |
| 2078 | pm_runtime_put_autosuspend(pch->dmac->ddma.dev); |
| 2079 | } |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2080 | } |
| 2081 | |
Thomas Abraham | 3e2ec13 | 2011-10-24 11:43:02 +0200 | [diff] [blame] | 2082 | bool pl330_filter(struct dma_chan *chan, void *param) |
| 2083 | { |
Thomas Abraham | cd07251 | 2011-10-24 11:43:11 +0200 | [diff] [blame] | 2084 | u8 *peri_id; |
Thomas Abraham | 3e2ec13 | 2011-10-24 11:43:02 +0200 | [diff] [blame] | 2085 | |
| 2086 | if (chan->device->dev->driver != &pl330_driver.drv) |
| 2087 | return false; |
| 2088 | |
Thomas Abraham | cd07251 | 2011-10-24 11:43:11 +0200 | [diff] [blame] | 2089 | peri_id = chan->private; |
Dan Carpenter | 2f986ec | 2013-11-08 12:51:16 +0300 | [diff] [blame] | 2090 | return *peri_id == (unsigned long)param; |
Thomas Abraham | 3e2ec13 | 2011-10-24 11:43:02 +0200 | [diff] [blame] | 2091 | } |
| 2092 | EXPORT_SYMBOL(pl330_filter); |
| 2093 | |
Padmavathi Venna | a80258f | 2013-02-14 09:10:06 +0530 | [diff] [blame] | 2094 | static struct dma_chan *of_dma_pl330_xlate(struct of_phandle_args *dma_spec, |
| 2095 | struct of_dma *ofdma) |
| 2096 | { |
| 2097 | int count = dma_spec->args_count; |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2098 | struct pl330_dmac *pl330 = ofdma->of_dma_data; |
Lars-Peter Clausen | 70cbb16 | 2014-01-11 20:08:39 +0100 | [diff] [blame] | 2099 | unsigned int chan_id; |
Padmavathi Venna | a80258f | 2013-02-14 09:10:06 +0530 | [diff] [blame] | 2100 | |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2101 | if (!pl330) |
| 2102 | return NULL; |
| 2103 | |
Padmavathi Venna | a80258f | 2013-02-14 09:10:06 +0530 | [diff] [blame] | 2104 | if (count != 1) |
| 2105 | return NULL; |
| 2106 | |
Lars-Peter Clausen | 70cbb16 | 2014-01-11 20:08:39 +0100 | [diff] [blame] | 2107 | chan_id = dma_spec->args[0]; |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2108 | if (chan_id >= pl330->num_peripherals) |
Lars-Peter Clausen | 70cbb16 | 2014-01-11 20:08:39 +0100 | [diff] [blame] | 2109 | return NULL; |
Padmavathi Venna | a80258f | 2013-02-14 09:10:06 +0530 | [diff] [blame] | 2110 | |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2111 | return dma_get_slave_channel(&pl330->peripherals[chan_id].chan); |
Padmavathi Venna | a80258f | 2013-02-14 09:10:06 +0530 | [diff] [blame] | 2112 | } |
| 2113 | |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2114 | static int pl330_alloc_chan_resources(struct dma_chan *chan) |
| 2115 | { |
| 2116 | struct dma_pl330_chan *pch = to_pchan(chan); |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2117 | struct pl330_dmac *pl330 = pch->dmac; |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2118 | unsigned long flags; |
| 2119 | |
| 2120 | spin_lock_irqsave(&pch->lock, flags); |
| 2121 | |
Russell King - ARM Linux | d3ee98cdc | 2012-03-06 22:35:47 +0000 | [diff] [blame] | 2122 | dma_cookie_init(chan); |
Boojin Kim | 42bc9cf | 2011-09-02 09:44:33 +0900 | [diff] [blame] | 2123 | pch->cyclic = false; |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2124 | |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2125 | pch->thread = pl330_request_channel(pl330); |
Lars-Peter Clausen | 65ad606 | 2014-07-06 20:32:26 +0200 | [diff] [blame] | 2126 | if (!pch->thread) { |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2127 | spin_unlock_irqrestore(&pch->lock, flags); |
Inderpal Singh | 0274788 | 2012-09-17 09:57:45 +0530 | [diff] [blame] | 2128 | return -ENOMEM; |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2129 | } |
| 2130 | |
| 2131 | tasklet_init(&pch->task, pl330_tasklet, (unsigned long) pch); |
| 2132 | |
| 2133 | spin_unlock_irqrestore(&pch->lock, flags); |
| 2134 | |
| 2135 | return 1; |
| 2136 | } |
| 2137 | |
Maxime Ripard | 740aa95 | 2014-11-17 14:42:29 +0100 | [diff] [blame] | 2138 | static int pl330_config(struct dma_chan *chan, |
| 2139 | struct dma_slave_config *slave_config) |
| 2140 | { |
| 2141 | struct dma_pl330_chan *pch = to_pchan(chan); |
| 2142 | |
| 2143 | if (slave_config->direction == DMA_MEM_TO_DEV) { |
| 2144 | if (slave_config->dst_addr) |
| 2145 | pch->fifo_addr = slave_config->dst_addr; |
| 2146 | if (slave_config->dst_addr_width) |
| 2147 | pch->burst_sz = __ffs(slave_config->dst_addr_width); |
| 2148 | if (slave_config->dst_maxburst) |
| 2149 | pch->burst_len = slave_config->dst_maxburst; |
| 2150 | } else if (slave_config->direction == DMA_DEV_TO_MEM) { |
| 2151 | if (slave_config->src_addr) |
| 2152 | pch->fifo_addr = slave_config->src_addr; |
| 2153 | if (slave_config->src_addr_width) |
| 2154 | pch->burst_sz = __ffs(slave_config->src_addr_width); |
| 2155 | if (slave_config->src_maxburst) |
| 2156 | pch->burst_len = slave_config->src_maxburst; |
| 2157 | } |
| 2158 | |
| 2159 | return 0; |
| 2160 | } |
| 2161 | |
| 2162 | static int pl330_terminate_all(struct dma_chan *chan) |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2163 | { |
| 2164 | struct dma_pl330_chan *pch = to_pchan(chan); |
Lars-Peter Clausen | 39ff861 | 2013-08-27 20:34:05 +0200 | [diff] [blame] | 2165 | struct dma_pl330_desc *desc; |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2166 | unsigned long flags; |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2167 | struct pl330_dmac *pl330 = pch->dmac; |
Boojin Kim | ae43b88 | 2011-09-02 09:44:32 +0900 | [diff] [blame] | 2168 | LIST_HEAD(list); |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2169 | |
Krzysztof Kozlowski | 81cc6ed | 2015-05-21 09:34:09 +0900 | [diff] [blame] | 2170 | pm_runtime_get_sync(pl330->ddma.dev); |
Maxime Ripard | 740aa95 | 2014-11-17 14:42:29 +0100 | [diff] [blame] | 2171 | spin_lock_irqsave(&pch->lock, flags); |
| 2172 | spin_lock(&pl330->lock); |
| 2173 | _stop(pch->thread); |
| 2174 | spin_unlock(&pl330->lock); |
Boojin Kim | 1d0c1d6 | 2011-09-02 09:44:31 +0900 | [diff] [blame] | 2175 | |
Maxime Ripard | 740aa95 | 2014-11-17 14:42:29 +0100 | [diff] [blame] | 2176 | pch->thread->req[0].desc = NULL; |
| 2177 | pch->thread->req[1].desc = NULL; |
| 2178 | pch->thread->req_running = -1; |
Lars-Peter Clausen | c26939e | 2014-07-06 20:32:32 +0200 | [diff] [blame] | 2179 | |
Maxime Ripard | 740aa95 | 2014-11-17 14:42:29 +0100 | [diff] [blame] | 2180 | /* Mark all desc done */ |
| 2181 | list_for_each_entry(desc, &pch->submitted_list, node) { |
| 2182 | desc->status = FREE; |
| 2183 | dma_cookie_complete(&desc->txd); |
Boojin Kim | 1d0c1d6 | 2011-09-02 09:44:31 +0900 | [diff] [blame] | 2184 | } |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2185 | |
Maxime Ripard | 740aa95 | 2014-11-17 14:42:29 +0100 | [diff] [blame] | 2186 | list_for_each_entry(desc, &pch->work_list , node) { |
| 2187 | desc->status = FREE; |
| 2188 | dma_cookie_complete(&desc->txd); |
| 2189 | } |
| 2190 | |
| 2191 | list_splice_tail_init(&pch->submitted_list, &pl330->desc_pool); |
| 2192 | list_splice_tail_init(&pch->work_list, &pl330->desc_pool); |
| 2193 | list_splice_tail_init(&pch->completed_list, &pl330->desc_pool); |
| 2194 | spin_unlock_irqrestore(&pch->lock, flags); |
Krzysztof Kozlowski | 81cc6ed | 2015-05-21 09:34:09 +0900 | [diff] [blame] | 2195 | pm_runtime_mark_last_busy(pl330->ddma.dev); |
| 2196 | pm_runtime_put_autosuspend(pl330->ddma.dev); |
Maxime Ripard | 740aa95 | 2014-11-17 14:42:29 +0100 | [diff] [blame] | 2197 | |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2198 | return 0; |
| 2199 | } |
| 2200 | |
Robert Baldyga | 88987d2 | 2015-02-11 13:23:18 +0100 | [diff] [blame] | 2201 | /* |
| 2202 | * We don't support DMA_RESUME command because of hardware |
| 2203 | * limitations, so after pausing the channel we cannot restore |
| 2204 | * it to active state. We have to terminate channel and setup |
| 2205 | * DMA transfer again. This pause feature was implemented to |
| 2206 | * allow safely read residue before channel termination. |
| 2207 | */ |
Ben Dooks | 5503aed | 2015-03-16 11:52:44 +0000 | [diff] [blame] | 2208 | static int pl330_pause(struct dma_chan *chan) |
Robert Baldyga | 88987d2 | 2015-02-11 13:23:18 +0100 | [diff] [blame] | 2209 | { |
| 2210 | struct dma_pl330_chan *pch = to_pchan(chan); |
| 2211 | struct pl330_dmac *pl330 = pch->dmac; |
| 2212 | unsigned long flags; |
| 2213 | |
| 2214 | pm_runtime_get_sync(pl330->ddma.dev); |
| 2215 | spin_lock_irqsave(&pch->lock, flags); |
| 2216 | |
| 2217 | spin_lock(&pl330->lock); |
| 2218 | _stop(pch->thread); |
| 2219 | spin_unlock(&pl330->lock); |
| 2220 | |
| 2221 | spin_unlock_irqrestore(&pch->lock, flags); |
| 2222 | pm_runtime_mark_last_busy(pl330->ddma.dev); |
| 2223 | pm_runtime_put_autosuspend(pl330->ddma.dev); |
| 2224 | |
| 2225 | return 0; |
| 2226 | } |
| 2227 | |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2228 | static void pl330_free_chan_resources(struct dma_chan *chan) |
| 2229 | { |
| 2230 | struct dma_pl330_chan *pch = to_pchan(chan); |
| 2231 | unsigned long flags; |
| 2232 | |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2233 | tasklet_kill(&pch->task); |
| 2234 | |
Krzysztof Kozlowski | ae43b32 | 2014-11-14 09:48:57 +0100 | [diff] [blame] | 2235 | pm_runtime_get_sync(pch->dmac->ddma.dev); |
Bartlomiej Zolnierkiewicz | da331ba | 2013-07-03 15:00:43 -0700 | [diff] [blame] | 2236 | spin_lock_irqsave(&pch->lock, flags); |
| 2237 | |
Lars-Peter Clausen | 65ad606 | 2014-07-06 20:32:26 +0200 | [diff] [blame] | 2238 | pl330_release_channel(pch->thread); |
| 2239 | pch->thread = NULL; |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2240 | |
Boojin Kim | 42bc9cf | 2011-09-02 09:44:33 +0900 | [diff] [blame] | 2241 | if (pch->cyclic) |
| 2242 | list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool); |
| 2243 | |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2244 | spin_unlock_irqrestore(&pch->lock, flags); |
Krzysztof Kozlowski | ae43b32 | 2014-11-14 09:48:57 +0100 | [diff] [blame] | 2245 | pm_runtime_mark_last_busy(pch->dmac->ddma.dev); |
| 2246 | pm_runtime_put_autosuspend(pch->dmac->ddma.dev); |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2247 | } |
| 2248 | |
Ben Dooks | 5503aed | 2015-03-16 11:52:44 +0000 | [diff] [blame] | 2249 | static int pl330_get_current_xferred_count(struct dma_pl330_chan *pch, |
| 2250 | struct dma_pl330_desc *desc) |
Robert Baldyga | aee4d1f | 2015-02-11 13:23:17 +0100 | [diff] [blame] | 2251 | { |
| 2252 | struct pl330_thread *thrd = pch->thread; |
| 2253 | struct pl330_dmac *pl330 = pch->dmac; |
| 2254 | void __iomem *regs = thrd->dmac->base; |
| 2255 | u32 val, addr; |
| 2256 | |
| 2257 | pm_runtime_get_sync(pl330->ddma.dev); |
| 2258 | val = addr = 0; |
| 2259 | if (desc->rqcfg.src_inc) { |
| 2260 | val = readl(regs + SA(thrd->id)); |
| 2261 | addr = desc->px.src_addr; |
| 2262 | } else { |
| 2263 | val = readl(regs + DA(thrd->id)); |
| 2264 | addr = desc->px.dst_addr; |
| 2265 | } |
| 2266 | pm_runtime_mark_last_busy(pch->dmac->ddma.dev); |
| 2267 | pm_runtime_put_autosuspend(pl330->ddma.dev); |
| 2268 | return val - addr; |
| 2269 | } |
| 2270 | |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2271 | static enum dma_status |
| 2272 | pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie, |
| 2273 | struct dma_tx_state *txstate) |
| 2274 | { |
Robert Baldyga | aee4d1f | 2015-02-11 13:23:17 +0100 | [diff] [blame] | 2275 | enum dma_status ret; |
| 2276 | unsigned long flags; |
| 2277 | struct dma_pl330_desc *desc, *running = NULL; |
| 2278 | struct dma_pl330_chan *pch = to_pchan(chan); |
| 2279 | unsigned int transferred, residual = 0; |
| 2280 | |
| 2281 | ret = dma_cookie_status(chan, cookie, txstate); |
| 2282 | |
| 2283 | if (!txstate) |
| 2284 | return ret; |
| 2285 | |
| 2286 | if (ret == DMA_COMPLETE) |
| 2287 | goto out; |
| 2288 | |
| 2289 | spin_lock_irqsave(&pch->lock, flags); |
| 2290 | |
| 2291 | if (pch->thread->req_running != -1) |
| 2292 | running = pch->thread->req[pch->thread->req_running].desc; |
| 2293 | |
| 2294 | /* Check in pending list */ |
| 2295 | list_for_each_entry(desc, &pch->work_list, node) { |
| 2296 | if (desc->status == DONE) |
| 2297 | transferred = desc->bytes_requested; |
| 2298 | else if (running && desc == running) |
| 2299 | transferred = |
| 2300 | pl330_get_current_xferred_count(pch, desc); |
| 2301 | else |
| 2302 | transferred = 0; |
| 2303 | residual += desc->bytes_requested - transferred; |
| 2304 | if (desc->txd.cookie == cookie) { |
Ben Dooks | 75967b78 | 2015-03-16 11:52:45 +0000 | [diff] [blame] | 2305 | switch (desc->status) { |
| 2306 | case DONE: |
| 2307 | ret = DMA_COMPLETE; |
| 2308 | break; |
| 2309 | case PREP: |
| 2310 | case BUSY: |
| 2311 | ret = DMA_IN_PROGRESS; |
| 2312 | break; |
| 2313 | default: |
| 2314 | WARN_ON(1); |
| 2315 | } |
Robert Baldyga | aee4d1f | 2015-02-11 13:23:17 +0100 | [diff] [blame] | 2316 | break; |
| 2317 | } |
| 2318 | if (desc->last) |
| 2319 | residual = 0; |
| 2320 | } |
| 2321 | spin_unlock_irqrestore(&pch->lock, flags); |
| 2322 | |
| 2323 | out: |
| 2324 | dma_set_residue(txstate, residual); |
| 2325 | |
| 2326 | return ret; |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2327 | } |
| 2328 | |
| 2329 | static void pl330_issue_pending(struct dma_chan *chan) |
| 2330 | { |
Lars-Peter Clausen | 04abf5d | 2014-01-11 20:08:38 +0100 | [diff] [blame] | 2331 | struct dma_pl330_chan *pch = to_pchan(chan); |
| 2332 | unsigned long flags; |
| 2333 | |
| 2334 | spin_lock_irqsave(&pch->lock, flags); |
Krzysztof Kozlowski | ae43b32 | 2014-11-14 09:48:57 +0100 | [diff] [blame] | 2335 | if (list_empty(&pch->work_list)) { |
| 2336 | /* |
| 2337 | * Warn on nothing pending. Empty submitted_list may |
| 2338 | * break our pm_runtime usage counter as it is |
| 2339 | * updated on work_list emptiness status. |
| 2340 | */ |
| 2341 | WARN_ON(list_empty(&pch->submitted_list)); |
| 2342 | pm_runtime_get_sync(pch->dmac->ddma.dev); |
| 2343 | } |
Lars-Peter Clausen | 04abf5d | 2014-01-11 20:08:38 +0100 | [diff] [blame] | 2344 | list_splice_tail_init(&pch->submitted_list, &pch->work_list); |
| 2345 | spin_unlock_irqrestore(&pch->lock, flags); |
| 2346 | |
| 2347 | pl330_tasklet((unsigned long)pch); |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2348 | } |
| 2349 | |
| 2350 | /* |
| 2351 | * We returned the last one of the circular list of descriptor(s) |
| 2352 | * from prep_xxx, so the argument to submit corresponds to the last |
| 2353 | * descriptor of the list. |
| 2354 | */ |
| 2355 | static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx) |
| 2356 | { |
| 2357 | struct dma_pl330_desc *desc, *last = to_desc(tx); |
| 2358 | struct dma_pl330_chan *pch = to_pchan(tx->chan); |
| 2359 | dma_cookie_t cookie; |
| 2360 | unsigned long flags; |
| 2361 | |
| 2362 | spin_lock_irqsave(&pch->lock, flags); |
| 2363 | |
| 2364 | /* Assign cookies to all nodes */ |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2365 | while (!list_empty(&last->node)) { |
| 2366 | desc = list_entry(last->node.next, struct dma_pl330_desc, node); |
Lars-Peter Clausen | fc51446 | 2013-07-23 10:24:50 +0200 | [diff] [blame] | 2367 | if (pch->cyclic) { |
| 2368 | desc->txd.callback = last->txd.callback; |
| 2369 | desc->txd.callback_param = last->txd.callback_param; |
| 2370 | } |
Krzysztof Kozlowski | 5dd90e5 | 2015-06-15 23:00:09 +0900 | [diff] [blame] | 2371 | desc->last = false; |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2372 | |
Russell King - ARM Linux | 884485e | 2012-03-06 22:34:46 +0000 | [diff] [blame] | 2373 | dma_cookie_assign(&desc->txd); |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2374 | |
Lars-Peter Clausen | 04abf5d | 2014-01-11 20:08:38 +0100 | [diff] [blame] | 2375 | list_move_tail(&desc->node, &pch->submitted_list); |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2376 | } |
| 2377 | |
Robert Baldyga | aee4d1f | 2015-02-11 13:23:17 +0100 | [diff] [blame] | 2378 | last->last = true; |
Russell King - ARM Linux | 884485e | 2012-03-06 22:34:46 +0000 | [diff] [blame] | 2379 | cookie = dma_cookie_assign(&last->txd); |
Lars-Peter Clausen | 04abf5d | 2014-01-11 20:08:38 +0100 | [diff] [blame] | 2380 | list_add_tail(&last->node, &pch->submitted_list); |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2381 | spin_unlock_irqrestore(&pch->lock, flags); |
| 2382 | |
| 2383 | return cookie; |
| 2384 | } |
| 2385 | |
| 2386 | static inline void _init_desc(struct dma_pl330_desc *desc) |
| 2387 | { |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2388 | desc->rqcfg.swap = SWAP_NO; |
Lars-Peter Clausen | f0564c7 | 2014-07-06 20:32:19 +0200 | [diff] [blame] | 2389 | desc->rqcfg.scctl = CCTRL0; |
| 2390 | desc->rqcfg.dcctl = CCTRL0; |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2391 | desc->txd.tx_submit = pl330_tx_submit; |
| 2392 | |
| 2393 | INIT_LIST_HEAD(&desc->node); |
| 2394 | } |
| 2395 | |
| 2396 | /* Returns the number of descriptors added to the DMAC pool */ |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2397 | static int add_desc(struct pl330_dmac *pl330, gfp_t flg, int count) |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2398 | { |
| 2399 | struct dma_pl330_desc *desc; |
| 2400 | unsigned long flags; |
| 2401 | int i; |
| 2402 | |
Will Deacon | 0baf8f6 | 2013-12-02 18:01:30 +0000 | [diff] [blame] | 2403 | desc = kcalloc(count, sizeof(*desc), flg); |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2404 | if (!desc) |
| 2405 | return 0; |
| 2406 | |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2407 | spin_lock_irqsave(&pl330->pool_lock, flags); |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2408 | |
| 2409 | for (i = 0; i < count; i++) { |
| 2410 | _init_desc(&desc[i]); |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2411 | list_add_tail(&desc[i].node, &pl330->desc_pool); |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2412 | } |
| 2413 | |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2414 | spin_unlock_irqrestore(&pl330->pool_lock, flags); |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2415 | |
| 2416 | return count; |
| 2417 | } |
| 2418 | |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2419 | static struct dma_pl330_desc *pluck_desc(struct pl330_dmac *pl330) |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2420 | { |
| 2421 | struct dma_pl330_desc *desc = NULL; |
| 2422 | unsigned long flags; |
| 2423 | |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2424 | spin_lock_irqsave(&pl330->pool_lock, flags); |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2425 | |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2426 | if (!list_empty(&pl330->desc_pool)) { |
| 2427 | desc = list_entry(pl330->desc_pool.next, |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2428 | struct dma_pl330_desc, node); |
| 2429 | |
| 2430 | list_del_init(&desc->node); |
| 2431 | |
| 2432 | desc->status = PREP; |
| 2433 | desc->txd.callback = NULL; |
| 2434 | } |
| 2435 | |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2436 | spin_unlock_irqrestore(&pl330->pool_lock, flags); |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2437 | |
| 2438 | return desc; |
| 2439 | } |
| 2440 | |
| 2441 | static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch) |
| 2442 | { |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2443 | struct pl330_dmac *pl330 = pch->dmac; |
Thomas Abraham | cd07251 | 2011-10-24 11:43:11 +0200 | [diff] [blame] | 2444 | u8 *peri_id = pch->chan.private; |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2445 | struct dma_pl330_desc *desc; |
| 2446 | |
| 2447 | /* Pluck one desc from the pool of DMAC */ |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2448 | desc = pluck_desc(pl330); |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2449 | |
| 2450 | /* If the DMAC pool is empty, alloc new */ |
| 2451 | if (!desc) { |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2452 | if (!add_desc(pl330, GFP_ATOMIC, 1)) |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2453 | return NULL; |
| 2454 | |
| 2455 | /* Try again */ |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2456 | desc = pluck_desc(pl330); |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2457 | if (!desc) { |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2458 | dev_err(pch->dmac->ddma.dev, |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2459 | "%s:%d ALERT!\n", __func__, __LINE__); |
| 2460 | return NULL; |
| 2461 | } |
| 2462 | } |
| 2463 | |
| 2464 | /* Initialize the descriptor */ |
| 2465 | desc->pchan = pch; |
| 2466 | desc->txd.cookie = 0; |
| 2467 | async_tx_ack(&desc->txd); |
| 2468 | |
Lars-Peter Clausen | 9dc5a31 | 2014-07-06 20:32:30 +0200 | [diff] [blame] | 2469 | desc->peri = peri_id ? pch->chan.chan_id : 0; |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2470 | desc->rqcfg.pcfg = &pch->dmac->pcfg; |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2471 | |
| 2472 | dma_async_tx_descriptor_init(&desc->txd, &pch->chan); |
| 2473 | |
| 2474 | return desc; |
| 2475 | } |
| 2476 | |
| 2477 | static inline void fill_px(struct pl330_xfer *px, |
| 2478 | dma_addr_t dst, dma_addr_t src, size_t len) |
| 2479 | { |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2480 | px->bytes = len; |
| 2481 | px->dst_addr = dst; |
| 2482 | px->src_addr = src; |
| 2483 | } |
| 2484 | |
| 2485 | static struct dma_pl330_desc * |
| 2486 | __pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst, |
| 2487 | dma_addr_t src, size_t len) |
| 2488 | { |
| 2489 | struct dma_pl330_desc *desc = pl330_get_desc(pch); |
| 2490 | |
| 2491 | if (!desc) { |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2492 | dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n", |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2493 | __func__, __LINE__); |
| 2494 | return NULL; |
| 2495 | } |
| 2496 | |
| 2497 | /* |
| 2498 | * Ideally we should lookout for reqs bigger than |
| 2499 | * those that can be programmed with 256 bytes of |
| 2500 | * MC buffer, but considering a req size is seldom |
| 2501 | * going to be word-unaligned and more than 200MB, |
| 2502 | * we take it easy. |
| 2503 | * Also, should the limit is reached we'd rather |
| 2504 | * have the platform increase MC buffer size than |
| 2505 | * complicating this API driver. |
| 2506 | */ |
| 2507 | fill_px(&desc->px, dst, src, len); |
| 2508 | |
| 2509 | return desc; |
| 2510 | } |
| 2511 | |
| 2512 | /* Call after fixing burst size */ |
| 2513 | static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len) |
| 2514 | { |
| 2515 | struct dma_pl330_chan *pch = desc->pchan; |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2516 | struct pl330_dmac *pl330 = pch->dmac; |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2517 | int burst_len; |
| 2518 | |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2519 | burst_len = pl330->pcfg.data_bus_width / 8; |
Jon Medhurst | c27f955 | 2014-11-07 18:05:18 +0000 | [diff] [blame] | 2520 | burst_len *= pl330->pcfg.data_buf_dep / pl330->pcfg.num_chan; |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2521 | burst_len >>= desc->rqcfg.brst_size; |
| 2522 | |
| 2523 | /* src/dst_burst_len can't be more than 16 */ |
| 2524 | if (burst_len > 16) |
| 2525 | burst_len = 16; |
| 2526 | |
| 2527 | while (burst_len > 1) { |
| 2528 | if (!(len % (burst_len << desc->rqcfg.brst_size))) |
| 2529 | break; |
| 2530 | burst_len--; |
| 2531 | } |
| 2532 | |
| 2533 | return burst_len; |
| 2534 | } |
| 2535 | |
Boojin Kim | 42bc9cf | 2011-09-02 09:44:33 +0900 | [diff] [blame] | 2536 | static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic( |
| 2537 | struct dma_chan *chan, dma_addr_t dma_addr, size_t len, |
Alexandre Bounine | 185ecb5 | 2012-03-08 15:35:13 -0500 | [diff] [blame] | 2538 | size_t period_len, enum dma_transfer_direction direction, |
Laurent Pinchart | 31c1e5a | 2014-08-01 12:20:10 +0200 | [diff] [blame] | 2539 | unsigned long flags) |
Boojin Kim | 42bc9cf | 2011-09-02 09:44:33 +0900 | [diff] [blame] | 2540 | { |
Lars-Peter Clausen | fc51446 | 2013-07-23 10:24:50 +0200 | [diff] [blame] | 2541 | struct dma_pl330_desc *desc = NULL, *first = NULL; |
Boojin Kim | 42bc9cf | 2011-09-02 09:44:33 +0900 | [diff] [blame] | 2542 | struct dma_pl330_chan *pch = to_pchan(chan); |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2543 | struct pl330_dmac *pl330 = pch->dmac; |
Lars-Peter Clausen | fc51446 | 2013-07-23 10:24:50 +0200 | [diff] [blame] | 2544 | unsigned int i; |
Boojin Kim | 42bc9cf | 2011-09-02 09:44:33 +0900 | [diff] [blame] | 2545 | dma_addr_t dst; |
| 2546 | dma_addr_t src; |
| 2547 | |
Lars-Peter Clausen | fc51446 | 2013-07-23 10:24:50 +0200 | [diff] [blame] | 2548 | if (len % period_len != 0) |
Boojin Kim | 42bc9cf | 2011-09-02 09:44:33 +0900 | [diff] [blame] | 2549 | return NULL; |
Boojin Kim | 42bc9cf | 2011-09-02 09:44:33 +0900 | [diff] [blame] | 2550 | |
Lars-Peter Clausen | fc51446 | 2013-07-23 10:24:50 +0200 | [diff] [blame] | 2551 | if (!is_slave_direction(direction)) { |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2552 | dev_err(pch->dmac->ddma.dev, "%s:%d Invalid dma direction\n", |
Boojin Kim | 42bc9cf | 2011-09-02 09:44:33 +0900 | [diff] [blame] | 2553 | __func__, __LINE__); |
| 2554 | return NULL; |
| 2555 | } |
| 2556 | |
Lars-Peter Clausen | fc51446 | 2013-07-23 10:24:50 +0200 | [diff] [blame] | 2557 | for (i = 0; i < len / period_len; i++) { |
| 2558 | desc = pl330_get_desc(pch); |
| 2559 | if (!desc) { |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2560 | dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n", |
Lars-Peter Clausen | fc51446 | 2013-07-23 10:24:50 +0200 | [diff] [blame] | 2561 | __func__, __LINE__); |
| 2562 | |
| 2563 | if (!first) |
| 2564 | return NULL; |
| 2565 | |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2566 | spin_lock_irqsave(&pl330->pool_lock, flags); |
Lars-Peter Clausen | fc51446 | 2013-07-23 10:24:50 +0200 | [diff] [blame] | 2567 | |
| 2568 | while (!list_empty(&first->node)) { |
| 2569 | desc = list_entry(first->node.next, |
| 2570 | struct dma_pl330_desc, node); |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2571 | list_move_tail(&desc->node, &pl330->desc_pool); |
Lars-Peter Clausen | fc51446 | 2013-07-23 10:24:50 +0200 | [diff] [blame] | 2572 | } |
| 2573 | |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2574 | list_move_tail(&first->node, &pl330->desc_pool); |
Lars-Peter Clausen | fc51446 | 2013-07-23 10:24:50 +0200 | [diff] [blame] | 2575 | |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2576 | spin_unlock_irqrestore(&pl330->pool_lock, flags); |
Lars-Peter Clausen | fc51446 | 2013-07-23 10:24:50 +0200 | [diff] [blame] | 2577 | |
| 2578 | return NULL; |
| 2579 | } |
| 2580 | |
| 2581 | switch (direction) { |
| 2582 | case DMA_MEM_TO_DEV: |
| 2583 | desc->rqcfg.src_inc = 1; |
| 2584 | desc->rqcfg.dst_inc = 0; |
Lars-Peter Clausen | fc51446 | 2013-07-23 10:24:50 +0200 | [diff] [blame] | 2585 | src = dma_addr; |
| 2586 | dst = pch->fifo_addr; |
| 2587 | break; |
| 2588 | case DMA_DEV_TO_MEM: |
| 2589 | desc->rqcfg.src_inc = 0; |
| 2590 | desc->rqcfg.dst_inc = 1; |
Lars-Peter Clausen | fc51446 | 2013-07-23 10:24:50 +0200 | [diff] [blame] | 2591 | src = pch->fifo_addr; |
| 2592 | dst = dma_addr; |
| 2593 | break; |
| 2594 | default: |
| 2595 | break; |
| 2596 | } |
| 2597 | |
Lars-Peter Clausen | 9dc5a31 | 2014-07-06 20:32:30 +0200 | [diff] [blame] | 2598 | desc->rqtype = direction; |
Lars-Peter Clausen | fc51446 | 2013-07-23 10:24:50 +0200 | [diff] [blame] | 2599 | desc->rqcfg.brst_size = pch->burst_sz; |
Caesar Wang | 0a18f9b | 2016-02-25 09:00:53 +0800 | [diff] [blame] | 2600 | desc->rqcfg.brst_len = 1; |
Robert Baldyga | aee4d1f | 2015-02-11 13:23:17 +0100 | [diff] [blame] | 2601 | desc->bytes_requested = period_len; |
Lars-Peter Clausen | fc51446 | 2013-07-23 10:24:50 +0200 | [diff] [blame] | 2602 | fill_px(&desc->px, dst, src, period_len); |
| 2603 | |
| 2604 | if (!first) |
| 2605 | first = desc; |
| 2606 | else |
| 2607 | list_add_tail(&desc->node, &first->node); |
| 2608 | |
| 2609 | dma_addr += period_len; |
| 2610 | } |
| 2611 | |
| 2612 | if (!desc) |
| 2613 | return NULL; |
Boojin Kim | 42bc9cf | 2011-09-02 09:44:33 +0900 | [diff] [blame] | 2614 | |
| 2615 | pch->cyclic = true; |
Lars-Peter Clausen | fc51446 | 2013-07-23 10:24:50 +0200 | [diff] [blame] | 2616 | desc->txd.flags = flags; |
Boojin Kim | 42bc9cf | 2011-09-02 09:44:33 +0900 | [diff] [blame] | 2617 | |
| 2618 | return &desc->txd; |
| 2619 | } |
| 2620 | |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2621 | static struct dma_async_tx_descriptor * |
| 2622 | pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst, |
| 2623 | dma_addr_t src, size_t len, unsigned long flags) |
| 2624 | { |
| 2625 | struct dma_pl330_desc *desc; |
| 2626 | struct dma_pl330_chan *pch = to_pchan(chan); |
Maninder Singh | f563685 | 2015-05-26 00:40:05 +0530 | [diff] [blame] | 2627 | struct pl330_dmac *pl330; |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2628 | int burst; |
| 2629 | |
Rob Herring | 4e0e610 | 2011-07-25 16:05:04 -0500 | [diff] [blame] | 2630 | if (unlikely(!pch || !len)) |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2631 | return NULL; |
| 2632 | |
Maninder Singh | f563685 | 2015-05-26 00:40:05 +0530 | [diff] [blame] | 2633 | pl330 = pch->dmac; |
| 2634 | |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2635 | desc = __pl330_prep_dma_memcpy(pch, dst, src, len); |
| 2636 | if (!desc) |
| 2637 | return NULL; |
| 2638 | |
| 2639 | desc->rqcfg.src_inc = 1; |
| 2640 | desc->rqcfg.dst_inc = 1; |
Lars-Peter Clausen | 9dc5a31 | 2014-07-06 20:32:30 +0200 | [diff] [blame] | 2641 | desc->rqtype = DMA_MEM_TO_MEM; |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2642 | |
| 2643 | /* Select max possible burst size */ |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2644 | burst = pl330->pcfg.data_bus_width / 8; |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2645 | |
Jon Medhurst | 137bd11 | 2014-11-07 18:05:17 +0000 | [diff] [blame] | 2646 | /* |
| 2647 | * Make sure we use a burst size that aligns with all the memcpy |
| 2648 | * parameters because our DMA programming algorithm doesn't cope with |
| 2649 | * transfers which straddle an entry in the DMA device's MFIFO. |
| 2650 | */ |
| 2651 | while ((src | dst | len) & (burst - 1)) |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2652 | burst /= 2; |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2653 | |
| 2654 | desc->rqcfg.brst_size = 0; |
| 2655 | while (burst != (1 << desc->rqcfg.brst_size)) |
| 2656 | desc->rqcfg.brst_size++; |
| 2657 | |
Jon Medhurst | 137bd11 | 2014-11-07 18:05:17 +0000 | [diff] [blame] | 2658 | /* |
| 2659 | * If burst size is smaller than bus width then make sure we only |
| 2660 | * transfer one at a time to avoid a burst stradling an MFIFO entry. |
| 2661 | */ |
| 2662 | if (desc->rqcfg.brst_size * 8 < pl330->pcfg.data_bus_width) |
| 2663 | desc->rqcfg.brst_len = 1; |
| 2664 | |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2665 | desc->rqcfg.brst_len = get_burst_len(desc, len); |
Krzysztof Kozlowski | ae12829 | 2015-06-15 17:25:16 +0900 | [diff] [blame] | 2666 | desc->bytes_requested = len; |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2667 | |
| 2668 | desc->txd.flags = flags; |
| 2669 | |
| 2670 | return &desc->txd; |
| 2671 | } |
| 2672 | |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2673 | static void __pl330_giveback_desc(struct pl330_dmac *pl330, |
Chanho Park | 52a9d17 | 2013-08-09 20:11:33 +0900 | [diff] [blame] | 2674 | struct dma_pl330_desc *first) |
| 2675 | { |
| 2676 | unsigned long flags; |
| 2677 | struct dma_pl330_desc *desc; |
| 2678 | |
| 2679 | if (!first) |
| 2680 | return; |
| 2681 | |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2682 | spin_lock_irqsave(&pl330->pool_lock, flags); |
Chanho Park | 52a9d17 | 2013-08-09 20:11:33 +0900 | [diff] [blame] | 2683 | |
| 2684 | while (!list_empty(&first->node)) { |
| 2685 | desc = list_entry(first->node.next, |
| 2686 | struct dma_pl330_desc, node); |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2687 | list_move_tail(&desc->node, &pl330->desc_pool); |
Chanho Park | 52a9d17 | 2013-08-09 20:11:33 +0900 | [diff] [blame] | 2688 | } |
| 2689 | |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2690 | list_move_tail(&first->node, &pl330->desc_pool); |
Chanho Park | 52a9d17 | 2013-08-09 20:11:33 +0900 | [diff] [blame] | 2691 | |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2692 | spin_unlock_irqrestore(&pl330->pool_lock, flags); |
Chanho Park | 52a9d17 | 2013-08-09 20:11:33 +0900 | [diff] [blame] | 2693 | } |
| 2694 | |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2695 | static struct dma_async_tx_descriptor * |
| 2696 | pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 2697 | unsigned int sg_len, enum dma_transfer_direction direction, |
Alexandre Bounine | 185ecb5 | 2012-03-08 15:35:13 -0500 | [diff] [blame] | 2698 | unsigned long flg, void *context) |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2699 | { |
| 2700 | struct dma_pl330_desc *first, *desc = NULL; |
| 2701 | struct dma_pl330_chan *pch = to_pchan(chan); |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2702 | struct scatterlist *sg; |
Boojin Kim | 1b9bb71 | 2011-09-02 09:44:30 +0900 | [diff] [blame] | 2703 | int i; |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2704 | dma_addr_t addr; |
| 2705 | |
Thomas Abraham | cd07251 | 2011-10-24 11:43:11 +0200 | [diff] [blame] | 2706 | if (unlikely(!pch || !sgl || !sg_len)) |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2707 | return NULL; |
| 2708 | |
Boojin Kim | 1b9bb71 | 2011-09-02 09:44:30 +0900 | [diff] [blame] | 2709 | addr = pch->fifo_addr; |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2710 | |
| 2711 | first = NULL; |
| 2712 | |
| 2713 | for_each_sg(sgl, sg, sg_len, i) { |
| 2714 | |
| 2715 | desc = pl330_get_desc(pch); |
| 2716 | if (!desc) { |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2717 | struct pl330_dmac *pl330 = pch->dmac; |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2718 | |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2719 | dev_err(pch->dmac->ddma.dev, |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2720 | "%s:%d Unable to fetch desc\n", |
| 2721 | __func__, __LINE__); |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2722 | __pl330_giveback_desc(pl330, first); |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2723 | |
| 2724 | return NULL; |
| 2725 | } |
| 2726 | |
| 2727 | if (!first) |
| 2728 | first = desc; |
| 2729 | else |
| 2730 | list_add_tail(&desc->node, &first->node); |
| 2731 | |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 2732 | if (direction == DMA_MEM_TO_DEV) { |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2733 | desc->rqcfg.src_inc = 1; |
| 2734 | desc->rqcfg.dst_inc = 0; |
| 2735 | fill_px(&desc->px, |
| 2736 | addr, sg_dma_address(sg), sg_dma_len(sg)); |
| 2737 | } else { |
| 2738 | desc->rqcfg.src_inc = 0; |
| 2739 | desc->rqcfg.dst_inc = 1; |
| 2740 | fill_px(&desc->px, |
| 2741 | sg_dma_address(sg), addr, sg_dma_len(sg)); |
| 2742 | } |
| 2743 | |
Boojin Kim | 1b9bb71 | 2011-09-02 09:44:30 +0900 | [diff] [blame] | 2744 | desc->rqcfg.brst_size = pch->burst_sz; |
Caesar Wang | 0a18f9b | 2016-02-25 09:00:53 +0800 | [diff] [blame] | 2745 | desc->rqcfg.brst_len = 1; |
Lars-Peter Clausen | 9dc5a31 | 2014-07-06 20:32:30 +0200 | [diff] [blame] | 2746 | desc->rqtype = direction; |
Robert Baldyga | aee4d1f | 2015-02-11 13:23:17 +0100 | [diff] [blame] | 2747 | desc->bytes_requested = sg_dma_len(sg); |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2748 | } |
| 2749 | |
| 2750 | /* Return the last desc in the chain */ |
| 2751 | desc->txd.flags = flg; |
| 2752 | return &desc->txd; |
| 2753 | } |
| 2754 | |
| 2755 | static irqreturn_t pl330_irq_handler(int irq, void *data) |
| 2756 | { |
| 2757 | if (pl330_update(data)) |
| 2758 | return IRQ_HANDLED; |
| 2759 | else |
| 2760 | return IRQ_NONE; |
| 2761 | } |
| 2762 | |
Lars-Peter Clausen | ca38ff1 | 2013-07-15 17:53:08 +0200 | [diff] [blame] | 2763 | #define PL330_DMA_BUSWIDTHS \ |
| 2764 | BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \ |
| 2765 | BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ |
| 2766 | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ |
| 2767 | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \ |
| 2768 | BIT(DMA_SLAVE_BUSWIDTH_8_BYTES) |
| 2769 | |
Krzysztof Kozlowski | b816ccc | 2014-11-18 12:17:56 +0100 | [diff] [blame] | 2770 | /* |
| 2771 | * Runtime PM callbacks are provided by amba/bus.c driver. |
| 2772 | * |
| 2773 | * It is assumed here that IRQ safe runtime PM is chosen in probe and amba |
| 2774 | * bus driver will only disable/enable the clock in runtime PM callbacks. |
| 2775 | */ |
| 2776 | static int __maybe_unused pl330_suspend(struct device *dev) |
| 2777 | { |
| 2778 | struct amba_device *pcdev = to_amba_device(dev); |
| 2779 | |
| 2780 | pm_runtime_disable(dev); |
| 2781 | |
| 2782 | if (!pm_runtime_status_suspended(dev)) { |
| 2783 | /* amba did not disable the clock */ |
| 2784 | amba_pclk_disable(pcdev); |
| 2785 | } |
| 2786 | amba_pclk_unprepare(pcdev); |
| 2787 | |
| 2788 | return 0; |
| 2789 | } |
| 2790 | |
| 2791 | static int __maybe_unused pl330_resume(struct device *dev) |
| 2792 | { |
| 2793 | struct amba_device *pcdev = to_amba_device(dev); |
| 2794 | int ret; |
| 2795 | |
| 2796 | ret = amba_pclk_prepare(pcdev); |
| 2797 | if (ret) |
| 2798 | return ret; |
| 2799 | |
| 2800 | if (!pm_runtime_status_suspended(dev)) |
| 2801 | ret = amba_pclk_enable(pcdev); |
| 2802 | |
| 2803 | pm_runtime_enable(dev); |
| 2804 | |
| 2805 | return ret; |
| 2806 | } |
| 2807 | |
| 2808 | static SIMPLE_DEV_PM_OPS(pl330_pm, pl330_suspend, pl330_resume); |
| 2809 | |
Bill Pemberton | 463a1f8 | 2012-11-19 13:22:55 -0500 | [diff] [blame] | 2810 | static int |
Russell King | aa25afa | 2011-02-19 15:55:00 +0000 | [diff] [blame] | 2811 | pl330_probe(struct amba_device *adev, const struct amba_id *id) |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2812 | { |
| 2813 | struct dma_pl330_platdata *pdat; |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2814 | struct pl330_config *pcfg; |
| 2815 | struct pl330_dmac *pl330; |
Padmavathi Venna | 0b94c57 | 2013-03-05 14:55:31 +0530 | [diff] [blame] | 2816 | struct dma_pl330_chan *pch, *_p; |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2817 | struct dma_device *pd; |
| 2818 | struct resource *res; |
| 2819 | int i, ret, irq; |
Rob Herring | 4e0e610 | 2011-07-25 16:05:04 -0500 | [diff] [blame] | 2820 | int num_chan; |
Addy Ke | 271e1b86 | 2016-01-22 19:06:46 +0800 | [diff] [blame] | 2821 | struct device_node *np = adev->dev.of_node; |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2822 | |
Jingoo Han | d4adcc0 | 2013-07-30 17:09:11 +0900 | [diff] [blame] | 2823 | pdat = dev_get_platdata(&adev->dev); |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2824 | |
Russell King | 6411301 | 2013-06-27 10:29:32 +0100 | [diff] [blame] | 2825 | ret = dma_set_mask_and_coherent(&adev->dev, DMA_BIT_MASK(32)); |
| 2826 | if (ret) |
| 2827 | return ret; |
| 2828 | |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2829 | /* Allocate a new DMAC and its Channels */ |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2830 | pl330 = devm_kzalloc(&adev->dev, sizeof(*pl330), GFP_KERNEL); |
Peter Griffin | aef94fe | 2016-06-07 18:38:41 +0100 | [diff] [blame] | 2831 | if (!pl330) |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2832 | return -ENOMEM; |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2833 | |
Andrew Jackson | cee4239 | 2014-11-06 11:39:47 +0000 | [diff] [blame] | 2834 | pd = &pl330->ddma; |
| 2835 | pd->dev = &adev->dev; |
| 2836 | |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2837 | pl330->mcbufsz = pdat ? pdat->mcbuf_sz : 0; |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2838 | |
Addy Ke | 271e1b86 | 2016-01-22 19:06:46 +0800 | [diff] [blame] | 2839 | /* get quirk */ |
| 2840 | for (i = 0; i < ARRAY_SIZE(of_quirks); i++) |
| 2841 | if (of_property_read_bool(np, of_quirks[i].quirk)) |
| 2842 | pl330->quirks |= of_quirks[i].id; |
| 2843 | |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2844 | res = &adev->res; |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2845 | pl330->base = devm_ioremap_resource(&adev->dev, res); |
| 2846 | if (IS_ERR(pl330->base)) |
| 2847 | return PTR_ERR(pl330->base); |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2848 | |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2849 | amba_set_drvdata(adev, pl330); |
Boojin Kim | a2f5203 | 2011-09-02 09:44:29 +0900 | [diff] [blame] | 2850 | |
Dan Carpenter | 02808b4 | 2013-11-08 12:50:24 +0300 | [diff] [blame] | 2851 | for (i = 0; i < AMBA_NR_IRQS; i++) { |
Michal Simek | e98b3ca | 2013-09-30 08:50:48 +0200 | [diff] [blame] | 2852 | irq = adev->irq[i]; |
| 2853 | if (irq) { |
| 2854 | ret = devm_request_irq(&adev->dev, irq, |
| 2855 | pl330_irq_handler, 0, |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2856 | dev_name(&adev->dev), pl330); |
Michal Simek | e98b3ca | 2013-09-30 08:50:48 +0200 | [diff] [blame] | 2857 | if (ret) |
| 2858 | return ret; |
| 2859 | } else { |
| 2860 | break; |
| 2861 | } |
| 2862 | } |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2863 | |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2864 | pcfg = &pl330->pcfg; |
| 2865 | |
| 2866 | pcfg->periph_id = adev->periphid; |
| 2867 | ret = pl330_add(pl330); |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2868 | if (ret) |
Michal Simek | 173e838 | 2013-09-04 16:40:17 +0200 | [diff] [blame] | 2869 | return ret; |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2870 | |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2871 | INIT_LIST_HEAD(&pl330->desc_pool); |
| 2872 | spin_lock_init(&pl330->pool_lock); |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2873 | |
| 2874 | /* Create a descriptor pool of default size */ |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2875 | if (!add_desc(pl330, GFP_KERNEL, NR_DEFAULT_DESC)) |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2876 | dev_warn(&adev->dev, "unable to allocate desc\n"); |
| 2877 | |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2878 | INIT_LIST_HEAD(&pd->channels); |
| 2879 | |
| 2880 | /* Initialize channel parameters */ |
Olof Johansson | c847382 | 2012-04-08 16:26:19 -0700 | [diff] [blame] | 2881 | if (pdat) |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2882 | num_chan = max_t(int, pdat->nr_valid_peri, pcfg->num_chan); |
Olof Johansson | c847382 | 2012-04-08 16:26:19 -0700 | [diff] [blame] | 2883 | else |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2884 | num_chan = max_t(int, pcfg->num_peri, pcfg->num_chan); |
Olof Johansson | c847382 | 2012-04-08 16:26:19 -0700 | [diff] [blame] | 2885 | |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2886 | pl330->num_peripherals = num_chan; |
Lars-Peter Clausen | 70cbb16 | 2014-01-11 20:08:39 +0100 | [diff] [blame] | 2887 | |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2888 | pl330->peripherals = kzalloc(num_chan * sizeof(*pch), GFP_KERNEL); |
| 2889 | if (!pl330->peripherals) { |
Sachin Kamat | 61c6e75 | 2012-09-17 15:20:23 +0530 | [diff] [blame] | 2890 | ret = -ENOMEM; |
Sachin Kamat | e4d43c1 | 2012-11-15 06:27:50 +0000 | [diff] [blame] | 2891 | goto probe_err2; |
Sachin Kamat | 61c6e75 | 2012-09-17 15:20:23 +0530 | [diff] [blame] | 2892 | } |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2893 | |
Rob Herring | 4e0e610 | 2011-07-25 16:05:04 -0500 | [diff] [blame] | 2894 | for (i = 0; i < num_chan; i++) { |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2895 | pch = &pl330->peripherals[i]; |
Thomas Abraham | 93ed554 | 2011-10-24 11:43:31 +0200 | [diff] [blame] | 2896 | if (!adev->dev.of_node) |
| 2897 | pch->chan.private = pdat ? &pdat->peri_id[i] : NULL; |
| 2898 | else |
| 2899 | pch->chan.private = adev->dev.of_node; |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2900 | |
Lars-Peter Clausen | 04abf5d | 2014-01-11 20:08:38 +0100 | [diff] [blame] | 2901 | INIT_LIST_HEAD(&pch->submitted_list); |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2902 | INIT_LIST_HEAD(&pch->work_list); |
Lars-Peter Clausen | 39ff861 | 2013-08-27 20:34:05 +0200 | [diff] [blame] | 2903 | INIT_LIST_HEAD(&pch->completed_list); |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2904 | spin_lock_init(&pch->lock); |
Lars-Peter Clausen | 65ad606 | 2014-07-06 20:32:26 +0200 | [diff] [blame] | 2905 | pch->thread = NULL; |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2906 | pch->chan.device = pd; |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2907 | pch->dmac = pl330; |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2908 | |
| 2909 | /* Add the channel to the DMAC list */ |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2910 | list_add_tail(&pch->chan.device_node, &pd->channels); |
| 2911 | } |
| 2912 | |
Thomas Abraham | 93ed554 | 2011-10-24 11:43:31 +0200 | [diff] [blame] | 2913 | if (pdat) { |
Thomas Abraham | cd07251 | 2011-10-24 11:43:11 +0200 | [diff] [blame] | 2914 | pd->cap_mask = pdat->cap_mask; |
Thomas Abraham | 93ed554 | 2011-10-24 11:43:31 +0200 | [diff] [blame] | 2915 | } else { |
Thomas Abraham | cd07251 | 2011-10-24 11:43:11 +0200 | [diff] [blame] | 2916 | dma_cap_set(DMA_MEMCPY, pd->cap_mask); |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2917 | if (pcfg->num_peri) { |
Thomas Abraham | 93ed554 | 2011-10-24 11:43:31 +0200 | [diff] [blame] | 2918 | dma_cap_set(DMA_SLAVE, pd->cap_mask); |
| 2919 | dma_cap_set(DMA_CYCLIC, pd->cap_mask); |
Tushar Behera | 5557a41 | 2012-08-29 10:16:25 +0530 | [diff] [blame] | 2920 | dma_cap_set(DMA_PRIVATE, pd->cap_mask); |
Thomas Abraham | 93ed554 | 2011-10-24 11:43:31 +0200 | [diff] [blame] | 2921 | } |
| 2922 | } |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2923 | |
| 2924 | pd->device_alloc_chan_resources = pl330_alloc_chan_resources; |
| 2925 | pd->device_free_chan_resources = pl330_free_chan_resources; |
| 2926 | pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy; |
Boojin Kim | 42bc9cf | 2011-09-02 09:44:33 +0900 | [diff] [blame] | 2927 | pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic; |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2928 | pd->device_tx_status = pl330_tx_status; |
| 2929 | pd->device_prep_slave_sg = pl330_prep_slave_sg; |
Maxime Ripard | 740aa95 | 2014-11-17 14:42:29 +0100 | [diff] [blame] | 2930 | pd->device_config = pl330_config; |
Robert Baldyga | 88987d2 | 2015-02-11 13:23:18 +0100 | [diff] [blame] | 2931 | pd->device_pause = pl330_pause; |
Maxime Ripard | 740aa95 | 2014-11-17 14:42:29 +0100 | [diff] [blame] | 2932 | pd->device_terminate_all = pl330_terminate_all; |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2933 | pd->device_issue_pending = pl330_issue_pending; |
Maxime Ripard | dcabe456 | 2014-11-17 14:42:50 +0100 | [diff] [blame] | 2934 | pd->src_addr_widths = PL330_DMA_BUSWIDTHS; |
| 2935 | pd->dst_addr_widths = PL330_DMA_BUSWIDTHS; |
| 2936 | pd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); |
Robert Baldyga | aee4d1f | 2015-02-11 13:23:17 +0100 | [diff] [blame] | 2937 | pd->residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; |
Shawn Lin | 86a8ce7 | 2016-01-22 19:06:51 +0800 | [diff] [blame] | 2938 | pd->max_burst = ((pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP) ? |
| 2939 | 1 : PL330_MAX_BURST); |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2940 | |
| 2941 | ret = dma_async_device_register(pd); |
| 2942 | if (ret) { |
| 2943 | dev_err(&adev->dev, "unable to register DMAC\n"); |
Padmavathi Venna | 0b94c57 | 2013-03-05 14:55:31 +0530 | [diff] [blame] | 2944 | goto probe_err3; |
| 2945 | } |
| 2946 | |
| 2947 | if (adev->dev.of_node) { |
| 2948 | ret = of_dma_controller_register(adev->dev.of_node, |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2949 | of_dma_pl330_xlate, pl330); |
Padmavathi Venna | 0b94c57 | 2013-03-05 14:55:31 +0530 | [diff] [blame] | 2950 | if (ret) { |
| 2951 | dev_err(&adev->dev, |
| 2952 | "unable to register DMA to the generic DT DMA helpers\n"); |
| 2953 | } |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2954 | } |
Lars-Peter Clausen | b714b84 | 2013-11-25 16:07:46 +0100 | [diff] [blame] | 2955 | |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2956 | adev->dev.dma_parms = &pl330->dma_parms; |
Lars-Peter Clausen | b714b84 | 2013-11-25 16:07:46 +0100 | [diff] [blame] | 2957 | |
Vinod Koul | dbaf6d8 | 2013-09-02 21:54:48 +0530 | [diff] [blame] | 2958 | /* |
| 2959 | * This is the limit for transfers with a buswidth of 1, larger |
| 2960 | * buswidths will have larger limits. |
| 2961 | */ |
| 2962 | ret = dma_set_max_seg_size(&adev->dev, 1900800); |
| 2963 | if (ret) |
| 2964 | dev_err(&adev->dev, "unable to set the seg size\n"); |
| 2965 | |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2966 | |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2967 | dev_info(&adev->dev, |
Liviu Dudau | 1f0a5cb | 2014-11-06 17:20:12 +0000 | [diff] [blame] | 2968 | "Loaded driver for PL330 DMAC-%x\n", adev->periphid); |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2969 | dev_info(&adev->dev, |
| 2970 | "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n", |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2971 | pcfg->data_buf_dep, pcfg->data_bus_width / 8, pcfg->num_chan, |
| 2972 | pcfg->num_peri, pcfg->num_events); |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2973 | |
Krzysztof Kozlowski | ae43b32 | 2014-11-14 09:48:57 +0100 | [diff] [blame] | 2974 | pm_runtime_irq_safe(&adev->dev); |
| 2975 | pm_runtime_use_autosuspend(&adev->dev); |
| 2976 | pm_runtime_set_autosuspend_delay(&adev->dev, PL330_AUTOSUSPEND_DELAY); |
| 2977 | pm_runtime_mark_last_busy(&adev->dev); |
| 2978 | pm_runtime_put_autosuspend(&adev->dev); |
| 2979 | |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2980 | return 0; |
Padmavathi Venna | 0b94c57 | 2013-03-05 14:55:31 +0530 | [diff] [blame] | 2981 | probe_err3: |
Padmavathi Venna | 0b94c57 | 2013-03-05 14:55:31 +0530 | [diff] [blame] | 2982 | /* Idle the DMAC */ |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2983 | list_for_each_entry_safe(pch, _p, &pl330->ddma.channels, |
Padmavathi Venna | 0b94c57 | 2013-03-05 14:55:31 +0530 | [diff] [blame] | 2984 | chan.device_node) { |
| 2985 | |
| 2986 | /* Remove the channel */ |
| 2987 | list_del(&pch->chan.device_node); |
| 2988 | |
| 2989 | /* Flush the channel */ |
Krzysztof Kozlowski | 0f5ebab | 2014-09-29 14:42:20 +0200 | [diff] [blame] | 2990 | if (pch->thread) { |
Maxime Ripard | 740aa95 | 2014-11-17 14:42:29 +0100 | [diff] [blame] | 2991 | pl330_terminate_all(&pch->chan); |
Krzysztof Kozlowski | 0f5ebab | 2014-09-29 14:42:20 +0200 | [diff] [blame] | 2992 | pl330_free_chan_resources(&pch->chan); |
| 2993 | } |
Padmavathi Venna | 0b94c57 | 2013-03-05 14:55:31 +0530 | [diff] [blame] | 2994 | } |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2995 | probe_err2: |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 2996 | pl330_del(pl330); |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 2997 | |
| 2998 | return ret; |
| 2999 | } |
| 3000 | |
Greg Kroah-Hartman | 4bf27b8 | 2012-12-21 15:09:59 -0800 | [diff] [blame] | 3001 | static int pl330_remove(struct amba_device *adev) |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 3002 | { |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 3003 | struct pl330_dmac *pl330 = amba_get_drvdata(adev); |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 3004 | struct dma_pl330_chan *pch, *_p; |
Vinod Koul | 46cf94d | 2016-07-05 10:02:16 +0530 | [diff] [blame] | 3005 | int i, irq; |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 3006 | |
Krzysztof Kozlowski | ae43b32 | 2014-11-14 09:48:57 +0100 | [diff] [blame] | 3007 | pm_runtime_get_noresume(pl330->ddma.dev); |
| 3008 | |
Padmavathi Venna | 0b94c57 | 2013-03-05 14:55:31 +0530 | [diff] [blame] | 3009 | if (adev->dev.of_node) |
| 3010 | of_dma_controller_free(adev->dev.of_node); |
Padmavathi Venna | 421da89 | 2013-02-14 09:10:07 +0530 | [diff] [blame] | 3011 | |
Vinod Koul | 46cf94d | 2016-07-05 10:02:16 +0530 | [diff] [blame] | 3012 | for (i = 0; i < AMBA_NR_IRQS; i++) { |
| 3013 | irq = adev->irq[i]; |
| 3014 | devm_free_irq(&adev->dev, irq, pl330); |
| 3015 | } |
| 3016 | |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 3017 | dma_async_device_unregister(&pl330->ddma); |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 3018 | |
| 3019 | /* Idle the DMAC */ |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 3020 | list_for_each_entry_safe(pch, _p, &pl330->ddma.channels, |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 3021 | chan.device_node) { |
| 3022 | |
| 3023 | /* Remove the channel */ |
| 3024 | list_del(&pch->chan.device_node); |
| 3025 | |
| 3026 | /* Flush the channel */ |
Krzysztof Kozlowski | 6e4a2a8 | 2014-09-29 14:42:21 +0200 | [diff] [blame] | 3027 | if (pch->thread) { |
Maxime Ripard | 740aa95 | 2014-11-17 14:42:29 +0100 | [diff] [blame] | 3028 | pl330_terminate_all(&pch->chan); |
Krzysztof Kozlowski | 6e4a2a8 | 2014-09-29 14:42:21 +0200 | [diff] [blame] | 3029 | pl330_free_chan_resources(&pch->chan); |
| 3030 | } |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 3031 | } |
| 3032 | |
Lars-Peter Clausen | f6f2421 | 2014-07-06 20:32:29 +0200 | [diff] [blame] | 3033 | pl330_del(pl330); |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 3034 | |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 3035 | return 0; |
| 3036 | } |
| 3037 | |
| 3038 | static struct amba_id pl330_ids[] = { |
| 3039 | { |
| 3040 | .id = 0x00041330, |
| 3041 | .mask = 0x000fffff, |
| 3042 | }, |
| 3043 | { 0, 0 }, |
| 3044 | }; |
| 3045 | |
Dave Martin | e8fa516 | 2011-10-05 15:15:20 +0100 | [diff] [blame] | 3046 | MODULE_DEVICE_TABLE(amba, pl330_ids); |
| 3047 | |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 3048 | static struct amba_driver pl330_driver = { |
| 3049 | .drv = { |
| 3050 | .owner = THIS_MODULE, |
| 3051 | .name = "dma-pl330", |
Krzysztof Kozlowski | b816ccc | 2014-11-18 12:17:56 +0100 | [diff] [blame] | 3052 | .pm = &pl330_pm, |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 3053 | }, |
| 3054 | .id_table = pl330_ids, |
| 3055 | .probe = pl330_probe, |
| 3056 | .remove = pl330_remove, |
| 3057 | }; |
| 3058 | |
viresh kumar | 9e5ed09 | 2012-03-15 10:40:38 +0100 | [diff] [blame] | 3059 | module_amba_driver(pl330_driver); |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 3060 | |
Jassi Brar | 046209f | 2014-12-05 19:07:49 +0530 | [diff] [blame] | 3061 | MODULE_AUTHOR("Jaswinder Singh <jassisinghbrar@gmail.com>"); |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 3062 | MODULE_DESCRIPTION("API Driver for PL330 DMAC"); |
| 3063 | MODULE_LICENSE("GPL"); |