Blame - drivers/pinctrl/sunxi/Kconfig - kernel/msm-4.19

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Maxime Ripard	5f91077	2014-04-18 18:53:02 +0200	[diff] [blame]	1	if ARCH_SUNXI
				2
Masahiro Yamada	3a42a04	2016-01-24 00:32:09 +0900	[diff] [blame]	3	config PINCTRL_SUNXI
Maxime Ripard	118c565	2014-05-22 16:47:12 +0200	[diff] [blame]	4	bool
Maxime Ripard	5f91077	2014-04-18 18:53:02 +0200	[diff] [blame]	5	select PINMUX
				6	select GENERIC_PINCONF
Icenowy Zheng	9396f44	2017-03-01 03:08:15 +0800	[diff] [blame]	7	select GPIOLIB
Maxime Ripard	5f91077	2014-04-18 18:53:02 +0200	[diff] [blame]	8
Maxime Ripard	340ba6c	2014-04-26 17:06:57 +0200	[diff] [blame]	9	config PINCTRL_SUN4I_A10
Maxime Ripard	d9ff081	2014-06-29 15:58:19 +0200	[diff] [blame]	10	def_bool MACH_SUN4I
Masahiro Yamada	3a42a04	2016-01-24 00:32:09 +0900	[diff] [blame]	11	select PINCTRL_SUNXI
Maxime Ripard	340ba6c	2014-04-26 17:06:57 +0200	[diff] [blame]	12
Maxime Ripard	858f559	2017-01-08 22:31:16 +0100	[diff] [blame]	13	config PINCTRL_SUN5I
Maxime Ripard	d9ff081	2014-06-29 15:58:19 +0200	[diff] [blame]	14	def_bool MACH_SUN5I
Masahiro Yamada	3a42a04	2016-01-24 00:32:09 +0900	[diff] [blame]	15	select PINCTRL_SUNXI
Maxime Ripard	340ba6c	2014-04-26 17:06:57 +0200	[diff] [blame]	16
Maxime Ripard	340ba6c	2014-04-26 17:06:57 +0200	[diff] [blame]	17	config PINCTRL_SUN6I_A31
Maxime Ripard	d9ff081	2014-06-29 15:58:19 +0200	[diff] [blame]	18	def_bool MACH_SUN6I
Masahiro Yamada	3a42a04	2016-01-24 00:32:09 +0900	[diff] [blame]	19	select PINCTRL_SUNXI
Maxime Ripard	340ba6c	2014-04-26 17:06:57 +0200	[diff] [blame]	20
				21	config PINCTRL_SUN6I_A31_R
Maxime Ripard	d9ff081	2014-06-29 15:58:19 +0200	[diff] [blame]	22	def_bool MACH_SUN6I
Maxime Ripard	de5af04	2014-05-23 20:50:43 +0200	[diff] [blame]	23	depends on RESET_CONTROLLER
Masahiro Yamada	3a42a04	2016-01-24 00:32:09 +0900	[diff] [blame]	24	select PINCTRL_SUNXI
Maxime Ripard	340ba6c	2014-04-26 17:06:57 +0200	[diff] [blame]	25
				26	config PINCTRL_SUN7I_A20
Maxime Ripard	d9ff081	2014-06-29 15:58:19 +0200	[diff] [blame]	27	def_bool MACH_SUN7I
Masahiro Yamada	3a42a04	2016-01-24 00:32:09 +0900	[diff] [blame]	28	select PINCTRL_SUNXI
Maxime Ripard	340ba6c	2014-04-26 17:06:57 +0200	[diff] [blame]	29
Chen-Yu Tsai	4c821d1	2014-06-17 22:52:51 +0800	[diff] [blame]	30	config PINCTRL_SUN8I_A23
				31	def_bool MACH_SUN8I
Masahiro Yamada	3a42a04	2016-01-24 00:32:09 +0900	[diff] [blame]	32	select PINCTRL_SUNXI
Chen-Yu Tsai	4c821d1	2014-06-17 22:52:51 +0800	[diff] [blame]	33
Vishnu Patekar	7164873	2015-06-02 11:08:40 +0200	[diff] [blame]	34	config PINCTRL_SUN8I_A33
				35	def_bool MACH_SUN8I
Masahiro Yamada	3a42a04	2016-01-24 00:32:09 +0900	[diff] [blame]	36	select PINCTRL_SUNXI
Vishnu Patekar	7164873	2015-06-02 11:08:40 +0200	[diff] [blame]	37
Vishnu Patekar	4730f33	2015-09-22 23:38:55 +0800	[diff] [blame]	38	config PINCTRL_SUN8I_A83T
				39	def_bool MACH_SUN8I
Masahiro Yamada	3a42a04	2016-01-24 00:32:09 +0900	[diff] [blame]	40	select PINCTRL_SUNXI
Vishnu Patekar	4730f33	2015-09-22 23:38:55 +0800	[diff] [blame]	41
Chen-Yu Tsai	d22bf40	2014-06-17 22:52:52 +0800	[diff] [blame]	42	config PINCTRL_SUN8I_A23_R
				43	def_bool MACH_SUN8I
				44	depends on RESET_CONTROLLER
Masahiro Yamada	3a42a04	2016-01-24 00:32:09 +0900	[diff] [blame]	45	select PINCTRL_SUNXI
Chen-Yu Tsai	d22bf40	2014-06-17 22:52:52 +0800	[diff] [blame]	46
Jens Kuske	e87623c	2015-12-04 22:24:41 +0100	[diff] [blame]	47	config PINCTRL_SUN8I_H3
				48	def_bool MACH_SUN8I
Masahiro Yamada	3a42a04	2016-01-24 00:32:09 +0900	[diff] [blame]	49	select PINCTRL_SUNXI
Jens Kuske	e87623c	2015-12-04 22:24:41 +0100	[diff] [blame]	50
Krzysztof Adamski	ba83a11	2016-02-02 22:21:51 +0100	[diff] [blame]	51	config PINCTRL_SUN8I_H3_R
Icenowy Zheng	082bc28	2017-03-02 02:01:07 +0800	[diff] [blame]	52	def_bool MACH_SUN8I \|\| (ARM64 && ARCH_SUNXI)
				53	select PINCTRL_SUNXI
Krzysztof Adamski	ba83a11	2016-02-02 22:21:51 +0100	[diff] [blame]	54
Icenowy Zheng	56d9e4a	2017-01-03 23:16:27 +0800	[diff] [blame]	55	config PINCTRL_SUN8I_V3S
				56	def_bool MACH_SUN8I
				57	select PINCTRL_SUNXI
				58
Maxime Ripard	d5e9fb3	2014-10-28 22:41:27 +0100	[diff] [blame]	59	config PINCTRL_SUN9I_A80
				60	def_bool MACH_SUN9I
Masahiro Yamada	3a42a04	2016-01-24 00:32:09 +0900	[diff] [blame]	61	select PINCTRL_SUNXI
Maxime Ripard	d5e9fb3	2014-10-28 22:41:27 +0100	[diff] [blame]	62
Maxime Ripard	0eccc9c	2015-12-17 00:39:42 +0800	[diff] [blame]	63	config PINCTRL_SUN9I_A80_R
				64	def_bool MACH_SUN9I
				65	depends on RESET_CONTROLLER
Masahiro Yamada	3a42a04	2016-01-24 00:32:09 +0900	[diff] [blame]	66	select PINCTRL_SUNXI
Maxime Ripard	0eccc9c	2015-12-17 00:39:42 +0800	[diff] [blame]	67
Andre Przywara	96851d3	2016-03-08 16:37:59 +0700	[diff] [blame]	68	config PINCTRL_SUN50I_A64
Icenowy Zheng	082bc28	2017-03-02 02:01:07 +0800	[diff] [blame]	69	def_bool ARM64 && ARCH_SUNXI
Andre Przywara	96851d3	2016-03-08 16:37:59 +0700	[diff] [blame]	70	select PINCTRL_SUNXI
				71
Icenowy Zheng	14c868b	2017-03-02 02:09:30 +0800	[diff] [blame]	72	config PINCTRL_SUN50I_A64_R
				73	def_bool ARM64 && ARCH_SUNXI
				74	select PINCTRL_SUNXI
				75
Icenowy Zheng	838adb5	2017-01-26 23:48:51 +0800	[diff] [blame]	76	config PINCTRL_SUN50I_H5
Icenowy Zheng	082bc28	2017-03-02 02:01:07 +0800	[diff] [blame]	77	def_bool ARM64 && ARCH_SUNXI
Icenowy Zheng	838adb5	2017-01-26 23:48:51 +0800	[diff] [blame]	78	select PINCTRL_SUNXI
				79
Maxime Ripard	5f91077	2014-04-18 18:53:02 +0200	[diff] [blame]	80	endif