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Thomas Abraham0561cea2011-11-02 19:31:15 +09001/*
2 * Samsung's Exynos4210 SoC device tree source
3 *
4 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 * Copyright (c) 2010-2011 Linaro Ltd.
7 * www.linaro.org
8 *
9 * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
10 * based board files can include this file and provide values for board specfic
11 * bindings.
12 *
13 * Note: This file does not include device nodes for all the controllers in
14 * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
15 * nodes can be added to this file.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20*/
21
Padmavathi Venna37992792013-06-18 00:02:08 +090022#include "exynos4.dtsi"
23#include "exynos4210-pinctrl.dtsi"
Lukasz Majewski9843a222015-01-30 08:26:03 +090024#include "exynos4-cpu-thermal.dtsi"
Thomas Abraham0561cea2011-11-02 19:31:15 +090025
26/ {
Sachin Kamat8bdb31b2014-03-21 02:17:22 +090027 compatible = "samsung,exynos4210", "samsung,exynos4";
Thomas Abraham0561cea2011-11-02 19:31:15 +090028
Thomas Abraham4980c392012-07-14 10:45:32 +090029 aliases {
Thomas Abraham87711d82012-09-07 06:14:26 +090030 pinctrl0 = &pinctrl_0;
31 pinctrl1 = &pinctrl_1;
32 pinctrl2 = &pinctrl_2;
Thomas Abraham4980c392012-07-14 10:45:32 +090033 };
34
Bartlomiej Zolnierkiewicze5409202014-09-25 17:40:14 +090035 cpus {
36 #address-cells = <1>;
37 #size-cells = <0>;
38
Lukasz Majewskibf4a0be2015-01-30 08:26:02 +090039 cpu0: cpu@900 {
Bartlomiej Zolnierkiewicze5409202014-09-25 17:40:14 +090040 device_type = "cpu";
41 compatible = "arm,cortex-a9";
42 reg = <0x900>;
Thomas Abraham300bde72015-04-03 18:43:47 +020043 clocks = <&clock CLK_ARM_CLK>;
44 clock-names = "cpu";
45 clock-latency = <160000>;
46
47 operating-points = <
48 1200000 1250000
49 1000000 1150000
50 800000 1075000
51 500000 975000
52 400000 975000
53 200000 950000
54 >;
Lukasz Majewskibf4a0be2015-01-30 08:26:02 +090055 cooling-min-level = <4>;
56 cooling-max-level = <2>;
57 #cooling-cells = <2>; /* min followed by max */
Bartlomiej Zolnierkiewicze5409202014-09-25 17:40:14 +090058 };
59
60 cpu@901 {
61 device_type = "cpu";
62 compatible = "arm,cortex-a9";
63 reg = <0x901>;
64 };
65 };
66
Krzysztof Kozlowski9c412212015-05-13 19:24:35 +090067 sysram: sysram@02020000 {
Sachin Kamatb3205de2014-05-13 07:13:44 +090068 compatible = "mmio-sram";
69 reg = <0x02020000 0x20000>;
70 #address-cells = <1>;
71 #size-cells = <1>;
72 ranges = <0 0x02020000 0x20000>;
73
74 smp-sysram@0 {
75 compatible = "samsung,exynos4210-sysram";
76 reg = <0x0 0x1000>;
77 };
78
79 smp-sysram@1f000 {
80 compatible = "samsung,exynos4210-sysram-ns";
81 reg = <0x1f000 0x1000>;
82 };
83 };
84
Tomasz Figa91d88f02012-11-22 00:22:09 +090085 pd_lcd1: lcd1-power-domain@10023CA0 {
86 compatible = "samsung,exynos4210-pd";
87 reg = <0x10023CA0 0x20>;
Marek Szyprowski0da65872015-01-24 13:16:15 +090088 #power-domain-cells = <0>;
Tomasz Figa91d88f02012-11-22 00:22:09 +090089 };
90
Tomasz Figa56b60b82015-01-08 07:54:34 +010091 l2c: l2-cache-controller@10502000 {
92 compatible = "arm,pl310-cache";
93 reg = <0x10502000 0x1000>;
94 cache-unified;
95 cache-level = <2>;
96 arm,tag-latency = <2 2 1>;
97 arm,data-latency = <2 2 1>;
98 };
99
Krzysztof Kozlowski9c412212015-05-13 19:24:35 +0900100 mct: mct@10050000 {
Thomas Abrahambbd97002013-03-09 16:12:35 +0900101 compatible = "samsung,exynos4210-mct";
102 reg = <0x10050000 0x800>;
Thomas Abrahambbd97002013-03-09 16:12:35 +0900103 interrupt-parent = <&mct_map>;
Tomasz Figa84ee1c152013-12-19 03:17:49 +0900104 interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
Andrzej Hajda1c75a782014-02-26 09:53:30 +0900105 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
Thomas Abraham7ad34332013-03-09 17:11:38 +0900106 clock-names = "fin_pll", "mct";
Thomas Abrahambbd97002013-03-09 16:12:35 +0900107
108 mct_map: mct-map {
Tomasz Figa84ee1c152013-12-19 03:17:49 +0900109 #interrupt-cells = <1>;
Thomas Abrahambbd97002013-03-09 16:12:35 +0900110 #address-cells = <0>;
111 #size-cells = <0>;
Tomasz Figa84ee1c152013-12-19 03:17:49 +0900112 interrupt-map = <0 &gic 0 57 0>,
113 <1 &gic 0 69 0>,
114 <2 &combiner 12 6>,
115 <3 &combiner 12 7>,
116 <4 &gic 0 42 0>,
117 <5 &gic 0 48 0>;
Thomas Abrahambbd97002013-03-09 16:12:35 +0900118 };
119 };
120
Lee Jonese7787aed2013-08-06 03:04:43 +0900121 clock: clock-controller@10030000 {
Thomas Abrahamd8bafc82013-03-09 17:11:33 +0900122 compatible = "samsung,exynos4210-clock";
123 reg = <0x10030000 0x20000>;
124 #clock-cells = <1>;
125 };
126
Thomas Abraham87711d82012-09-07 06:14:26 +0900127 pinctrl_0: pinctrl@11400000 {
Kukjin Kimb533c862013-01-02 16:05:42 -0800128 compatible = "samsung,exynos4210-pinctrl";
Thomas Abraham87711d82012-09-07 06:14:26 +0900129 reg = <0x11400000 0x1000>;
130 interrupts = <0 47 0>;
Thomas Abraham87711d82012-09-07 06:14:26 +0900131 };
132
133 pinctrl_1: pinctrl@11000000 {
Kukjin Kimb533c862013-01-02 16:05:42 -0800134 compatible = "samsung,exynos4210-pinctrl";
Thomas Abraham87711d82012-09-07 06:14:26 +0900135 reg = <0x11000000 0x1000>;
136 interrupts = <0 46 0>;
Thomas Abraham87711d82012-09-07 06:14:26 +0900137
138 wakup_eint: wakeup-interrupt-controller {
139 compatible = "samsung,exynos4210-wakeup-eint";
140 interrupt-parent = <&gic>;
Tomasz Figaa04b07c2012-10-11 10:11:18 +0200141 interrupts = <0 32 0>;
Thomas Abraham87711d82012-09-07 06:14:26 +0900142 };
143 };
144
145 pinctrl_2: pinctrl@03860000 {
Kukjin Kimb533c862013-01-02 16:05:42 -0800146 compatible = "samsung,exynos4210-pinctrl";
Thomas Abraham87711d82012-09-07 06:14:26 +0900147 reg = <0x03860000 0x1000>;
148 };
149
Lukasz Majewski9843a222015-01-30 08:26:03 +0900150 tmu: tmu@100C0000 {
Amit Daniel Kachhap8d4155d2012-10-29 21:18:01 +0900151 compatible = "samsung,exynos4210-tmu";
152 interrupt-parent = <&combiner>;
153 reg = <0x100C0000 0x100>;
154 interrupts = <2 4>;
Andrzej Hajda1c75a782014-02-26 09:53:30 +0900155 clocks = <&clock CLK_TMU_APBIF>;
Sachin Kamate6199af2013-04-23 23:20:19 +0900156 clock-names = "tmu_apbif";
Lukasz Majewski9843a222015-01-30 08:26:03 +0900157 samsung,tmu_gain = <15>;
158 samsung,tmu_reference_voltage = <7>;
Sachin Kamate6199af2013-04-23 23:20:19 +0900159 status = "disabled";
Amit Daniel Kachhap8d4155d2012-10-29 21:18:01 +0900160 };
Sachin Kamat66d302a2013-04-04 13:48:45 +0900161
Lukasz Majewski9843a222015-01-30 08:26:03 +0900162 thermal-zones {
163 cpu_thermal: cpu-thermal {
164 polling-delay-passive = <0>;
165 polling-delay = <0>;
166 thermal-sensors = <&tmu 0>;
167
168 trips {
169 cpu_alert0: cpu-alert-0 {
170 temperature = <85000>; /* millicelsius */
171 };
172 cpu_alert1: cpu-alert-1 {
173 temperature = <100000>; /* millicelsius */
174 };
175 cpu_alert2: cpu-alert-2 {
176 temperature = <110000>; /* millicelsius */
177 };
178 };
179 };
180 };
181
Krzysztof Kozlowski9c412212015-05-13 19:24:35 +0900182 g2d: g2d@12800000 {
Sachin Kamat66d302a2013-04-04 13:48:45 +0900183 compatible = "samsung,s5pv210-g2d";
184 reg = <0x12800000 0x1000>;
185 interrupts = <0 89 0>;
Andrzej Hajda1c75a782014-02-26 09:53:30 +0900186 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
Sachin Kamat37bf5792013-06-10 17:52:24 +0900187 clock-names = "sclk_fimg2d", "fimg2d";
Marek Szyprowski25cd01b2015-11-25 13:55:26 +0100188 power-domains = <&pd_lcd0>;
Marek Szyprowski71d3a9f2015-06-04 08:09:41 +0900189 iommus = <&sysmmu_g2d>;
Sachin Kamat66d302a2013-04-04 13:48:45 +0900190 };
Sylwester Nawrocki54a88962013-08-06 02:49:45 +0900191
192 camera {
Andrzej Hajda1c75a782014-02-26 09:53:30 +0900193 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
194 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
Sylwester Nawrocki54a88962013-08-06 02:49:45 +0900195 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
196
197 fimc_0: fimc@11800000 {
198 samsung,pix-limits = <4224 8192 1920 4224>;
199 samsung,mainscaler-ext;
200 samsung,cam-if;
201 };
202
203 fimc_1: fimc@11810000 {
204 samsung,pix-limits = <4224 8192 1920 4224>;
205 samsung,mainscaler-ext;
206 samsung,cam-if;
207 };
208
209 fimc_2: fimc@11820000 {
210 samsung,pix-limits = <4224 8192 1920 4224>;
211 samsung,mainscaler-ext;
212 samsung,lcd-wb;
213 };
214
215 fimc_3: fimc@11830000 {
216 samsung,pix-limits = <1920 8192 1366 1920>;
217 samsung,rotators = <0>;
218 samsung,mainscaler-ext;
219 samsung,lcd-wb;
220 };
221 };
Chanwoo Choi30e0e472015-02-04 08:10:58 +0900222
Marek Szyprowskied80d4c2015-02-04 23:44:16 +0900223 mixer: mixer@12C10000 {
224 clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer",
225 "sclk_mixer";
226 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
227 <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>,
228 <&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>;
229 };
230
Chanwoo Choi30e0e472015-02-04 08:10:58 +0900231 ppmu_lcd1: ppmu_lcd1@12240000 {
232 compatible = "samsung,exynos-ppmu";
233 reg = <0x12240000 0x2000>;
234 clocks = <&clock CLK_PPMULCD1>;
235 clock-names = "ppmu";
236 status = "disabled";
237 };
Marek Szyprowski71d3a9f2015-06-04 08:09:41 +0900238
239 sysmmu_g2d: sysmmu@12A20000 {
240 compatible = "samsung,exynos-sysmmu";
241 reg = <0x12A20000 0x1000>;
242 interrupt-parent = <&combiner>;
243 interrupts = <4 7>;
244 clock-names = "sysmmu", "master";
245 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
246 power-domains = <&pd_lcd0>;
247 #iommu-cells = <0>;
248 };
249
250 sysmmu_fimd1: sysmmu@12220000 {
251 compatible = "samsung,exynos-sysmmu";
252 interrupt-parent = <&combiner>;
253 reg = <0x12220000 0x1000>;
254 interrupts = <5 3>;
255 clock-names = "sysmmu", "master";
256 clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
257 power-domains = <&pd_lcd1>;
258 #iommu-cells = <0>;
259 };
Thomas Abraham0561cea2011-11-02 19:31:15 +0900260};
Krzysztof Kozlowski070bb0f2015-04-06 17:06:44 +0200261
262&gic {
263 cpu-offset = <0x8000>;
264};
265
266&combiner {
267 samsung,combiner-nr = <16>;
268 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
269 <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
270 <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
271 <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
272};
273
Marek Szyprowskif99e9a72015-11-26 13:49:47 +0100274&mdma1 {
275 power-domains = <&pd_lcd0>;
276};
277
Krzysztof Kozlowski070bb0f2015-04-06 17:06:44 +0200278&pmu_system_controller {
279 clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
280 "clkout4", "clkout8", "clkout9";
281 clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
282 <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
283 <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;
284 #clock-cells = <1>;
285};
Marek Szyprowski0c7e90b52015-11-13 14:29:43 +0100286
287&rotator {
288 power-domains = <&pd_lcd0>;
289};
Marek Szyprowski3398a182015-11-13 14:29:44 +0100290
291&sysmmu_rotator {
292 power-domains = <&pd_lcd0>;
293};