Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm-4.19 / b8199ff31f86ee94fa1166997259b03022ecb4de / . / drivers / clk / rockchip / clk-rk3399.c
blob: e8f040be3feae650637095cdcb865d1386882b92 [file] [log] [blame]
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1/*
2 * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
3 * Author: Xing Zheng <zhengxing@rock-chips.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/clk-provider.h>
17#include <linux/of.h>
18#include <linux/of_address.h>
19#include <linux/platform_device.h>
20#include <linux/regmap.h>
21#include <dt-bindings/clock/rk3399-cru.h>
22#include "clk.h"
23
24enum rk3399_plls {
25 lpll, bpll, dpll, cpll, gpll, npll, vpll,
26};
27
28enum rk3399_pmu_plls {
29 ppll,
30};
31
32static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
33 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
34 RK3036_PLL_RATE(2208000000, 1, 92, 1, 1, 1, 0),
35 RK3036_PLL_RATE(2184000000, 1, 91, 1, 1, 1, 0),
36 RK3036_PLL_RATE(2160000000, 1, 90, 1, 1, 1, 0),
37 RK3036_PLL_RATE(2136000000, 1, 89, 1, 1, 1, 0),
38 RK3036_PLL_RATE(2112000000, 1, 88, 1, 1, 1, 0),
39 RK3036_PLL_RATE(2088000000, 1, 87, 1, 1, 1, 0),
40 RK3036_PLL_RATE(2064000000, 1, 86, 1, 1, 1, 0),
41 RK3036_PLL_RATE(2040000000, 1, 85, 1, 1, 1, 0),
42 RK3036_PLL_RATE(2016000000, 1, 84, 1, 1, 1, 0),
43 RK3036_PLL_RATE(1992000000, 1, 83, 1, 1, 1, 0),
44 RK3036_PLL_RATE(1968000000, 1, 82, 1, 1, 1, 0),
45 RK3036_PLL_RATE(1944000000, 1, 81, 1, 1, 1, 0),
46 RK3036_PLL_RATE(1920000000, 1, 80, 1, 1, 1, 0),
47 RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0),
48 RK3036_PLL_RATE(1872000000, 1, 78, 1, 1, 1, 0),
49 RK3036_PLL_RATE(1848000000, 1, 77, 1, 1, 1, 0),
50 RK3036_PLL_RATE(1824000000, 1, 76, 1, 1, 1, 0),
51 RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0),
52 RK3036_PLL_RATE(1776000000, 1, 74, 1, 1, 1, 0),
53 RK3036_PLL_RATE(1752000000, 1, 73, 1, 1, 1, 0),
54 RK3036_PLL_RATE(1728000000, 1, 72, 1, 1, 1, 0),
55 RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0),
56 RK3036_PLL_RATE(1680000000, 1, 70, 1, 1, 1, 0),
57 RK3036_PLL_RATE(1656000000, 1, 69, 1, 1, 1, 0),
58 RK3036_PLL_RATE(1632000000, 1, 68, 1, 1, 1, 0),
59 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
60 RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
61 RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
62 RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
63 RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
64 RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
65 RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
66 RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
67 RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
68 RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
69 RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
70 RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
71 RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
72 RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
73 RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
74 RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
75 RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
76 RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
77 RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
78 RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
79 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
80 RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
81 RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0),
82 RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0),
83 RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0),
84 RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0),
85 RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0),
86 RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0),
87 RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0),
88 RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0),
89 RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0),
90 RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0),
91 RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0),
92 RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0),
93 RK3036_PLL_RATE( 676000000, 3, 169, 2, 1, 1, 0),
94 RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0),
95 RK3036_PLL_RATE( 594000000, 2, 99, 2, 1, 1, 0),
96 RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0),
97 RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0),
98 RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0),
99 RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0),
100 RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0),
101 RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0),
102 { /* sentinel */ },
103};
104
105/* CRU parents */
106PNAME(mux_pll_p) = { "xin24m", "xin32k" };
107
108PNAME(mux_armclkl_p) = { "clk_core_l_lpll_src",
109 "clk_core_l_bpll_src",
110 "clk_core_l_dpll_src",
111 "clk_core_l_gpll_src" };
112PNAME(mux_armclkb_p) = { "clk_core_b_lpll_src",
113 "clk_core_b_bpll_src",
114 "clk_core_b_dpll_src",
115 "clk_core_b_gpll_src" };
116PNAME(mux_aclk_cci_p) = { "cpll_aclk_cci_src",
117 "gpll_aclk_cci_src",
118 "npll_aclk_cci_src",
119 "vpll_aclk_cci_src" };
Heiko Stuebner995d3fd2016-04-19 21:07:01 +0200[diff] [blame]120PNAME(mux_cci_trace_p) = { "cpll_cci_trace",
121 "gpll_cci_trace" };
122PNAME(mux_cs_p) = { "cpll_cs", "gpll_cs",
123 "npll_cs"};
124PNAME(mux_aclk_perihp_p) = { "cpll_aclk_perihp_src",
125 "gpll_aclk_perihp_src" };
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]126
127PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
128PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" };
129PNAME(mux_pll_src_cpll_gpll_ppll_p) = { "cpll", "gpll", "ppll" };
130PNAME(mux_pll_src_cpll_gpll_upll_p) = { "cpll", "gpll", "upll" };
131PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" };
Heiko Stuebner995d3fd2016-04-19 21:07:01 +0200[diff] [blame]132PNAME(mux_pll_src_cpll_gpll_npll_ppll_p) = { "cpll", "gpll", "npll",
133 "ppll" };
134PNAME(mux_pll_src_cpll_gpll_npll_24m_p) = { "cpll", "gpll", "npll",
135 "xin24m" };
136PNAME(mux_pll_src_cpll_gpll_npll_usbphy480m_p) = { "cpll", "gpll", "npll",
137 "clk_usbphy_480m" };
138PNAME(mux_pll_src_ppll_cpll_gpll_npll_p) = { "ppll", "cpll", "gpll",
139 "npll", "upll" };
140PNAME(mux_pll_src_cpll_gpll_npll_upll_24m_p) = { "cpll", "gpll", "npll",
141 "upll", "xin24m" };
142PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll",
143 "ppll", "upll", "xin24m" };
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]144
145PNAME(mux_pll_src_vpll_cpll_gpll_p) = { "vpll", "cpll", "gpll" };
Heiko Stuebner995d3fd2016-04-19 21:07:01 +0200[diff] [blame]146PNAME(mux_pll_src_vpll_cpll_gpll_npll_p) = { "vpll", "cpll", "gpll",
147 "npll" };
148PNAME(mux_pll_src_vpll_cpll_gpll_24m_p) = { "vpll", "cpll", "gpll",
149 "xin24m" };
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]150
Heiko Stuebner995d3fd2016-04-19 21:07:01 +0200[diff] [blame]151PNAME(mux_dclk_vop0_p) = { "dclk_vop0_div",
152 "dclk_vop0_frac" };
153PNAME(mux_dclk_vop1_p) = { "dclk_vop1_div",
154 "dclk_vop1_frac" };
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]155
Heiko Stuebner995d3fd2016-04-19 21:07:01 +0200[diff] [blame]156PNAME(mux_clk_cif_p) = { "clk_cifout_div", "xin24m" };
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]157
Heiko Stuebner995d3fd2016-04-19 21:07:01 +0200[diff] [blame]158PNAME(mux_pll_src_24m_usbphy480m_p) = { "xin24m", "clk_usbphy_480m" };
159PNAME(mux_pll_src_24m_pciephy_p) = { "xin24m", "clk_pciephy_ref100m" };
160PNAME(mux_pll_src_24m_32k_cpll_gpll_p) = { "xin24m", "xin32k",
161 "cpll", "gpll" };
162PNAME(mux_pciecore_cru_phy_p) = { "clk_pcie_core_cru",
163 "clk_pcie_core_phy" };
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]164
Heiko Stuebner995d3fd2016-04-19 21:07:01 +0200[diff] [blame]165PNAME(mux_aclk_emmc_p) = { "cpll_aclk_emmc_src",
166 "gpll_aclk_emmc_src" };
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]167
Heiko Stuebner995d3fd2016-04-19 21:07:01 +0200[diff] [blame]168PNAME(mux_aclk_perilp0_p) = { "cpll_aclk_perilp0_src",
169 "gpll_aclk_perilp0_src" };
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]170
Heiko Stuebner995d3fd2016-04-19 21:07:01 +0200[diff] [blame]171PNAME(mux_fclk_cm0s_p) = { "cpll_fclk_cm0s_src",
172 "gpll_fclk_cm0s_src" };
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]173
Heiko Stuebner995d3fd2016-04-19 21:07:01 +0200[diff] [blame]174PNAME(mux_hclk_perilp1_p) = { "cpll_hclk_perilp1_src",
175 "gpll_hclk_perilp1_src" };
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]176
Heiko Stuebner995d3fd2016-04-19 21:07:01 +0200[diff] [blame]177PNAME(mux_clk_testout1_p) = { "clk_testout1_pll_src", "xin24m" };
178PNAME(mux_clk_testout2_p) = { "clk_testout2_pll_src", "xin24m" };
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]179
Heiko Stuebner995d3fd2016-04-19 21:07:01 +0200[diff] [blame]180PNAME(mux_usbphy_480m_p) = { "clk_usbphy0_480m_src",
181 "clk_usbphy1_480m_src" };
182PNAME(mux_aclk_gmac_p) = { "cpll_aclk_gmac_src",
183 "gpll_aclk_gmac_src" };
184PNAME(mux_rmii_p) = { "clk_gmac", "clkin_gmac" };
185PNAME(mux_spdif_p) = { "clk_spdif_div", "clk_spdif_frac",
186 "clkin_i2s", "xin12m" };
187PNAME(mux_i2s0_p) = { "clk_i2s0_div", "clk_i2s0_frac",
188 "clkin_i2s", "xin12m" };
189PNAME(mux_i2s1_p) = { "clk_i2s1_div", "clk_i2s1_frac",
190 "clkin_i2s", "xin12m" };
191PNAME(mux_i2s2_p) = { "clk_i2s2_div", "clk_i2s2_frac",
192 "clkin_i2s", "xin12m" };
193PNAME(mux_i2sch_p) = { "clk_i2s0", "clk_i2s1",
194 "clk_i2s2" };
195PNAME(mux_i2sout_p) = { "clk_i2sout_src", "xin12m" };
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]196
Heiko Stuebner995d3fd2016-04-19 21:07:01 +0200[diff] [blame]197PNAME(mux_uart0_p) = { "clk_uart0_div", "clk_uart0_frac", "xin24m" };
198PNAME(mux_uart1_p) = { "clk_uart1_div", "clk_uart1_frac", "xin24m" };
199PNAME(mux_uart2_p) = { "clk_uart2_div", "clk_uart2_frac", "xin24m" };
200PNAME(mux_uart3_p) = { "clk_uart3_div", "clk_uart3_frac", "xin24m" };
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]201
202/* PMU CRU parents */
Heiko Stuebner995d3fd2016-04-19 21:07:01 +0200[diff] [blame]203PNAME(mux_ppll_24m_p) = { "ppll", "xin24m" };
204PNAME(mux_24m_ppll_p) = { "xin24m", "ppll" };
205PNAME(mux_fclk_cm0s_pmu_ppll_p) = { "fclk_cm0s_pmu_ppll_src", "xin24m" };
206PNAME(mux_wifi_pmu_p) = { "clk_wifi_div", "clk_wifi_frac" };
207PNAME(mux_uart4_pmu_p) = { "clk_uart4_div", "clk_uart4_frac",
208 "xin24m" };
209PNAME(mux_clk_testout2_2io_p) = { "clk_testout2", "clk_32k_suspend_pmu" };
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]210
211static struct rockchip_pll_clock rk3399_pll_clks[] __initdata = {
212 [lpll] = PLL(pll_rk3399, PLL_APLLL, "lpll", mux_pll_p, 0, RK3399_PLL_CON(0),
213 RK3399_PLL_CON(3), 8, 31, 0, rk3399_pll_rates),
214 [bpll] = PLL(pll_rk3399, PLL_APLLB, "bpll", mux_pll_p, 0, RK3399_PLL_CON(8),
215 RK3399_PLL_CON(11), 8, 31, 0, rk3399_pll_rates),
216 [dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RK3399_PLL_CON(16),
217 RK3399_PLL_CON(19), 8, 31, 0, NULL),
218 [cpll] = PLL(pll_rk3399, PLL_CPLL, "cpll", mux_pll_p, 0, RK3399_PLL_CON(24),
219 RK3399_PLL_CON(27), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
220 [gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RK3399_PLL_CON(32),
221 RK3399_PLL_CON(35), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
222 [npll] = PLL(pll_rk3399, PLL_NPLL, "npll", mux_pll_p, 0, RK3399_PLL_CON(40),
223 RK3399_PLL_CON(43), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
224 [vpll] = PLL(pll_rk3399, PLL_VPLL, "vpll", mux_pll_p, 0, RK3399_PLL_CON(48),
225 RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
226};
227
228static struct rockchip_pll_clock rk3399_pmu_pll_clks[] __initdata = {
229 [ppll] = PLL(pll_rk3399, PLL_PPLL, "ppll", mux_pll_p, 0, RK3399_PMU_PLL_CON(0),
230 RK3399_PMU_PLL_CON(3), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
231};
232
233#define MFLAGS CLK_MUX_HIWORD_MASK
234#define DFLAGS CLK_DIVIDER_HIWORD_MASK
235#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
236#define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK
237
238static struct rockchip_clk_branch rk3399_spdif_fracmux __initdata =
239 MUX(0, "clk_spdif_mux", mux_spdif_p, CLK_SET_RATE_PARENT,
240 RK3399_CLKSEL_CON(32), 13, 2, MFLAGS);
241
242static struct rockchip_clk_branch rk3399_i2s0_fracmux __initdata =
243 MUX(0, "clk_i2s0_mux", mux_i2s0_p, CLK_SET_RATE_PARENT,
244 RK3399_CLKSEL_CON(28), 8, 2, MFLAGS);
245
246static struct rockchip_clk_branch rk3399_i2s1_fracmux __initdata =
247 MUX(0, "clk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT,
248 RK3399_CLKSEL_CON(29), 8, 2, MFLAGS);
249
250static struct rockchip_clk_branch rk3399_i2s2_fracmux __initdata =
251 MUX(0, "clk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT,
252 RK3399_CLKSEL_CON(30), 8, 2, MFLAGS);
253
254static struct rockchip_clk_branch rk3399_uart0_fracmux __initdata =
255 MUX(SCLK_UART0, "clk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
256 RK3399_CLKSEL_CON(33), 8, 2, MFLAGS);
257
258static struct rockchip_clk_branch rk3399_uart1_fracmux __initdata =
259 MUX(SCLK_UART1, "clk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
260 RK3399_CLKSEL_CON(34), 8, 2, MFLAGS);
261
262static struct rockchip_clk_branch rk3399_uart2_fracmux __initdata =
263 MUX(SCLK_UART2, "clk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
264 RK3399_CLKSEL_CON(35), 8, 2, MFLAGS);
265
266static struct rockchip_clk_branch rk3399_uart3_fracmux __initdata =
267 MUX(SCLK_UART3, "clk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
268 RK3399_CLKSEL_CON(36), 8, 2, MFLAGS);
269
270static struct rockchip_clk_branch rk3399_uart4_pmu_fracmux __initdata =
271 MUX(SCLK_UART4_PMU, "clk_uart4_pmu", mux_uart4_pmu_p, CLK_SET_RATE_PARENT,
272 RK3399_PMU_CLKSEL_CON(5), 8, 2, MFLAGS);
273
274static struct rockchip_clk_branch rk3399_dclk_vop0_fracmux __initdata =
275 MUX(DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_p, CLK_SET_RATE_PARENT,
276 RK3399_CLKSEL_CON(49), 11, 1, MFLAGS);
277
278static struct rockchip_clk_branch rk3399_dclk_vop1_fracmux __initdata =
279 MUX(DCLK_VOP1, "dclk_vop1", mux_dclk_vop1_p, CLK_SET_RATE_PARENT,
280 RK3399_CLKSEL_CON(50), 11, 1, MFLAGS);
281
282static struct rockchip_clk_branch rk3399_pmuclk_wifi_fracmux __initdata =
283 MUX(SCLK_WIFI_PMU, "clk_wifi_pmu", mux_wifi_pmu_p, CLK_SET_RATE_PARENT,
284 RK3399_PMU_CLKSEL_CON(1), 14, 1, MFLAGS);
285
286static const struct rockchip_cpuclk_reg_data rk3399_cpuclkl_data = {
287 .core_reg = RK3399_CLKSEL_CON(0),
288 .div_core_shift = 0,
289 .div_core_mask = 0x1f,
290 .mux_core_alt = 3,
291 .mux_core_main = 0,
292 .mux_core_shift = 6,
293 .mux_core_mask = 0x3,
294};
295
296static const struct rockchip_cpuclk_reg_data rk3399_cpuclkb_data = {
297 .core_reg = RK3399_CLKSEL_CON(2),
298 .div_core_shift = 0,
299 .div_core_mask = 0x1f,
300 .mux_core_alt = 3,
301 .mux_core_main = 1,
302 .mux_core_shift = 6,
303 .mux_core_mask = 0x3,
304};
305
306#define RK3399_DIV_ACLKM_MASK 0x1f
307#define RK3399_DIV_ACLKM_SHIFT 8
308#define RK3399_DIV_ATCLK_MASK 0x1f
309#define RK3399_DIV_ATCLK_SHIFT 0
310#define RK3399_DIV_PCLK_DBG_MASK 0x1f
311#define RK3399_DIV_PCLK_DBG_SHIFT 8
312
313#define RK3399_CLKSEL0(_offs, _aclkm) \
314 { \
315 .reg = RK3399_CLKSEL_CON(0 + _offs), \
316 .val = HIWORD_UPDATE(_aclkm, RK3399_DIV_ACLKM_MASK, \
317 RK3399_DIV_ACLKM_SHIFT), \
318 }
319#define RK3399_CLKSEL1(_offs, _atclk, _pdbg) \
320 { \
321 .reg = RK3399_CLKSEL_CON(1 + _offs), \
322 .val = HIWORD_UPDATE(_atclk, RK3399_DIV_ATCLK_MASK, \
323 RK3399_DIV_ATCLK_SHIFT) | \
324 HIWORD_UPDATE(_pdbg, RK3399_DIV_PCLK_DBG_MASK, \
325 RK3399_DIV_PCLK_DBG_SHIFT), \
326 }
327
328/* cluster_l: aclkm in clksel0, rest in clksel1 */
329#define RK3399_CPUCLKL_RATE(_prate, _aclkm, _atclk, _pdbg) \
330 { \
331 .prate = _prate##U, \
332 .divs = { \
333 RK3399_CLKSEL0(0, _aclkm), \
334 RK3399_CLKSEL1(0, _atclk, _pdbg), \
335 }, \
336 }
337
338/* cluster_b: aclkm in clksel2, rest in clksel3 */
339#define RK3399_CPUCLKB_RATE(_prate, _aclkm, _atclk, _pdbg) \
340 { \
341 .prate = _prate##U, \
342 .divs = { \
343 RK3399_CLKSEL0(2, _aclkm), \
344 RK3399_CLKSEL1(2, _atclk, _pdbg), \
345 }, \
346 }
347
348static struct rockchip_cpuclk_rate_table rk3399_cpuclkl_rates[] __initdata = {
349 RK3399_CPUCLKL_RATE(1800000000, 1, 8, 8),
350 RK3399_CPUCLKL_RATE(1704000000, 1, 8, 8),
351 RK3399_CPUCLKL_RATE(1608000000, 1, 7, 7),
352 RK3399_CPUCLKL_RATE(1512000000, 1, 7, 7),
353 RK3399_CPUCLKL_RATE(1488000000, 1, 6, 6),
354 RK3399_CPUCLKL_RATE(1416000000, 1, 6, 6),
355 RK3399_CPUCLKL_RATE(1200000000, 1, 5, 5),
356 RK3399_CPUCLKL_RATE(1008000000, 1, 5, 5),
357 RK3399_CPUCLKL_RATE( 816000000, 1, 4, 4),
358 RK3399_CPUCLKL_RATE( 696000000, 1, 3, 3),
359 RK3399_CPUCLKL_RATE( 600000000, 1, 3, 3),
360 RK3399_CPUCLKL_RATE( 408000000, 1, 2, 2),
361 RK3399_CPUCLKL_RATE( 312000000, 1, 1, 1),
362};
363
364static struct rockchip_cpuclk_rate_table rk3399_cpuclkb_rates[] __initdata = {
365 RK3399_CPUCLKB_RATE(2208000000, 1, 11, 11),
366 RK3399_CPUCLKB_RATE(2184000000, 1, 11, 11),
367 RK3399_CPUCLKB_RATE(2088000000, 1, 10, 10),
368 RK3399_CPUCLKB_RATE(2040000000, 1, 10, 10),
369 RK3399_CPUCLKB_RATE(1992000000, 1, 9, 9),
370 RK3399_CPUCLKB_RATE(1896000000, 1, 9, 9),
371 RK3399_CPUCLKB_RATE(1800000000, 1, 8, 8),
372 RK3399_CPUCLKB_RATE(1704000000, 1, 8, 8),
373 RK3399_CPUCLKB_RATE(1608000000, 1, 7, 7),
374 RK3399_CPUCLKB_RATE(1512000000, 1, 7, 7),
375 RK3399_CPUCLKB_RATE(1488000000, 1, 6, 6),
376 RK3399_CPUCLKB_RATE(1416000000, 1, 6, 6),
377 RK3399_CPUCLKB_RATE(1200000000, 1, 5, 5),
378 RK3399_CPUCLKB_RATE(1008000000, 1, 5, 5),
379 RK3399_CPUCLKB_RATE( 816000000, 1, 4, 4),
380 RK3399_CPUCLKB_RATE( 696000000, 1, 3, 3),
381 RK3399_CPUCLKB_RATE( 600000000, 1, 3, 3),
382 RK3399_CPUCLKB_RATE( 408000000, 1, 2, 2),
383 RK3399_CPUCLKB_RATE( 312000000, 1, 1, 1),
384};
385
386static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
387 /*
388 * CRU Clock-Architecture
389 */
390
391 /* usbphy */
392 GATE(SCLK_USB2PHY0_REF, "clk_usb2phy0_ref", "xin24m", CLK_IGNORE_UNUSED,
393 RK3399_CLKGATE_CON(6), 5, GFLAGS),
394 GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", CLK_IGNORE_UNUSED,
395 RK3399_CLKGATE_CON(6), 6, GFLAGS),
396
397 GATE(0, "clk_usbphy0_480m_src", "clk_usbphy0_480m", CLK_IGNORE_UNUSED,
398 RK3399_CLKGATE_CON(13), 12, GFLAGS),
399 GATE(0, "clk_usbphy1_480m_src", "clk_usbphy1_480m", CLK_IGNORE_UNUSED,
400 RK3399_CLKGATE_CON(13), 12, GFLAGS),
401 MUX(0, "clk_usbphy_480m", mux_usbphy_480m_p, CLK_IGNORE_UNUSED,
402 RK3399_CLKSEL_CON(14), 6, 1, MFLAGS),
403
404 MUX(0, "upll", mux_pll_src_24m_usbphy480m_p, 0,
405 RK3399_CLKSEL_CON(14), 15, 1, MFLAGS),
406
407 COMPOSITE_NODIV(SCLK_HSICPHY, "clk_hsicphy", mux_pll_src_cpll_gpll_npll_usbphy480m_p, CLK_IGNORE_UNUSED,
408 RK3399_CLKSEL_CON(19), 0, 2, MFLAGS,
409 RK3399_CLKGATE_CON(6), 4, GFLAGS),
410
411 COMPOSITE(ACLK_USB3, "aclk_usb3", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
412 RK3399_CLKSEL_CON(39), 6, 2, MFLAGS, 0, 5, DFLAGS,
413 RK3399_CLKGATE_CON(12), 0, GFLAGS),
414 GATE(ACLK_USB3_NOC, "aclk_usb3_noc", "aclk_usb3", CLK_IGNORE_UNUSED,
415 RK3399_CLKGATE_CON(30), 0, GFLAGS),
416 GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb3", CLK_IGNORE_UNUSED,
417 RK3399_CLKGATE_CON(30), 1, GFLAGS),
418 GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb3", CLK_IGNORE_UNUSED,
419 RK3399_CLKGATE_CON(30), 2, GFLAGS),
420 GATE(ACLK_USB3_RKSOC_AXI_PERF, "aclk_usb3_rksoc_axi_perf", "aclk_usb3", CLK_IGNORE_UNUSED,
421 RK3399_CLKGATE_CON(30), 3, GFLAGS),
422 GATE(ACLK_USB3_GRF, "aclk_usb3_grf", "aclk_usb3", CLK_IGNORE_UNUSED,
423 RK3399_CLKGATE_CON(30), 4, GFLAGS),
424
425 GATE(SCLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", CLK_IGNORE_UNUSED,
426 RK3399_CLKGATE_CON(12), 1, GFLAGS),
427 GATE(SCLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", CLK_IGNORE_UNUSED,
428 RK3399_CLKGATE_CON(12), 2, GFLAGS),
429
430 COMPOSITE(SCLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", mux_pll_p, CLK_IGNORE_UNUSED,
431 RK3399_CLKSEL_CON(40), 15, 1, MFLAGS, 0, 10, DFLAGS,
432 RK3399_CLKGATE_CON(12), 3, GFLAGS),
433
434 COMPOSITE(SCLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", mux_pll_p, CLK_IGNORE_UNUSED,
435 RK3399_CLKSEL_CON(41), 15, 1, MFLAGS, 0, 10, DFLAGS,
436 RK3399_CLKGATE_CON(12), 4, GFLAGS),
437
438 COMPOSITE(SCLK_UPHY0_TCPDPHY_REF, "clk_uphy0_tcpdphy_ref", mux_pll_p, CLK_IGNORE_UNUSED,
439 RK3399_CLKSEL_CON(64), 15, 1, MFLAGS, 8, 5, DFLAGS,
440 RK3399_CLKGATE_CON(13), 4, GFLAGS),
441
442 COMPOSITE(SCLK_UPHY0_TCPDCORE, "clk_uphy0_tcpdcore", mux_pll_src_24m_32k_cpll_gpll_p, CLK_IGNORE_UNUSED,
443 RK3399_CLKSEL_CON(64), 6, 2, MFLAGS, 0, 5, DFLAGS,
444 RK3399_CLKGATE_CON(13), 5, GFLAGS),
445
446 COMPOSITE(SCLK_UPHY1_TCPDPHY_REF, "clk_uphy1_tcpdphy_ref", mux_pll_p, CLK_IGNORE_UNUSED,
447 RK3399_CLKSEL_CON(65), 15, 1, MFLAGS, 8, 5, DFLAGS,
448 RK3399_CLKGATE_CON(13), 6, GFLAGS),
449
450 COMPOSITE(SCLK_UPHY1_TCPDCORE, "clk_uphy1_tcpdcore", mux_pll_src_24m_32k_cpll_gpll_p, CLK_IGNORE_UNUSED,
451 RK3399_CLKSEL_CON(65), 6, 2, MFLAGS, 0, 5, DFLAGS,
452 RK3399_CLKGATE_CON(13), 7, GFLAGS),
453
454 /* little core */
455 GATE(0, "clk_core_l_lpll_src", "lpll", CLK_IGNORE_UNUSED,
456 RK3399_CLKGATE_CON(0), 0, GFLAGS),
457 GATE(0, "clk_core_l_bpll_src", "bpll", CLK_IGNORE_UNUSED,
458 RK3399_CLKGATE_CON(0), 1, GFLAGS),
459 GATE(0, "clk_core_l_dpll_src", "dpll", CLK_IGNORE_UNUSED,
460 RK3399_CLKGATE_CON(0), 2, GFLAGS),
461 GATE(0, "clk_core_l_gpll_src", "gpll", CLK_IGNORE_UNUSED,
462 RK3399_CLKGATE_CON(0), 3, GFLAGS),
463
464 COMPOSITE_NOMUX(0, "aclkm_core_l", "armclkl", CLK_IGNORE_UNUSED,
465 RK3399_CLKSEL_CON(0), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
466 RK3399_CLKGATE_CON(0), 4, GFLAGS),
467 COMPOSITE_NOMUX(0, "atclk_core_l", "armclkl", CLK_IGNORE_UNUSED,
468 RK3399_CLKSEL_CON(1), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
469 RK3399_CLKGATE_CON(0), 5, GFLAGS),
470 COMPOSITE_NOMUX(0, "pclk_dbg_core_l", "armclkl", CLK_IGNORE_UNUSED,
471 RK3399_CLKSEL_CON(1), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
472 RK3399_CLKGATE_CON(0), 6, GFLAGS),
473
474 GATE(ACLK_CORE_ADB400_CORE_L_2_CCI500, "aclk_core_adb400_core_l_2_cci500", "aclkm_core_l", CLK_IGNORE_UNUSED,
475 RK3399_CLKGATE_CON(14), 12, GFLAGS),
476 GATE(ACLK_PERF_CORE_L, "aclk_perf_core_l", "aclkm_core_l", CLK_IGNORE_UNUSED,
477 RK3399_CLKGATE_CON(14), 13, GFLAGS),
478
479 GATE(0, "clk_dbg_pd_core_l", "armclkl", CLK_IGNORE_UNUSED,
480 RK3399_CLKGATE_CON(14), 9, GFLAGS),
481 GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_core_adb400_gic_2_core_l", "armclkl", CLK_IGNORE_UNUSED,
482 RK3399_CLKGATE_CON(14), 10, GFLAGS),
483 GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_core_adb400_core_l_2_gic", "armclkl", CLK_IGNORE_UNUSED,
484 RK3399_CLKGATE_CON(14), 11, GFLAGS),
485 GATE(SCLK_PVTM_CORE_L, "clk_pvtm_core_l", "xin24m", CLK_IGNORE_UNUSED,
486 RK3399_CLKGATE_CON(0), 7, GFLAGS),
487
488 /* big core */
489 GATE(0, "clk_core_b_lpll_src", "lpll", CLK_IGNORE_UNUSED,
490 RK3399_CLKGATE_CON(1), 0, GFLAGS),
491 GATE(0, "clk_core_b_bpll_src", "bpll", CLK_IGNORE_UNUSED,
492 RK3399_CLKGATE_CON(1), 1, GFLAGS),
493 GATE(0, "clk_core_b_dpll_src", "dpll", CLK_IGNORE_UNUSED,
494 RK3399_CLKGATE_CON(1), 2, GFLAGS),
495 GATE(0, "clk_core_b_gpll_src", "gpll", CLK_IGNORE_UNUSED,
496 RK3399_CLKGATE_CON(1), 3, GFLAGS),
497
498 COMPOSITE_NOMUX(0, "aclkm_core_b", "armclkb", CLK_IGNORE_UNUSED,
499 RK3399_CLKSEL_CON(2), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
500 RK3399_CLKGATE_CON(1), 4, GFLAGS),
501 COMPOSITE_NOMUX(0, "atclk_core_b", "armclkb", CLK_IGNORE_UNUSED,
502 RK3399_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
503 RK3399_CLKGATE_CON(1), 5, GFLAGS),
504 COMPOSITE_NOMUX(0, "pclk_dbg_core_b", "armclkb", CLK_IGNORE_UNUSED,
505 RK3399_CLKSEL_CON(3), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
506 RK3399_CLKGATE_CON(1), 6, GFLAGS),
507
508 GATE(ACLK_CORE_ADB400_CORE_B_2_CCI500, "aclk_core_adb400_core_b_2_cci500", "aclkm_core_b", CLK_IGNORE_UNUSED,
509 RK3399_CLKGATE_CON(14), 5, GFLAGS),
510 GATE(ACLK_PERF_CORE_B, "aclk_perf_core_b", "aclkm_core_b", CLK_IGNORE_UNUSED,
511 RK3399_CLKGATE_CON(14), 6, GFLAGS),
512
513 GATE(0, "clk_dbg_pd_core_b", "armclkb", CLK_IGNORE_UNUSED,
514 RK3399_CLKGATE_CON(14), 1, GFLAGS),
515 GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_core_adb400_gic_2_core_b", "armclkb", CLK_IGNORE_UNUSED,
516 RK3399_CLKGATE_CON(14), 3, GFLAGS),
517 GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_core_adb400_core_b_2_gic", "armclkb", CLK_IGNORE_UNUSED,
518 RK3399_CLKGATE_CON(14), 4, GFLAGS),
519
520 DIV(0, "pclken_dbg_core_b", "pclk_dbg_core_b", CLK_IGNORE_UNUSED,
521 RK3399_CLKSEL_CON(3), 13, 2, DFLAGS | CLK_DIVIDER_READ_ONLY),
522
523 GATE(0, "pclk_dbg_cxcs_pd_core_b", "pclk_dbg_core_b", CLK_IGNORE_UNUSED,
524 RK3399_CLKGATE_CON(14), 2, GFLAGS),
525
526 GATE(SCLK_PVTM_CORE_B, "clk_pvtm_core_b", "xin24m", CLK_IGNORE_UNUSED,
527 RK3399_CLKGATE_CON(1), 7, GFLAGS),
528
529 /* gmac */
530 GATE(0, "cpll_aclk_gmac_src", "cpll", CLK_IGNORE_UNUSED,
531 RK3399_CLKGATE_CON(6), 9, GFLAGS),
532 GATE(0, "gpll_aclk_gmac_src", "gpll", CLK_IGNORE_UNUSED,
533 RK3399_CLKGATE_CON(6), 8, GFLAGS),
534 COMPOSITE(0, "aclk_gmac_pre", mux_aclk_gmac_p, CLK_IGNORE_UNUSED,
535 RK3399_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 5, DFLAGS,
536 RK3399_CLKGATE_CON(6), 10, GFLAGS),
537
538 GATE(ACLK_GMAC, "aclk_gmac", "aclk_gmac_pre", CLK_IGNORE_UNUSED,
539 RK3399_CLKGATE_CON(32), 0, GFLAGS),
540 GATE(ACLK_GMAC_NOC, "aclk_gmac_noc", "aclk_gmac_pre", CLK_IGNORE_UNUSED,
541 RK3399_CLKGATE_CON(32), 1, GFLAGS),
542 GATE(ACLK_PERF_GMAC, "aclk_perf_gmac", "aclk_gmac_pre", CLK_IGNORE_UNUSED,
543 RK3399_CLKGATE_CON(32), 4, GFLAGS),
544
545 COMPOSITE_NOMUX(0, "pclk_gmac_pre", "aclk_gmac_pre", 0,
546 RK3399_CLKSEL_CON(19), 8, 3, DFLAGS,
547 RK3399_CLKGATE_CON(6), 11, GFLAGS),
548 GATE(PCLK_GMAC, "pclk_gmac", "pclk_gmac_pre", CLK_IGNORE_UNUSED,
549 RK3399_CLKGATE_CON(32), 2, GFLAGS),
550 GATE(PCLK_GMAC_NOC, "pclk_gmac_noc", "pclk_gmac_pre", CLK_IGNORE_UNUSED,
551 RK3399_CLKGATE_CON(32), 3, GFLAGS),
552
553 COMPOSITE(SCLK_MAC, "clk_gmac", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
554 RK3399_CLKSEL_CON(20), 14, 2, MFLAGS, 8, 5, DFLAGS,
555 RK3399_CLKGATE_CON(5), 5, GFLAGS),
556
557 MUX(0, "clk_rmii_src", mux_rmii_p, CLK_SET_RATE_PARENT,
558 RK3399_CLKSEL_CON(19), 4, 1, MFLAGS),
559 GATE(SCLK_MACREF_OUT, "clk_mac_refout", "clk_rmii_src", CLK_IGNORE_UNUSED,
560 RK3399_CLKGATE_CON(5), 6, GFLAGS),
561 GATE(SCLK_MACREF, "clk_mac_ref", "clk_rmii_src", CLK_IGNORE_UNUSED,
562 RK3399_CLKGATE_CON(5), 7, GFLAGS),
563 GATE(SCLK_MAC_RX, "clk_rmii_rx", "clk_rmii_src", CLK_IGNORE_UNUSED,
564 RK3399_CLKGATE_CON(5), 8, GFLAGS),
565 GATE(SCLK_MAC_TX, "clk_rmii_tx", "clk_rmii_src", CLK_IGNORE_UNUSED,
566 RK3399_CLKGATE_CON(5), 9, GFLAGS),
567
568 /* spdif */
569 COMPOSITE(0, "clk_spdif_div", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
570 RK3399_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 7, DFLAGS,
571 RK3399_CLKGATE_CON(8), 13, GFLAGS),
572 COMPOSITE_FRACMUX(0, "clk_spdif_frac", "clk_spdif_div", CLK_SET_RATE_PARENT,
573 RK3399_CLKSEL_CON(99), 0,
574 RK3399_CLKGATE_CON(8), 14, GFLAGS,
575 &rk3399_spdif_fracmux),
576 GATE(SCLK_SPDIF_8CH, "clk_spdif", "clk_spdif_mux", CLK_SET_RATE_PARENT,
577 RK3399_CLKGATE_CON(8), 15, GFLAGS),
578
579 COMPOSITE(SCLK_SPDIF_REC_DPTX, "clk_spdif_rec_dptx", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
580 RK3399_CLKSEL_CON(32), 15, 1, MFLAGS, 0, 5, DFLAGS,
581 RK3399_CLKGATE_CON(10), 6, GFLAGS),
582 /* i2s */
583 COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
584 RK3399_CLKSEL_CON(28), 7, 1, MFLAGS, 0, 7, DFLAGS,
585 RK3399_CLKGATE_CON(8), 3, GFLAGS),
586 COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", CLK_SET_RATE_PARENT,
587 RK3399_CLKSEL_CON(96), 0,
588 RK3399_CLKGATE_CON(8), 4, GFLAGS,
589 &rk3399_i2s0_fracmux),
590 GATE(SCLK_I2S0_8CH, "clk_i2s0", "clk_i2s0_mux", CLK_SET_RATE_PARENT,
591 RK3399_CLKGATE_CON(8), 5, GFLAGS),
592
593 COMPOSITE(0, "clk_i2s1_div", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
594 RK3399_CLKSEL_CON(29), 7, 1, MFLAGS, 0, 7, DFLAGS,
595 RK3399_CLKGATE_CON(8), 6, GFLAGS),
596 COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", CLK_SET_RATE_PARENT,
597 RK3399_CLKSEL_CON(97), 0,
598 RK3399_CLKGATE_CON(8), 7, GFLAGS,
599 &rk3399_i2s1_fracmux),
600 GATE(SCLK_I2S1_8CH, "clk_i2s1", "clk_i2s1_mux", CLK_SET_RATE_PARENT,
601 RK3399_CLKGATE_CON(8), 8, GFLAGS),
602
603 COMPOSITE(0, "clk_i2s2_div", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
604 RK3399_CLKSEL_CON(30), 7, 1, MFLAGS, 0, 7, DFLAGS,
605 RK3399_CLKGATE_CON(8), 9, GFLAGS),
606 COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", CLK_SET_RATE_PARENT,
607 RK3399_CLKSEL_CON(98), 0,
608 RK3399_CLKGATE_CON(8), 10, GFLAGS,
609 &rk3399_i2s2_fracmux),
610 GATE(SCLK_I2S2_8CH, "clk_i2s2", "clk_i2s2_mux", CLK_SET_RATE_PARENT,
611 RK3399_CLKGATE_CON(8), 11, GFLAGS),
612
613 MUX(0, "clk_i2sout_src", mux_i2sch_p, CLK_SET_RATE_PARENT,
614 RK3399_CLKSEL_CON(31), 0, 2, MFLAGS),
615 COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "clk_i2sout", mux_i2sout_p, CLK_SET_RATE_PARENT,
616 RK3399_CLKSEL_CON(30), 8, 2, MFLAGS,
617 RK3399_CLKGATE_CON(8), 12, GFLAGS),
618
619 /* uart */
620 MUX(0, "clk_uart0_src", mux_pll_src_cpll_gpll_upll_p, 0,
621 RK3399_CLKSEL_CON(33), 12, 2, MFLAGS),
622 COMPOSITE_NOMUX(0, "clk_uart0_div", "clk_uart0_src", 0,
623 RK3399_CLKSEL_CON(33), 0, 7, DFLAGS,
624 RK3399_CLKGATE_CON(9), 0, GFLAGS),
625 COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_div", CLK_SET_RATE_PARENT,
626 RK3399_CLKSEL_CON(100), 0,
627 RK3399_CLKGATE_CON(9), 1, GFLAGS,
628 &rk3399_uart0_fracmux),
629
630 MUX(0, "clk_uart_src", mux_pll_src_cpll_gpll_p, 0,
631 RK3399_CLKSEL_CON(33), 15, 1, MFLAGS),
632 COMPOSITE_NOMUX(0, "clk_uart1_div", "clk_uart_src", 0,
633 RK3399_CLKSEL_CON(34), 0, 7, DFLAGS,
634 RK3399_CLKGATE_CON(9), 2, GFLAGS),
635 COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_div", CLK_SET_RATE_PARENT,
636 RK3399_CLKSEL_CON(101), 0,
637 RK3399_CLKGATE_CON(9), 3, GFLAGS,
638 &rk3399_uart1_fracmux),
639
640 COMPOSITE_NOMUX(0, "clk_uart2_div", "clk_uart_src", 0,
641 RK3399_CLKSEL_CON(35), 0, 7, DFLAGS,
642 RK3399_CLKGATE_CON(9), 4, GFLAGS),
643 COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_div", CLK_SET_RATE_PARENT,
644 RK3399_CLKSEL_CON(102), 0,
645 RK3399_CLKGATE_CON(9), 5, GFLAGS,
646 &rk3399_uart2_fracmux),
647
648 COMPOSITE_NOMUX(0, "clk_uart3_div", "clk_uart_src", 0,
649 RK3399_CLKSEL_CON(36), 0, 7, DFLAGS,
650 RK3399_CLKGATE_CON(9), 6, GFLAGS),
651 COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_div", CLK_SET_RATE_PARENT,
652 RK3399_CLKSEL_CON(103), 0,
653 RK3399_CLKGATE_CON(9), 7, GFLAGS,
654 &rk3399_uart3_fracmux),
655
656 COMPOSITE(0, "pclk_ddr", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
657 RK3399_CLKSEL_CON(6), 15, 1, MFLAGS, 8, 5, DFLAGS,
658 RK3399_CLKGATE_CON(3), 4, GFLAGS),
659
660 GATE(PCLK_CENTER_MAIN_NOC, "pclk_center_main_noc", "pclk_ddr", CLK_IGNORE_UNUSED,
661 RK3399_CLKGATE_CON(18), 10, GFLAGS),
662 GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_ddr", CLK_IGNORE_UNUSED,
663 RK3399_CLKGATE_CON(18), 12, GFLAGS),
664 GATE(PCLK_CIC, "pclk_cic", "pclk_ddr", CLK_IGNORE_UNUSED,
665 RK3399_CLKGATE_CON(18), 15, GFLAGS),
666 GATE(PCLK_DDR_SGRF, "pclk_ddr_sgrf", "pclk_ddr", CLK_IGNORE_UNUSED,
667 RK3399_CLKGATE_CON(19), 2, GFLAGS),
668
669 GATE(SCLK_PVTM_DDR, "clk_pvtm_ddr", "xin24m", CLK_IGNORE_UNUSED,
670 RK3399_CLKGATE_CON(4), 11, GFLAGS),
671 GATE(SCLK_DFIMON0_TIMER, "clk_dfimon0_timer", "xin24m", CLK_IGNORE_UNUSED,
672 RK3399_CLKGATE_CON(3), 5, GFLAGS),
673 GATE(SCLK_DFIMON1_TIMER, "clk_dfimon1_timer", "xin24m", CLK_IGNORE_UNUSED,
674 RK3399_CLKGATE_CON(3), 6, GFLAGS),
675
676 /* cci */
677 GATE(0, "cpll_aclk_cci_src", "cpll", CLK_IGNORE_UNUSED,
678 RK3399_CLKGATE_CON(2), 0, GFLAGS),
679 GATE(0, "gpll_aclk_cci_src", "gpll", CLK_IGNORE_UNUSED,
680 RK3399_CLKGATE_CON(2), 1, GFLAGS),
681 GATE(0, "npll_aclk_cci_src", "npll", CLK_IGNORE_UNUSED,
682 RK3399_CLKGATE_CON(2), 2, GFLAGS),
683 GATE(0, "vpll_aclk_cci_src", "vpll", CLK_IGNORE_UNUSED,
684 RK3399_CLKGATE_CON(2), 3, GFLAGS),
685
686 COMPOSITE(0, "aclk_cci_pre", mux_aclk_cci_p, CLK_IGNORE_UNUSED,
687 RK3399_CLKSEL_CON(5), 6, 2, MFLAGS, 0, 5, DFLAGS,
688 RK3399_CLKGATE_CON(2), 4, GFLAGS),
689
690 GATE(ACLK_ADB400M_PD_CORE_L, "aclk_adb400m_pd_core_l", "aclk_cci_pre", CLK_IGNORE_UNUSED,
691 RK3399_CLKGATE_CON(15), 0, GFLAGS),
692 GATE(ACLK_ADB400M_PD_CORE_B, "aclk_adb400m_pd_core_b", "aclk_cci_pre", CLK_IGNORE_UNUSED,
693 RK3399_CLKGATE_CON(15), 1, GFLAGS),
694 GATE(ACLK_CCI, "aclk_cci", "aclk_cci_pre", CLK_IGNORE_UNUSED,
695 RK3399_CLKGATE_CON(15), 2, GFLAGS),
696 GATE(ACLK_CCI_NOC0, "aclk_cci_noc0", "aclk_cci_pre", CLK_IGNORE_UNUSED,
697 RK3399_CLKGATE_CON(15), 3, GFLAGS),
698 GATE(ACLK_CCI_NOC1, "aclk_cci_noc1", "aclk_cci_pre", CLK_IGNORE_UNUSED,
699 RK3399_CLKGATE_CON(15), 4, GFLAGS),
700 GATE(ACLK_CCI_GRF, "aclk_cci_grf", "aclk_cci_pre", CLK_IGNORE_UNUSED,
701 RK3399_CLKGATE_CON(15), 7, GFLAGS),
702
703 GATE(0, "cpll_cci_trace", "cpll", CLK_IGNORE_UNUSED,
704 RK3399_CLKGATE_CON(2), 5, GFLAGS),
705 GATE(0, "gpll_cci_trace", "gpll", CLK_IGNORE_UNUSED,
706 RK3399_CLKGATE_CON(2), 6, GFLAGS),
707 COMPOSITE(SCLK_CCI_TRACE, "clk_cci_trace", mux_cci_trace_p, CLK_IGNORE_UNUSED,
708 RK3399_CLKSEL_CON(5), 15, 2, MFLAGS, 8, 5, DFLAGS,
709 RK3399_CLKGATE_CON(2), 7, GFLAGS),
710
711 GATE(0, "cpll_cs", "cpll", CLK_IGNORE_UNUSED,
712 RK3399_CLKGATE_CON(2), 8, GFLAGS),
713 GATE(0, "gpll_cs", "gpll", CLK_IGNORE_UNUSED,
714 RK3399_CLKGATE_CON(2), 9, GFLAGS),
715 GATE(0, "npll_cs", "npll", CLK_IGNORE_UNUSED,
716 RK3399_CLKGATE_CON(2), 10, GFLAGS),
717 COMPOSITE_NOGATE(0, "clk_cs", mux_cs_p, CLK_IGNORE_UNUSED,
718 RK3399_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 5, DFLAGS),
719 GATE(0, "clk_dbg_cxcs", "clk_cs", CLK_IGNORE_UNUSED,
720 RK3399_CLKGATE_CON(15), 5, GFLAGS),
721 GATE(0, "clk_dbg_noc", "clk_cs", CLK_IGNORE_UNUSED,
722 RK3399_CLKGATE_CON(15), 6, GFLAGS),
723
724 /* vcodec */
725 COMPOSITE(0, "aclk_vcodec_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
726 RK3399_CLKSEL_CON(7), 6, 2, MFLAGS, 0, 5, DFLAGS,
727 RK3399_CLKGATE_CON(4), 0, GFLAGS),
728 COMPOSITE_NOMUX(0, "hclk_vcodec_pre", "aclk_vcodec_pre", 0,
729 RK3399_CLKSEL_CON(7), 8, 5, DFLAGS,
730 RK3399_CLKGATE_CON(4), 1, GFLAGS),
731 GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", CLK_IGNORE_UNUSED,
732 RK3399_CLKGATE_CON(17), 2, GFLAGS),
733 GATE(0, "hclk_vcodec_noc", "hclk_vcodec_pre", CLK_IGNORE_UNUSED,
734 RK3399_CLKGATE_CON(17), 3, GFLAGS),
735
736 GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre", CLK_IGNORE_UNUSED,
737 RK3399_CLKGATE_CON(17), 0, GFLAGS),
738 GATE(0, "aclk_vcodec_noc", "aclk_vcodec_pre", CLK_IGNORE_UNUSED,
739 RK3399_CLKGATE_CON(17), 1, GFLAGS),
740
741 /* vdu */
742 COMPOSITE(SCLK_VDU_CORE, "clk_vdu_core", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
743 RK3399_CLKSEL_CON(9), 6, 2, MFLAGS, 0, 5, DFLAGS,
744 RK3399_CLKGATE_CON(4), 4, GFLAGS),
745 COMPOSITE(SCLK_VDU_CA, "clk_vdu_ca", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
746 RK3399_CLKSEL_CON(9), 14, 2, MFLAGS, 8, 5, DFLAGS,
747 RK3399_CLKGATE_CON(4), 5, GFLAGS),
748
749 COMPOSITE(0, "aclk_vdu_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
750 RK3399_CLKSEL_CON(8), 6, 2, MFLAGS, 0, 5, DFLAGS,
751 RK3399_CLKGATE_CON(4), 2, GFLAGS),
752 COMPOSITE_NOMUX(0, "hclk_vdu_pre", "aclk_vdu_pre", 0,
753 RK3399_CLKSEL_CON(8), 8, 5, DFLAGS,
754 RK3399_CLKGATE_CON(4), 3, GFLAGS),
755 GATE(HCLK_VDU, "hclk_vdu", "hclk_vdu_pre", CLK_IGNORE_UNUSED,
756 RK3399_CLKGATE_CON(17), 10, GFLAGS),
757 GATE(HCLK_VDU_NOC, "hclk_vdu_noc", "hclk_vdu_pre", CLK_IGNORE_UNUSED,
758 RK3399_CLKGATE_CON(17), 11, GFLAGS),
759
760 GATE(ACLK_VDU, "aclk_vdu", "aclk_vdu_pre", CLK_IGNORE_UNUSED,
761 RK3399_CLKGATE_CON(17), 8, GFLAGS),
762 GATE(ACLK_VDU_NOC, "aclk_vdu_noc", "aclk_vdu_pre", CLK_IGNORE_UNUSED,
763 RK3399_CLKGATE_CON(17), 9, GFLAGS),
764
765 /* iep */
766 COMPOSITE(0, "aclk_iep_pre", mux_pll_src_cpll_gpll_npll_ppll_p, CLK_IGNORE_UNUSED,
767 RK3399_CLKSEL_CON(10), 6, 2, MFLAGS, 0, 5, DFLAGS,
768 RK3399_CLKGATE_CON(4), 6, GFLAGS),
769 COMPOSITE_NOMUX(0, "hclk_iep_pre", "aclk_iep_pre", 0,
770 RK3399_CLKSEL_CON(10), 8, 5, DFLAGS,
771 RK3399_CLKGATE_CON(4), 7, GFLAGS),
772 GATE(HCLK_IEP, "hclk_iep", "hclk_iep_pre", CLK_IGNORE_UNUSED,
773 RK3399_CLKGATE_CON(16), 2, GFLAGS),
774 GATE(HCLK_IEP_NOC, "hclk_iep_noc", "hclk_iep_pre", CLK_IGNORE_UNUSED,
775 RK3399_CLKGATE_CON(16), 3, GFLAGS),
776
777 GATE(ACLK_IEP, "aclk_iep", "aclk_iep_pre", CLK_IGNORE_UNUSED,
778 RK3399_CLKGATE_CON(16), 0, GFLAGS),
779 GATE(ACLK_IEP_NOC, "aclk_iep_noc", "aclk_iep_pre", CLK_IGNORE_UNUSED,
780 RK3399_CLKGATE_CON(16), 1, GFLAGS),
781
782 /* rga */
783 COMPOSITE(0, "clk_rga_core", mux_pll_src_cpll_gpll_npll_ppll_p, CLK_IGNORE_UNUSED,
784 RK3399_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 5, DFLAGS,
785 RK3399_CLKGATE_CON(4), 10, GFLAGS),
786
787 COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_npll_ppll_p, CLK_IGNORE_UNUSED,
788 RK3399_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 5, DFLAGS,
789 RK3399_CLKGATE_CON(4), 8, GFLAGS),
790 COMPOSITE_NOMUX(0, "hclk_rga_pre", "aclk_rga_pre", 0,
791 RK3399_CLKSEL_CON(11), 8, 5, DFLAGS,
792 RK3399_CLKGATE_CON(4), 9, GFLAGS),
793 GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", CLK_IGNORE_UNUSED,
794 RK3399_CLKGATE_CON(16), 10, GFLAGS),
795 GATE(HCLK_RGA_NOC, "hclk_rga_noc", "hclk_rga_pre", CLK_IGNORE_UNUSED,
796 RK3399_CLKGATE_CON(16), 11, GFLAGS),
797
798 GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", CLK_IGNORE_UNUSED,
799 RK3399_CLKGATE_CON(16), 8, GFLAGS),
800 GATE(ACLK_RGA_NOC, "aclk_rga_noc", "aclk_rga_pre", CLK_IGNORE_UNUSED,
801 RK3399_CLKGATE_CON(16), 9, GFLAGS),
802
803 /* center */
804 COMPOSITE(0, "aclk_center", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
805 RK3399_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 5, DFLAGS,
806 RK3399_CLKGATE_CON(3), 7, GFLAGS),
807 GATE(ACLK_CENTER_MAIN_NOC, "aclk_center_main_noc", "aclk_center", CLK_IGNORE_UNUSED,
808 RK3399_CLKGATE_CON(19), 0, GFLAGS),
809 GATE(ACLK_CENTER_PERI_NOC, "aclk_center_peri_noc", "aclk_center", CLK_IGNORE_UNUSED,
810 RK3399_CLKGATE_CON(19), 1, GFLAGS),
811
812 /* gpu */
813 COMPOSITE(0, "aclk_gpu_pre", mux_pll_src_ppll_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
814 RK3399_CLKSEL_CON(13), 5, 3, MFLAGS, 0, 5, DFLAGS,
815 RK3399_CLKGATE_CON(13), 0, GFLAGS),
816 GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", CLK_IGNORE_UNUSED,
817 RK3399_CLKGATE_CON(30), 8, GFLAGS),
818 GATE(ACLK_PERF_GPU, "aclk_perf_gpu", "aclk_gpu_pre", CLK_IGNORE_UNUSED,
819 RK3399_CLKGATE_CON(30), 10, GFLAGS),
820 GATE(ACLK_GPU_GRF, "aclk_gpu_grf", "aclk_gpu_pre", CLK_IGNORE_UNUSED,
821 RK3399_CLKGATE_CON(30), 11, GFLAGS),
822 GATE(SCLK_PVTM_GPU, "aclk_pvtm_gpu", "xin24m", CLK_IGNORE_UNUSED,
823 RK3399_CLKGATE_CON(13), 1, GFLAGS),
824
825 /* perihp */
826 GATE(0, "cpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
827 RK3399_CLKGATE_CON(5), 0, GFLAGS),
828 GATE(0, "gpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
829 RK3399_CLKGATE_CON(5), 1, GFLAGS),
830 COMPOSITE(ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_p, CLK_IGNORE_UNUSED,
831 RK3399_CLKSEL_CON(14), 7, 1, MFLAGS, 0, 5, DFLAGS,
832 RK3399_CLKGATE_CON(5), 2, GFLAGS),
833 COMPOSITE_NOMUX(HCLK_PERIHP, "hclk_perihp", "aclk_perihp", CLK_IGNORE_UNUSED,
834 RK3399_CLKSEL_CON(14), 8, 2, DFLAGS,
835 RK3399_CLKGATE_CON(5), 3, GFLAGS),
836 COMPOSITE_NOMUX(PCLK_PERIHP, "pclk_perihp", "aclk_perihp", CLK_IGNORE_UNUSED,
837 RK3399_CLKSEL_CON(14), 12, 2, DFLAGS,
838 RK3399_CLKGATE_CON(5), 4, GFLAGS),
839
840 GATE(ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp", CLK_IGNORE_UNUSED,
841 RK3399_CLKGATE_CON(20), 2, GFLAGS),
842 GATE(ACLK_PCIE, "aclk_pcie", "aclk_perihp", CLK_IGNORE_UNUSED,
843 RK3399_CLKGATE_CON(20), 10, GFLAGS),
844 GATE(0, "aclk_perihp_noc", "aclk_perihp", CLK_IGNORE_UNUSED,
845 RK3399_CLKGATE_CON(20), 12, GFLAGS),
846
847 GATE(HCLK_HOST0, "hclk_host0", "hclk_perihp", CLK_IGNORE_UNUSED,
848 RK3399_CLKGATE_CON(20), 5, GFLAGS),
849 GATE(HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_perihp", CLK_IGNORE_UNUSED,
850 RK3399_CLKGATE_CON(20), 6, GFLAGS),
851 GATE(HCLK_HOST1, "hclk_host1", "hclk_perihp", CLK_IGNORE_UNUSED,
852 RK3399_CLKGATE_CON(20), 7, GFLAGS),
853 GATE(HCLK_HOST1_ARB, "hclk_host1_arb", "hclk_perihp", CLK_IGNORE_UNUSED,
854 RK3399_CLKGATE_CON(20), 8, GFLAGS),
855 GATE(HCLK_HSIC, "hclk_hsic", "hclk_perihp", CLK_IGNORE_UNUSED,
856 RK3399_CLKGATE_CON(20), 9, GFLAGS),
857 GATE(0, "hclk_perihp_noc", "hclk_perihp", CLK_IGNORE_UNUSED,
858 RK3399_CLKGATE_CON(20), 13, GFLAGS),
859 GATE(0, "hclk_ahb1tom", "hclk_perihp", CLK_IGNORE_UNUSED,
860 RK3399_CLKGATE_CON(20), 15, GFLAGS),
861
862 GATE(PCLK_PERIHP_GRF, "pclk_perihp_grf", "pclk_perihp", CLK_IGNORE_UNUSED,
863 RK3399_CLKGATE_CON(20), 4, GFLAGS),
864 GATE(PCLK_PCIE, "pclk_pcie", "pclk_perihp", CLK_IGNORE_UNUSED,
865 RK3399_CLKGATE_CON(20), 11, GFLAGS),
866 GATE(0, "pclk_perihp_noc", "pclk_perihp", CLK_IGNORE_UNUSED,
867 RK3399_CLKGATE_CON(20), 14, GFLAGS),
868 GATE(PCLK_HSICPHY, "pclk_hsicphy", "pclk_perihp", CLK_IGNORE_UNUSED,
869 RK3399_CLKGATE_CON(31), 8, GFLAGS),
870
871 /* sdio & sdmmc */
872 COMPOSITE(0, "hclk_sd", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
873 RK3399_CLKSEL_CON(13), 15, 1, MFLAGS, 8, 5, DFLAGS,
874 RK3399_CLKGATE_CON(12), 13, GFLAGS),
875 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", CLK_IGNORE_UNUSED,
876 RK3399_CLKGATE_CON(33), 8, GFLAGS),
877 GATE(0, "hclk_sdmmc_noc", "hclk_sd", CLK_IGNORE_UNUSED,
878 RK3399_CLKGATE_CON(33), 9, GFLAGS),
879
880 COMPOSITE(SCLK_SDIO, "clk_sdio", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p, CLK_IGNORE_UNUSED,
881 RK3399_CLKSEL_CON(15), 8, 3, MFLAGS, 0, 7, DFLAGS,
882 RK3399_CLKGATE_CON(6), 0, GFLAGS),
883
884 COMPOSITE(SCLK_SDMMC, "clk_sdmmc", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p, CLK_IGNORE_UNUSED,
885 RK3399_CLKSEL_CON(16), 8, 3, MFLAGS, 0, 7, DFLAGS,
886 RK3399_CLKGATE_CON(6), 1, GFLAGS),
887
888 MMC(SCLK_SDMMC_DRV, "emmc_drv", "clk_sdmmc", RK3399_SDMMC_CON0, 1),
889 MMC(SCLK_SDMMC_SAMPLE, "emmc_sample", "clk_sdmmc", RK3399_SDMMC_CON1, 1),
890
891 MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", RK3399_SDIO_CON0, 1),
892 MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", RK3399_SDIO_CON1, 1),
893
894 /* pcie */
895 COMPOSITE(SCLK_PCIE_PM, "clk_pcie_pm", mux_pll_src_cpll_gpll_npll_24m_p, CLK_IGNORE_UNUSED,
896 RK3399_CLKSEL_CON(17), 8, 3, MFLAGS, 0, 7, DFLAGS,
897 RK3399_CLKGATE_CON(6), 2, GFLAGS),
898
899 COMPOSITE_NOMUX(0, "clk_pciephy_ref100m", "npll", CLK_IGNORE_UNUSED,
900 RK3399_CLKSEL_CON(18), 11, 5, DFLAGS,
901 RK3399_CLKGATE_CON(12), 6, GFLAGS),
902 MUX(SCLK_PCIEPHY_REF, "clk_pciephy_ref", mux_pll_src_24m_pciephy_p, CLK_SET_RATE_PARENT,
903 RK3399_CLKSEL_CON(18), 10, 1, MFLAGS),
904
905 COMPOSITE(0, "clk_pcie_core_cru", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
906 RK3399_CLKSEL_CON(18), 8, 2, MFLAGS, 0, 7, DFLAGS,
907 RK3399_CLKGATE_CON(6), 3, GFLAGS),
908 MUX(SCLK_PCIE_CORE, "clk_pcie_core", mux_pciecore_cru_phy_p, CLK_SET_RATE_PARENT,
909 RK3399_CLKSEL_CON(18), 7, 1, MFLAGS),
910
911 /* emmc */
912 COMPOSITE(SCLK_EMMC, "clk_emmc", mux_pll_src_cpll_gpll_npll_upll_24m_p, CLK_IGNORE_UNUSED,
913 RK3399_CLKSEL_CON(22), 8, 3, MFLAGS, 0, 7, DFLAGS,
914 RK3399_CLKGATE_CON(6), 14, GFLAGS),
915
916 GATE(0, "cpll_aclk_emmc_src", "cpll", CLK_IGNORE_UNUSED,
917 RK3399_CLKGATE_CON(6), 12, GFLAGS),
918 GATE(0, "gpll_aclk_emmc_src", "gpll", CLK_IGNORE_UNUSED,
919 RK3399_CLKGATE_CON(6), 13, GFLAGS),
920 COMPOSITE_NOGATE(ACLK_EMMC, "aclk_emmc", mux_aclk_emmc_p, CLK_IGNORE_UNUSED,
921 RK3399_CLKSEL_CON(21), 7, 1, MFLAGS, 0, 5, DFLAGS),
922 GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", CLK_IGNORE_UNUSED,
923 RK3399_CLKGATE_CON(32), 8, GFLAGS),
924 GATE(ACLK_EMMC_NOC, "aclk_emmc_noc", "aclk_emmc", CLK_IGNORE_UNUSED,
925 RK3399_CLKGATE_CON(32), 9, GFLAGS),
926 GATE(ACLK_EMMC_GRF, "aclk_emmcgrf", "aclk_emmc", CLK_IGNORE_UNUSED,
927 RK3399_CLKGATE_CON(32), 10, GFLAGS),
928
929 /* perilp0 */
930 GATE(0, "cpll_aclk_perilp0_src", "cpll", CLK_IGNORE_UNUSED,
931 RK3399_CLKGATE_CON(7), 1, GFLAGS),
932 GATE(0, "gpll_aclk_perilp0_src", "gpll", CLK_IGNORE_UNUSED,
933 RK3399_CLKGATE_CON(7), 0, GFLAGS),
934 COMPOSITE(ACLK_PERILP0, "aclk_perilp0", mux_aclk_perilp0_p, CLK_IGNORE_UNUSED,
935 RK3399_CLKSEL_CON(23), 7, 1, MFLAGS, 0, 5, DFLAGS,
936 RK3399_CLKGATE_CON(7), 2, GFLAGS),
937 COMPOSITE_NOMUX(HCLK_PERILP0, "hclk_perilp0", "aclk_perilp0", CLK_IGNORE_UNUSED,
938 RK3399_CLKSEL_CON(23), 8, 2, DFLAGS,
939 RK3399_CLKGATE_CON(7), 3, GFLAGS),
940 COMPOSITE_NOMUX(PCLK_PERILP0, "pclk_perilp0", "aclk_perilp0", 0,
941 RK3399_CLKSEL_CON(23), 12, 3, DFLAGS,
942 RK3399_CLKGATE_CON(7), 4, GFLAGS),
943
944 /* aclk_perilp0 gates */
945 GATE(ACLK_INTMEM, "aclk_intmem", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 0, GFLAGS),
946 GATE(ACLK_TZMA, "aclk_tzma", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 1, GFLAGS),
947 GATE(SCLK_INTMEM0, "clk_intmem0", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 2, GFLAGS),
948 GATE(SCLK_INTMEM1, "clk_intmem1", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 3, GFLAGS),
949 GATE(SCLK_INTMEM2, "clk_intmem2", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 4, GFLAGS),
950 GATE(SCLK_INTMEM3, "clk_intmem3", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 5, GFLAGS),
951 GATE(SCLK_INTMEM4, "clk_intmem4", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 6, GFLAGS),
952 GATE(SCLK_INTMEM5, "clk_intmem5", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 7, GFLAGS),
953 GATE(ACLK_DCF, "aclk_dcf", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 8, GFLAGS),
954 GATE(ACLK_DMAC0_PERILP, "aclk_dmac0_perilp", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 5, GFLAGS),
955 GATE(ACLK_DMAC1_PERILP, "aclk_dmac1_perilp", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 6, GFLAGS),
956 GATE(ACLK_PERILP0_NOC, "aclk_perilp0_noc", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 7, GFLAGS),
957
958 /* hclk_perilp0 gates */
959 GATE(HCLK_ROM, "hclk_rom", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 4, GFLAGS),
960 GATE(HCLK_M_CRYPTO0, "hclk_m_crypto0", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 5, GFLAGS),
961 GATE(HCLK_S_CRYPTO0, "hclk_s_crypto0", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 6, GFLAGS),
962 GATE(HCLK_M_CRYPTO1, "hclk_m_crypto1", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 14, GFLAGS),
963 GATE(HCLK_S_CRYPTO1, "hclk_s_crypto1", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 15, GFLAGS),
964 GATE(HCLK_PERILP0_NOC, "hclk_perilp0_noc", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 8, GFLAGS),
965
966 /* pclk_perilp0 gates */
967 GATE(PCLK_DCF, "pclk_dcf", "pclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 9, GFLAGS),
968
969 /* crypto */
970 COMPOSITE(SCLK_CRYPTO0, "clk_crypto0", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED,
971 RK3399_CLKSEL_CON(24), 6, 2, MFLAGS, 0, 5, DFLAGS,
972 RK3399_CLKGATE_CON(7), 7, GFLAGS),
973
974 COMPOSITE(SCLK_CRYPTO1, "clk_crypto1", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED,
975 RK3399_CLKSEL_CON(26), 6, 2, MFLAGS, 0, 5, DFLAGS,
976 RK3399_CLKGATE_CON(7), 8, GFLAGS),
977
978 /* cm0s_perilp */
979 GATE(0, "cpll_fclk_cm0s_src", "cpll", CLK_IGNORE_UNUSED,
980 RK3399_CLKGATE_CON(7), 6, GFLAGS),
981 GATE(0, "gpll_fclk_cm0s_src", "gpll", CLK_IGNORE_UNUSED,
982 RK3399_CLKGATE_CON(7), 5, GFLAGS),
983 COMPOSITE(FCLK_CM0S, "fclk_cm0s", mux_fclk_cm0s_p, CLK_IGNORE_UNUSED,
984 RK3399_CLKSEL_CON(24), 15, 1, MFLAGS, 8, 5, DFLAGS,
985 RK3399_CLKGATE_CON(7), 9, GFLAGS),
986
987 /* fclk_cm0s gates */
988 GATE(SCLK_M0_PERILP, "sclk_m0_perilp", "fclk_cm0s", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 8, GFLAGS),
989 GATE(HCLK_M0_PERILP, "hclk_m0_perilp", "fclk_cm0s", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 9, GFLAGS),
990 GATE(DCLK_M0_PERILP, "dclk_m0_perilp", "fclk_cm0s", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 10, GFLAGS),
991 GATE(SCLK_M0_PERILP_DEC, "clk_m0_perilp_dec", "fclk_cm0s", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 11, GFLAGS),
992 GATE(HCLK_M0_PERILP_NOC, "hclk_m0_perilp_noc", "fclk_cm0s", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 11, GFLAGS),
993
994 /* perilp1 */
995 GATE(0, "cpll_hclk_perilp1_src", "cpll", CLK_IGNORE_UNUSED,
996 RK3399_CLKGATE_CON(8), 1, GFLAGS),
997 GATE(0, "gpll_hclk_perilp1_src", "gpll", CLK_IGNORE_UNUSED,
998 RK3399_CLKGATE_CON(8), 0, GFLAGS),
999 COMPOSITE_NOGATE(HCLK_PERILP1, "hclk_perilp1", mux_hclk_perilp1_p, CLK_IGNORE_UNUSED,
1000 RK3399_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 5, DFLAGS),
1001 COMPOSITE_NOMUX(PCLK_PERILP1, "pclk_perilp1", "hclk_perilp1", CLK_IGNORE_UNUSED,
1002 RK3399_CLKSEL_CON(25), 8, 3, DFLAGS,
1003 RK3399_CLKGATE_CON(8), 2, GFLAGS),
1004
1005 /* hclk_perilp1 gates */
1006 GATE(0, "hclk_perilp1_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 9, GFLAGS),
1007 GATE(0, "hclk_sdio_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 12, GFLAGS),
1008 GATE(HCLK_I2S0_8CH, "hclk_i2s0", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(34), 0, GFLAGS),
1009 GATE(HCLK_I2S1_8CH, "hclk_i2s1", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(34), 1, GFLAGS),
1010 GATE(HCLK_I2S2_8CH, "hclk_i2s2", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(34), 2, GFLAGS),
1011 GATE(HCLK_SPDIF, "hclk_spdif", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(34), 3, GFLAGS),
1012 GATE(HCLK_SDIO, "hclk_sdio", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(34), 4, GFLAGS),
1013 GATE(PCLK_SPI5, "pclk_spi5", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(34), 5, GFLAGS),
1014 GATE(0, "hclk_sdioaudio_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(34), 6, GFLAGS),
1015
1016 /* pclk_perilp1 gates */
1017 GATE(PCLK_UART0, "pclk_uart0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 0, GFLAGS),
1018 GATE(PCLK_UART1, "pclk_uart1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 1, GFLAGS),
1019 GATE(PCLK_UART2, "pclk_uart2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 2, GFLAGS),
1020 GATE(PCLK_UART3, "pclk_uart3", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 3, GFLAGS),
1021 GATE(PCLK_I2C7, "pclk_rki2c7", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 5, GFLAGS),
1022 GATE(PCLK_I2C1, "pclk_rki2c1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 6, GFLAGS),
1023 GATE(PCLK_I2C5, "pclk_rki2c5", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 7, GFLAGS),
1024 GATE(PCLK_I2C6, "pclk_rki2c6", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 8, GFLAGS),
1025 GATE(PCLK_I2C2, "pclk_rki2c2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 9, GFLAGS),
1026 GATE(PCLK_I2C3, "pclk_rki2c3", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 10, GFLAGS),
1027 GATE(PCLK_MAILBOX0, "pclk_mailbox0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 11, GFLAGS),
1028 GATE(PCLK_SARADC, "pclk_saradc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 12, GFLAGS),
1029 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 13, GFLAGS),
1030 GATE(PCLK_EFUSE1024NS, "pclk_efuse1024ns", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 14, GFLAGS),
1031 GATE(PCLK_EFUSE1024S, "pclk_efuse1024s", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 15, GFLAGS),
1032 GATE(PCLK_SPI0, "pclk_spi0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 10, GFLAGS),
1033 GATE(PCLK_SPI1, "pclk_spi1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 11, GFLAGS),
1034 GATE(PCLK_SPI2, "pclk_spi2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 12, GFLAGS),
1035 GATE(PCLK_SPI4, "pclk_spi4", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 13, GFLAGS),
1036 GATE(PCLK_PERIHP_GRF, "pclk_perilp_sgrf", "pclk_perilp1", 0, RK3399_CLKGATE_CON(24), 13, GFLAGS),
1037 GATE(0, "pclk_perilp1_noc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(25), 10, GFLAGS),
1038
1039 /* saradc */
1040 COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0,
1041 RK3399_CLKSEL_CON(26), 8, 8, DFLAGS,
1042 RK3399_CLKGATE_CON(9), 11, GFLAGS),
1043
1044 /* tsadc */
1045 COMPOSITE(SCLK_TSADC, "clk_tsadc", mux_pll_p, CLK_IGNORE_UNUSED,
1046 RK3399_CLKSEL_CON(27), 15, 1, MFLAGS, 0, 10, DFLAGS,
1047 RK3399_CLKGATE_CON(9), 10, GFLAGS),
1048
1049 /* cif_testout */
1050 MUX(0, "clk_testout1_pll_src", mux_pll_src_cpll_gpll_npll_p, 0,
1051 RK3399_CLKSEL_CON(38), 6, 2, MFLAGS),
1052 COMPOSITE(0, "clk_testout1", mux_clk_testout1_p, 0,
1053 RK3399_CLKSEL_CON(38), 5, 1, MFLAGS, 0, 5, DFLAGS,
1054 RK3399_CLKGATE_CON(13), 14, GFLAGS),
1055
1056 MUX(0, "clk_testout2_pll_src", mux_pll_src_cpll_gpll_npll_p, 0,
1057 RK3399_CLKSEL_CON(38), 14, 2, MFLAGS),
1058 COMPOSITE(0, "clk_testout2", mux_clk_testout2_p, 0,
1059 RK3399_CLKSEL_CON(38), 13, 1, MFLAGS, 8, 5, DFLAGS,
1060 RK3399_CLKGATE_CON(13), 15, GFLAGS),
1061
1062 /* vio */
1063 COMPOSITE(ACLK_VIO, "aclk_vio", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED,
1064 RK3399_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS,
1065 RK3399_CLKGATE_CON(11), 10, GFLAGS),
1066 COMPOSITE_NOMUX(PCLK_VIO, "pclk_vio", "aclk_vio", 0,
1067 RK3399_CLKSEL_CON(43), 0, 5, DFLAGS,
1068 RK3399_CLKGATE_CON(11), 1, GFLAGS),
1069
1070 GATE(ACLK_VIO_NOC, "aclk_vio_noc", "aclk_vio", CLK_IGNORE_UNUSED,
1071 RK3399_CLKGATE_CON(29), 0, GFLAGS),
1072
1073 GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "pclk_vio", CLK_IGNORE_UNUSED,
1074 RK3399_CLKGATE_CON(29), 1, GFLAGS),
1075 GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "pclk_vio", CLK_IGNORE_UNUSED,
1076 RK3399_CLKGATE_CON(29), 2, GFLAGS),
1077 GATE(PCLK_VIO_GRF, "pclk_vio_grf", "pclk_vio", CLK_IGNORE_UNUSED,
1078 RK3399_CLKGATE_CON(29), 12, GFLAGS),
1079
1080 /* hdcp */
1081 COMPOSITE(ACLK_HDCP, "aclk_hdcp", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED,
1082 RK3399_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS,
1083 RK3399_CLKGATE_CON(11), 12, GFLAGS),
1084 COMPOSITE_NOMUX(HCLK_HDCP, "hclk_hdcp", "aclk_hdcp", CLK_IGNORE_UNUSED,
1085 RK3399_CLKSEL_CON(43), 5, 5, DFLAGS,
1086 RK3399_CLKGATE_CON(11), 3, GFLAGS),
1087 COMPOSITE_NOMUX(PCLK_HDCP, "pclk_hdcp", "aclk_hdcp", CLK_IGNORE_UNUSED,
1088 RK3399_CLKSEL_CON(43), 10, 5, DFLAGS,
1089 RK3399_CLKGATE_CON(11), 10, GFLAGS),
1090
1091 GATE(ACLK_HDCP_NOC, "aclk_hdcp_noc", "aclk_hdcp", CLK_IGNORE_UNUSED,
1092 RK3399_CLKGATE_CON(29), 4, GFLAGS),
1093 GATE(ACLK_HDCP22, "aclk_hdcp22", "aclk_hdcp", CLK_IGNORE_UNUSED,
1094 RK3399_CLKGATE_CON(29), 10, GFLAGS),
1095
1096 GATE(HCLK_HDCP_NOC, "hclk_hdcp_noc", "hclk_hdcp", CLK_IGNORE_UNUSED,
1097 RK3399_CLKGATE_CON(29), 5, GFLAGS),
1098 GATE(HCLK_HDCP22, "hclk_hdcp22", "hclk_hdcp", CLK_IGNORE_UNUSED,
1099 RK3399_CLKGATE_CON(29), 9, GFLAGS),
1100
1101 GATE(PCLK_HDCP_NOC, "pclk_hdcp_noc", "pclk_hdcp", CLK_IGNORE_UNUSED,
1102 RK3399_CLKGATE_CON(29), 3, GFLAGS),
1103 GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "pclk_hdcp", CLK_IGNORE_UNUSED,
1104 RK3399_CLKGATE_CON(29), 6, GFLAGS),
1105 GATE(PCLK_DP_CTRL, "pclk_dp_ctrl", "pclk_hdcp", CLK_IGNORE_UNUSED,
1106 RK3399_CLKGATE_CON(29), 7, GFLAGS),
1107 GATE(PCLK_HDCP22, "pclk_hdcp22", "pclk_hdcp", CLK_IGNORE_UNUSED,
1108 RK3399_CLKGATE_CON(29), 8, GFLAGS),
1109 GATE(PCLK_GASKET, "pclk_gasket", "pclk_hdcp", CLK_IGNORE_UNUSED,
1110 RK3399_CLKGATE_CON(29), 11, GFLAGS),
1111
1112 /* edp */
1113 COMPOSITE(SCLK_DP_CORE, "clk_dp_core", mux_pll_src_npll_cpll_gpll_p, CLK_IGNORE_UNUSED,
1114 RK3399_CLKSEL_CON(46), 6, 2, MFLAGS, 0, 5, DFLAGS,
1115 RK3399_CLKGATE_CON(11), 8, GFLAGS),
1116
1117 COMPOSITE(PCLK_EDP, "pclk_edp", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
1118 RK3399_CLKSEL_CON(44), 15, 1, MFLAGS, 8, 5, DFLAGS,
1119 RK3399_CLKGATE_CON(11), 11, GFLAGS),
1120 GATE(PCLK_EDP_NOC, "pclk_edp_noc", "pclk_edp", CLK_IGNORE_UNUSED,
1121 RK3399_CLKGATE_CON(32), 12, GFLAGS),
1122 GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_edp", CLK_IGNORE_UNUSED,
1123 RK3399_CLKGATE_CON(32), 13, GFLAGS),
1124
1125 /* hdmi */
1126 GATE(SCLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", CLK_IGNORE_UNUSED,
1127 RK3399_CLKGATE_CON(11), 6, GFLAGS),
1128
1129 COMPOSITE(SCLK_HDMI_CEC, "clk_hdmi_cec", mux_pll_p, CLK_IGNORE_UNUSED,
1130 RK3399_CLKSEL_CON(45), 15, 1, MFLAGS, 0, 10, DFLAGS,
1131 RK3399_CLKGATE_CON(11), 7, GFLAGS),
1132
1133 /* vop0 */
1134 COMPOSITE(ACLK_VOP0_PRE, "aclk_vop0_pre", mux_pll_src_vpll_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
1135 RK3399_CLKSEL_CON(47), 6, 2, MFLAGS, 0, 5, DFLAGS,
1136 RK3399_CLKGATE_CON(10), 8, GFLAGS),
1137 COMPOSITE_NOMUX(0, "hclk_vop0_pre", "aclk_vop0_pre", 0,
1138 RK3399_CLKSEL_CON(47), 8, 5, DFLAGS,
1139 RK3399_CLKGATE_CON(10), 9, GFLAGS),
1140
1141 GATE(ACLK_VOP0, "aclk_vop0", "aclk_vop0_pre", CLK_IGNORE_UNUSED,
1142 RK3399_CLKGATE_CON(28), 3, GFLAGS),
1143 GATE(ACLK_VOP0_NOC, "aclk_vop0_noc", "aclk_vop0_pre", CLK_IGNORE_UNUSED,
1144 RK3399_CLKGATE_CON(28), 1, GFLAGS),
1145
1146 GATE(HCLK_VOP0, "hclk_vop0", "hclk_vop0_pre", CLK_IGNORE_UNUSED,
1147 RK3399_CLKGATE_CON(28), 2, GFLAGS),
1148 GATE(HCLK_VOP0_NOC, "hclk_vop0_noc", "hclk_vop0_pre", CLK_IGNORE_UNUSED,
1149 RK3399_CLKGATE_CON(28), 0, GFLAGS),
1150
1151 COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, CLK_IGNORE_UNUSED,
1152 RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS,
1153 RK3399_CLKGATE_CON(10), 12, GFLAGS),
1154
1155 COMPOSITE_FRACMUX_NOGATE(0, "dclk_vop0_frac", "dclk_vop0_div", CLK_SET_RATE_PARENT,
1156 RK3399_CLKSEL_CON(106), 0,
1157 &rk3399_dclk_vop0_fracmux),
1158
1159 COMPOSITE(SCLK_VOP0_PWM, "clk_vop0_pwm", mux_pll_src_vpll_cpll_gpll_24m_p, CLK_IGNORE_UNUSED,
1160 RK3399_CLKSEL_CON(51), 6, 2, MFLAGS, 0, 5, DFLAGS,
1161 RK3399_CLKGATE_CON(10), 14, GFLAGS),
1162
1163 /* vop1 */
1164 COMPOSITE(ACLK_VOP1_PRE, "aclk_vop1_pre", mux_pll_src_vpll_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
1165 RK3399_CLKSEL_CON(48), 6, 2, MFLAGS, 0, 5, DFLAGS,
1166 RK3399_CLKGATE_CON(10), 10, GFLAGS),
1167 COMPOSITE_NOMUX(0, "hclk_vop1_pre", "aclk_vop1_pre", 0,
1168 RK3399_CLKSEL_CON(48), 8, 5, DFLAGS,
1169 RK3399_CLKGATE_CON(10), 11, GFLAGS),
1170
1171 GATE(ACLK_VOP1, "aclk_vop1", "aclk_vop1_pre", CLK_IGNORE_UNUSED,
1172 RK3399_CLKGATE_CON(28), 7, GFLAGS),
1173 GATE(ACLK_VOP1_NOC, "aclk_vop1_noc", "aclk_vop1_pre", CLK_IGNORE_UNUSED,
1174 RK3399_CLKGATE_CON(28), 5, GFLAGS),
1175
1176 GATE(HCLK_VOP1, "hclk_vop1", "hclk_vop1_pre", CLK_IGNORE_UNUSED,
1177 RK3399_CLKGATE_CON(28), 6, GFLAGS),
1178 GATE(HCLK_VOP1_NOC, "hclk_vop1_noc", "hclk_vop1_pre", CLK_IGNORE_UNUSED,
1179 RK3399_CLKGATE_CON(28), 4, GFLAGS),
1180
1181 COMPOSITE(DCLK_VOP1_DIV, "dclk_vop1_div", mux_pll_src_vpll_cpll_gpll_p, CLK_IGNORE_UNUSED,
1182 RK3399_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 8, DFLAGS,
1183 RK3399_CLKGATE_CON(10), 13, GFLAGS),
1184
1185 COMPOSITE_FRACMUX_NOGATE(0, "dclk_vop1_frac", "dclk_vop1_div", CLK_SET_RATE_PARENT,
1186 RK3399_CLKSEL_CON(107), 0,
1187 &rk3399_dclk_vop1_fracmux),
1188
1189 COMPOSITE(SCLK_VOP1_PWM, "clk_vop1_pwm", mux_pll_src_vpll_cpll_gpll_24m_p, CLK_IGNORE_UNUSED,
1190 RK3399_CLKSEL_CON(52), 6, 2, MFLAGS, 0, 5, DFLAGS,
1191 RK3399_CLKGATE_CON(10), 15, GFLAGS),
1192
1193 /* isp */
1194 COMPOSITE(0, "aclk_isp0", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED,
1195 RK3399_CLKSEL_CON(53), 6, 2, MFLAGS, 0, 5, DFLAGS,
1196 RK3399_CLKGATE_CON(12), 8, GFLAGS),
1197 COMPOSITE_NOMUX(0, "hclk_isp0", "aclk_isp0", 0,
1198 RK3399_CLKSEL_CON(53), 8, 5, DFLAGS,
1199 RK3399_CLKGATE_CON(12), 9, GFLAGS),
1200
1201 GATE(ACLK_ISP0_NOC, "aclk_isp0_noc", "aclk_isp0", CLK_IGNORE_UNUSED,
1202 RK3399_CLKGATE_CON(27), 1, GFLAGS),
1203 GATE(ACLK_ISP0_WRAPPER, "aclk_isp0_wrapper", "aclk_isp0", CLK_IGNORE_UNUSED,
1204 RK3399_CLKGATE_CON(27), 5, GFLAGS),
1205 GATE(HCLK_ISP1_WRAPPER, "hclk_isp1_wrapper", "aclk_isp0", CLK_IGNORE_UNUSED,
1206 RK3399_CLKGATE_CON(27), 7, GFLAGS),
1207
1208 GATE(HCLK_ISP0_NOC, "hclk_isp0_noc", "hclk_isp0", CLK_IGNORE_UNUSED,
1209 RK3399_CLKGATE_CON(27), 0, GFLAGS),
1210 GATE(HCLK_ISP0_WRAPPER, "hclk_isp0_wrapper", "hclk_isp0", CLK_IGNORE_UNUSED,
1211 RK3399_CLKGATE_CON(27), 4, GFLAGS),
1212
1213 COMPOSITE(SCLK_ISP0, "clk_isp0", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
1214 RK3399_CLKSEL_CON(55), 6, 2, MFLAGS, 0, 5, DFLAGS,
1215 RK3399_CLKGATE_CON(11), 4, GFLAGS),
1216
1217 COMPOSITE(ACLK_ISP1, "aclk_isp1", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED,
1218 RK3399_CLKSEL_CON(54), 6, 2, MFLAGS, 0, 5, DFLAGS,
1219 RK3399_CLKGATE_CON(12), 10, GFLAGS),
1220 COMPOSITE_NOMUX(0, "hclk_isp1", "aclk_isp1", 0,
1221 RK3399_CLKSEL_CON(54), 8, 5, DFLAGS,
1222 RK3399_CLKGATE_CON(12), 11, GFLAGS),
1223
1224 GATE(ACLK_ISP1_NOC, "aclk_isp1_noc", "aclk_isp1", CLK_IGNORE_UNUSED,
1225 RK3399_CLKGATE_CON(27), 3, GFLAGS),
1226
1227 GATE(HCLK_ISP1_NOC, "hclk_isp1_noc", "hclk_isp1", CLK_IGNORE_UNUSED,
1228 RK3399_CLKGATE_CON(27), 2, GFLAGS),
1229 GATE(ACLK_ISP1_WRAPPER, "aclk_isp1_wrapper", "hclk_isp1", CLK_IGNORE_UNUSED,
1230 RK3399_CLKGATE_CON(27), 8, GFLAGS),
1231
1232 COMPOSITE(SCLK_ISP1, "clk_isp1", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
1233 RK3399_CLKSEL_CON(55), 14, 2, MFLAGS, 8, 5, DFLAGS,
1234 RK3399_CLKGATE_CON(11), 5, GFLAGS),
1235
1236 /*
1237 * We use pclkin_cifinv by default GRF_SOC_CON20[9] (GSC20_9) setting in system,
1238 * so we ignore the mux and make clocks nodes as following,
1239 *
1240 * pclkin_cifinv --|-------\
1241 * |GSC20_9|-- pclkin_cifmux -- |G27_6| -- pclkin_isp1_wrapper
1242 * pclkin_cif --|-------/
1243 */
1244 GATE(PCLK_ISP1_WRAPPER, "pclkin_isp1_wrapper", "pclkin_cif", CLK_IGNORE_UNUSED,
1245 RK3399_CLKGATE_CON(27), 6, GFLAGS),
1246
1247 /* cif */
1248 COMPOSITE(0, "clk_cifout_div", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
1249 RK3399_CLKSEL_CON(56), 6, 2, MFLAGS, 0, 5, DFLAGS,
1250 RK3399_CLKGATE_CON(10), 7, GFLAGS),
1251 MUX(SCLK_CIF_OUT, "clk_cifout", mux_clk_cif_p, CLK_SET_RATE_PARENT,
1252 RK3399_CLKSEL_CON(56), 5, 1, MFLAGS),
1253
1254 /* gic */
1255 COMPOSITE(ACLK_GIC_PRE, "aclk_gic_pre", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
1256 RK3399_CLKSEL_CON(56), 15, 1, MFLAGS, 8, 5, DFLAGS,
1257 RK3399_CLKGATE_CON(12), 12, GFLAGS),
1258
1259 GATE(ACLK_GIC, "aclk_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 0, GFLAGS),
1260 GATE(ACLK_GIC_NOC, "aclk_gic_noc", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 1, GFLAGS),
1261 GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_gic_adb400_core_l_2_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 2, GFLAGS),
1262 GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_gic_adb400_core_b_2_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 3, GFLAGS),
1263 GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_gic_adb400_gic_2_core_l", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 4, GFLAGS),
1264 GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_gic_adb400_gic_2_core_b", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 5, GFLAGS),
1265
1266 /* alive */
1267 /* pclk_alive_gpll_src is controlled by PMUGRF_SOC_CON0[6] */
1268 DIV(PCLK_ALIVE, "pclk_alive", "gpll", 0,
1269 RK3399_CLKSEL_CON(57), 0, 5, DFLAGS),
1270
1271 GATE(PCLK_USBPHY_MUX_G, "pclk_usbphy_mux_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 4, GFLAGS),
1272 GATE(PCLK_UPHY0_TCPHY_G, "pclk_uphy0_tcphy_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 5, GFLAGS),
1273 GATE(PCLK_UPHY0_TCPD_G, "pclk_uphy0_tcpd_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 6, GFLAGS),
1274 GATE(PCLK_UPHY1_TCPHY_G, "pclk_uphy1_tcphy_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 8, GFLAGS),
1275 GATE(PCLK_UPHY1_TCPD_G, "pclk_uphy1_tcpd_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 9, GFLAGS),
1276
1277 GATE(PCLK_GRF, "pclk_grf", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 1, GFLAGS),
1278 GATE(PCLK_INTR_ARB, "pclk_intr_arb", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 2, GFLAGS),
1279 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 3, GFLAGS),
1280 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 4, GFLAGS),
1281 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 5, GFLAGS),
1282 GATE(PCLK_TIMER0, "pclk_timer0", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 6, GFLAGS),
1283 GATE(PCLK_TIMER1, "pclk_timer1", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 7, GFLAGS),
1284 GATE(PCLK_PMU_INTR_ARB, "pclk_pmu_intr_arb", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 9, GFLAGS),
1285 GATE(PCLK_SGRF, "pclk_sgrf", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 10, GFLAGS),
1286
1287 GATE(SCLK_MIPIDPHY_REF, "clk_mipidphy_ref", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(11), 14, GFLAGS),
1288 GATE(SCLK_DPHY_PLL, "clk_dphy_pll", "clk_mipidphy_ref", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 0, GFLAGS),
1289
1290 GATE(SCLK_MIPIDPHY_CFG, "clk_mipidphy_cfg", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(11), 15, GFLAGS),
1291 GATE(SCLK_DPHY_TX0_CFG, "clk_dphy_tx0_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 1, GFLAGS),
1292 GATE(SCLK_DPHY_TX1RX1_CFG, "clk_dphy_tx1rx1_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 2, GFLAGS),
1293 GATE(SCLK_DPHY_RX0_CFG, "clk_dphy_rx0_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 3, GFLAGS),
1294
1295 /* testout */
1296 MUX(0, "clk_test_pre", mux_pll_src_cpll_gpll_p, CLK_SET_RATE_PARENT,
1297 RK3399_CLKSEL_CON(58), 7, 1, MFLAGS),
1298 COMPOSITE_FRAC(0, "clk_test_frac", "clk_test_pre", CLK_SET_RATE_PARENT,
1299 RK3399_CLKSEL_CON(105), 0,
1300 RK3399_CLKGATE_CON(13), 9, GFLAGS),
1301
1302 DIV(0, "clk_test_24m", "xin24m", 0,
1303 RK3399_CLKSEL_CON(57), 6, 10, DFLAGS),
1304
1305 /* spi */
1306 COMPOSITE(SCLK_SPI0, "clk_spi0", mux_pll_src_cpll_gpll_p, 0,
1307 RK3399_CLKSEL_CON(59), 7, 1, MFLAGS, 0, 7, DFLAGS,
1308 RK3399_CLKGATE_CON(9), 12, GFLAGS),
1309
1310 COMPOSITE(SCLK_SPI1, "clk_spi1", mux_pll_src_cpll_gpll_p, 0,
1311 RK3399_CLKSEL_CON(59), 15, 1, MFLAGS, 8, 7, DFLAGS,
1312 RK3399_CLKGATE_CON(9), 13, GFLAGS),
1313
1314 COMPOSITE(SCLK_SPI2, "clk_spi2", mux_pll_src_cpll_gpll_p, 0,
1315 RK3399_CLKSEL_CON(60), 7, 1, MFLAGS, 0, 7, DFLAGS,
1316 RK3399_CLKGATE_CON(9), 14, GFLAGS),
1317
1318 COMPOSITE(SCLK_SPI4, "clk_spi4", mux_pll_src_cpll_gpll_p, 0,
1319 RK3399_CLKSEL_CON(60), 15, 1, MFLAGS, 8, 7, DFLAGS,
1320 RK3399_CLKGATE_CON(9), 15, GFLAGS),
1321
1322 COMPOSITE(SCLK_SPI5, "clk_spi5", mux_pll_src_cpll_gpll_p, 0,
1323 RK3399_CLKSEL_CON(58), 15, 1, MFLAGS, 8, 7, DFLAGS,
1324 RK3399_CLKGATE_CON(13), 13, GFLAGS),
1325
1326 /* i2c */
1327 COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_pll_src_cpll_gpll_p, 0,
1328 RK3399_CLKSEL_CON(61), 7, 1, MFLAGS, 0, 7, DFLAGS,
1329 RK3399_CLKGATE_CON(10), 0, GFLAGS),
1330
1331 COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_pll_src_cpll_gpll_p, 0,
1332 RK3399_CLKSEL_CON(62), 7, 1, MFLAGS, 0, 7, DFLAGS,
1333 RK3399_CLKGATE_CON(10), 2, GFLAGS),
1334
1335 COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_pll_src_cpll_gpll_p, 0,
1336 RK3399_CLKSEL_CON(63), 7, 1, MFLAGS, 0, 7, DFLAGS,
1337 RK3399_CLKGATE_CON(10), 4, GFLAGS),
1338
1339 COMPOSITE(SCLK_I2C5, "clk_i2c5", mux_pll_src_cpll_gpll_p, 0,
1340 RK3399_CLKSEL_CON(61), 15, 1, MFLAGS, 8, 7, DFLAGS,
1341 RK3399_CLKGATE_CON(10), 1, GFLAGS),
1342
1343 COMPOSITE(SCLK_I2C6, "clk_i2c6", mux_pll_src_cpll_gpll_p, 0,
1344 RK3399_CLKSEL_CON(62), 15, 1, MFLAGS, 8, 7, DFLAGS,
1345 RK3399_CLKGATE_CON(10), 3, GFLAGS),
1346
1347 COMPOSITE(SCLK_I2C7, "clk_i2c7", mux_pll_src_cpll_gpll_p, 0,
1348 RK3399_CLKSEL_CON(63), 15, 1, MFLAGS, 8, 7, DFLAGS,
1349 RK3399_CLKGATE_CON(10), 5, GFLAGS),
1350
1351 /* timer */
1352 GATE(SCLK_TIMER00, "clk_timer00", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 0, GFLAGS),
1353 GATE(SCLK_TIMER01, "clk_timer01", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 1, GFLAGS),
1354 GATE(SCLK_TIMER02, "clk_timer02", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 2, GFLAGS),
1355 GATE(SCLK_TIMER03, "clk_timer03", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 3, GFLAGS),
1356 GATE(SCLK_TIMER04, "clk_timer04", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 4, GFLAGS),
1357 GATE(SCLK_TIMER05, "clk_timer05", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 5, GFLAGS),
1358 GATE(SCLK_TIMER06, "clk_timer06", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 6, GFLAGS),
1359 GATE(SCLK_TIMER07, "clk_timer07", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 7, GFLAGS),
1360 GATE(SCLK_TIMER08, "clk_timer08", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 8, GFLAGS),
1361 GATE(SCLK_TIMER09, "clk_timer09", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 9, GFLAGS),
1362 GATE(SCLK_TIMER10, "clk_timer10", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 10, GFLAGS),
1363 GATE(SCLK_TIMER11, "clk_timer11", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 11, GFLAGS),
1364
1365 /* clk_test */
1366 /* clk_test_pre is controlled by CRU_MISC_CON[3] */
1367 COMPOSITE_NOMUX(0, "clk_test", "clk_test_pre", CLK_IGNORE_UNUSED,
1368 RK3368_CLKSEL_CON(58), 0, 5, DFLAGS,
1369 RK3368_CLKGATE_CON(13), 11, GFLAGS),
1370};
1371
1372static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = {
1373 /*
1374 * PMU CRU Clock-Architecture
1375 */
1376
1377 GATE(0, "fclk_cm0s_pmu_ppll_src", "ppll", CLK_IGNORE_UNUSED,
1378 RK3399_PMU_CLKGATE_CON(0), 1, GFLAGS),
1379
1380 COMPOSITE_NOGATE(FCLK_CM0S_SRC_PMU, "fclk_cm0s_src_pmu", mux_fclk_cm0s_pmu_ppll_p, CLK_IGNORE_UNUSED,
1381 RK3399_PMU_CLKSEL_CON(0), 15, 1, MFLAGS, 8, 5, DFLAGS),
1382
1383 COMPOSITE(SCLK_SPI3_PMU, "clk_spi3_pmu", mux_24m_ppll_p, CLK_IGNORE_UNUSED,
1384 RK3399_PMU_CLKSEL_CON(1), 7, 1, MFLAGS, 0, 7, DFLAGS,
1385 RK3399_PMU_CLKGATE_CON(0), 2, GFLAGS),
1386
1387 COMPOSITE(0, "clk_wifi_div", mux_ppll_24m_p, CLK_IGNORE_UNUSED,
1388 RK3399_PMU_CLKSEL_CON(1), 13, 1, MFLAGS, 8, 5, DFLAGS,
1389 RK3399_PMU_CLKGATE_CON(0), 8, GFLAGS),
1390
1391 COMPOSITE_FRACMUX_NOGATE(0, "clk_wifi_frac", "clk_wifi_div", CLK_SET_RATE_PARENT,
1392 RK3399_PMU_CLKSEL_CON(7), 0,
1393 &rk3399_pmuclk_wifi_fracmux),
1394
1395 MUX(0, "clk_timer_src_pmu", mux_pll_p, CLK_IGNORE_UNUSED,
1396 RK3399_PMU_CLKSEL_CON(1), 15, 1, MFLAGS),
1397
1398 COMPOSITE_NOMUX(SCLK_I2C0_PMU, "clk_i2c0_pmu", "ppll", 0,
1399 RK3399_PMU_CLKSEL_CON(2), 0, 7, DFLAGS,
1400 RK3399_PMU_CLKGATE_CON(0), 9, GFLAGS),
1401
1402 COMPOSITE_NOMUX(SCLK_I2C4_PMU, "clk_i2c4_pmu", "ppll", 0,
1403 RK3399_PMU_CLKSEL_CON(3), 0, 7, DFLAGS,
1404 RK3399_PMU_CLKGATE_CON(0), 11, GFLAGS),
1405
1406 COMPOSITE_NOMUX(SCLK_I2C8_PMU, "clk_i2c8_pmu", "ppll", 0,
1407 RK3399_PMU_CLKSEL_CON(2), 8, 7, DFLAGS,
1408 RK3399_PMU_CLKGATE_CON(0), 10, GFLAGS),
1409
1410 DIV(0, "clk_32k_suspend_pmu", "xin24m", CLK_IGNORE_UNUSED,
1411 RK3399_PMU_CLKSEL_CON(4), 0, 10, DFLAGS),
1412 MUX(0, "clk_testout_2io", mux_clk_testout2_2io_p, CLK_IGNORE_UNUSED,
1413 RK3399_PMU_CLKSEL_CON(4), 15, 1, MFLAGS),
1414
1415 COMPOSITE(0, "clk_uart4_div", mux_24m_ppll_p, CLK_IGNORE_UNUSED,
1416 RK3399_PMU_CLKSEL_CON(5), 10, 1, MFLAGS, 0, 7, DFLAGS,
1417 RK3399_PMU_CLKGATE_CON(0), 5, GFLAGS),
1418
1419 COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_div", CLK_SET_RATE_PARENT,
1420 RK3399_PMU_CLKSEL_CON(6), 0,
1421 RK3399_PMU_CLKGATE_CON(0), 6, GFLAGS,
1422 &rk3399_uart4_pmu_fracmux),
1423
1424 DIV(PCLK_SRC_PMU, "pclk_pmu_src", "ppll", CLK_IGNORE_UNUSED,
1425 RK3399_PMU_CLKSEL_CON(0), 0, 5, DFLAGS),
1426
1427 /* pmu clock gates */
1428 GATE(SCLK_TIMER12_PMU, "clk_timer0_pmu", "clk_timer_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(0), 3, GFLAGS),
1429 GATE(SCLK_TIMER13_PMU, "clk_timer1_pmu", "clk_timer_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(0), 4, GFLAGS),
1430
1431 GATE(SCLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(0), 7, GFLAGS),
1432
1433 GATE(PCLK_PMU, "pclk_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 0, GFLAGS),
1434 GATE(PCLK_PMUGRF_PMU, "pclk_pmugrf_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 1, GFLAGS),
1435 GATE(PCLK_INTMEM1_PMU, "pclk_intmem1_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 2, GFLAGS),
1436 GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 3, GFLAGS),
1437 GATE(PCLK_GPIO1_PMU, "pclk_gpio1_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 4, GFLAGS),
1438 GATE(PCLK_SGRF_PMU, "pclk_sgrf_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 5, GFLAGS),
1439 GATE(PCLK_NOC_PMU, "pclk_noc_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 6, GFLAGS),
1440 GATE(PCLK_I2C0_PMU, "pclk_i2c0_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 7, GFLAGS),
1441 GATE(PCLK_I2C4_PMU, "pclk_i2c4_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 8, GFLAGS),
1442 GATE(PCLK_I2C8_PMU, "pclk_i2c8_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 9, GFLAGS),
1443 GATE(PCLK_RKPWM_PMU, "pclk_rkpwm_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 10, GFLAGS),
1444 GATE(PCLK_SPI3_PMU, "pclk_spi3_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 11, GFLAGS),
1445 GATE(PCLK_TIMER_PMU, "pclk_timer_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 12, GFLAGS),
1446 GATE(PCLK_MAILBOX_PMU, "pclk_mailbox_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 13, GFLAGS),
1447 GATE(PCLK_UART4_PMU, "pclk_uart4_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 14, GFLAGS),
1448 GATE(PCLK_WDT_M0_PMU, "pclk_wdt_m0_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 15, GFLAGS),
1449
1450 GATE(FCLK_CM0S_PMU, "fclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 0, GFLAGS),
1451 GATE(SCLK_CM0S_PMU, "sclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 1, GFLAGS),
1452 GATE(HCLK_CM0S_PMU, "hclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 2, GFLAGS),
1453 GATE(DCLK_CM0S_PMU, "dclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 3, GFLAGS),
1454 GATE(HCLK_NOC_PMU, "hclk_noc_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 5, GFLAGS),
1455};
1456
1457static const char *const rk3399_cru_critical_clocks[] __initconst = {
1458 "aclk_cci_pre",
1459 "pclk_perilp0",
1460 "pclk_perilp0",
1461 "hclk_perilp0",
1462 "hclk_perilp0_noc",
1463 "pclk_perilp1",
1464 "pclk_perilp1_noc",
1465 "pclk_perihp",
1466 "pclk_perihp_noc",
1467 "hclk_perihp",
1468 "aclk_perihp",
1469 "aclk_perihp_noc",
1470 "aclk_perilp0",
1471 "aclk_perilp0_noc",
1472 "hclk_perilp1",
1473 "hclk_perilp1_noc",
1474 "aclk_dmac0_perilp",
1475 "gpll_hclk_perilp1_src",
1476 "gpll_aclk_perilp0_src",
1477 "gpll_aclk_perihp_src",
1478};
1479
1480static const char *const rk3399_pmucru_critical_clocks[] __initconst = {
1481 "ppll",
1482 "pclk_pmu_src",
1483 "fclk_cm0s_src_pmu",
1484 "clk_timer_src_pmu",
1485};
1486
1487static void __init rk3399_clk_init(struct device_node *np)
1488{
1489 struct rockchip_clk_provider *ctx;
1490 void __iomem *reg_base;
1491
1492 reg_base = of_iomap(np, 0);
1493 if (!reg_base) {
1494 pr_err("%s: could not map cru region\n", __func__);
1495 return;
1496 }
1497
1498 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
1499 if (IS_ERR(ctx)) {
1500 pr_err("%s: rockchip clk init failed\n", __func__);
1501 return;
1502 }
1503
1504 rockchip_clk_register_plls(ctx, rk3399_pll_clks,
1505 ARRAY_SIZE(rk3399_pll_clks), -1);
1506
1507 rockchip_clk_register_branches(ctx, rk3399_clk_branches,
1508 ARRAY_SIZE(rk3399_clk_branches));
1509
1510 rockchip_clk_protect_critical(rk3399_cru_critical_clocks,
1511 ARRAY_SIZE(rk3399_cru_critical_clocks));
1512
1513 rockchip_clk_register_armclk(ctx, ARMCLKL, "armclkl",
1514 mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p),
1515 &rk3399_cpuclkl_data, rk3399_cpuclkl_rates,
1516 ARRAY_SIZE(rk3399_cpuclkl_rates));
1517
1518 rockchip_clk_register_armclk(ctx, ARMCLKB, "armclkb",
1519 mux_armclkb_p, ARRAY_SIZE(mux_armclkb_p),
1520 &rk3399_cpuclkb_data, rk3399_cpuclkb_rates,
1521 ARRAY_SIZE(rk3399_cpuclkb_rates));
1522
1523 rockchip_register_softrst(np, 21, reg_base + RK3399_SOFTRST_CON(0),
1524 ROCKCHIP_SOFTRST_HIWORD_MASK);
1525
1526 rockchip_register_restart_notifier(ctx, RK3399_GLB_SRST_FST, NULL);
1527
1528 rockchip_clk_of_add_provider(np, ctx);
1529}
1530CLK_OF_DECLARE(rk3399_cru, "rockchip,rk3399-cru", rk3399_clk_init);
1531
1532static void __init rk3399_pmu_clk_init(struct device_node *np)
1533{
1534 struct rockchip_clk_provider *ctx;
1535 void __iomem *reg_base;
1536
1537 reg_base = of_iomap(np, 0);
1538 if (!reg_base) {
1539 pr_err("%s: could not map cru pmu region\n", __func__);
1540 return;
1541 }
1542
1543 ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS);
1544 if (IS_ERR(ctx)) {
1545 pr_err("%s: rockchip pmu clk init failed\n", __func__);
1546 return;
1547 }
1548
1549 rockchip_clk_register_plls(ctx, rk3399_pmu_pll_clks,
1550 ARRAY_SIZE(rk3399_pmu_pll_clks), -1);
1551
1552 rockchip_clk_register_branches(ctx, rk3399_clk_pmu_branches,
1553 ARRAY_SIZE(rk3399_clk_pmu_branches));
1554
1555 rockchip_clk_protect_critical(rk3399_pmucru_critical_clocks,
Heiko Stuebner995d3fd2016-04-19 21:07:01 +0200[diff] [blame]1556 ARRAY_SIZE(rk3399_pmucru_critical_clocks));
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1557
1558 rockchip_register_softrst(np, 2, reg_base + RK3399_PMU_SOFTRST_CON(0),
1559 ROCKCHIP_SOFTRST_HIWORD_MASK);
1560
1561 rockchip_clk_of_add_provider(np, ctx);
1562}
1563CLK_OF_DECLARE(rk3399_cru_pmu, "rockchip,rk3399-pmucru", rk3399_pmu_clk_init);