blob: eeb55ed2152d4377ac69b5a892906439d4cfdca8 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
3 *
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
Ayaz Abdulla87046e52006-12-19 23:33:32 -05006 * and Andrew de Quincey.
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
8 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
9 * trademarks of NVIDIA Corporation in the United States and other
10 * countries.
11 *
Manfred Spraul18360982005-12-24 14:19:24 +010012 * Copyright (C) 2003,4,5 Manfred Spraul
Linus Torvalds1da177e2005-04-16 15:20:36 -070013 * Copyright (C) 2004 Andrew de Quincey (wol support)
14 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
15 * IRQ rate fixes, bigendian fixes, cleanups, verification)
Ayaz Abdullaf648d122008-01-13 16:02:57 -050016 * Copyright (c) 2004,2005,2006,2007,2008 NVIDIA Corporation
Linus Torvalds1da177e2005-04-16 15:20:36 -070017 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070032 * Known bugs:
33 * We suspect that on some hardware no TX done interrupts are generated.
34 * This means recovery from netif_stop_queue only happens if the hw timer
35 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
36 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
37 * If your hardware reliably generates tx done interrupts, then you can remove
38 * DEV_NEED_TIMERIRQ from the driver_data flags.
39 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
40 * superfluous timer interrupts from the nic.
41 */
Jeff Garzik8148ff42007-10-16 20:56:09 -040042#define FORCEDETH_VERSION "0.61"
Linus Torvalds1da177e2005-04-16 15:20:36 -070043#define DRV_NAME "forcedeth"
44
45#include <linux/module.h>
46#include <linux/types.h>
47#include <linux/pci.h>
48#include <linux/interrupt.h>
49#include <linux/netdevice.h>
50#include <linux/etherdevice.h>
51#include <linux/delay.h>
52#include <linux/spinlock.h>
53#include <linux/ethtool.h>
54#include <linux/timer.h>
55#include <linux/skbuff.h>
56#include <linux/mii.h>
57#include <linux/random.h>
58#include <linux/init.h>
Manfred Spraul22c6d142005-04-19 21:17:09 +020059#include <linux/if_vlan.h>
Matthias Gehre910638a2006-03-28 01:56:48 -080060#include <linux/dma-mapping.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070061
62#include <asm/irq.h>
63#include <asm/io.h>
64#include <asm/uaccess.h>
65#include <asm/system.h>
66
67#if 0
68#define dprintk printk
69#else
70#define dprintk(x...) do { } while (0)
71#endif
72
Stephen Hemmingerbea33482007-10-03 16:41:36 -070073#define TX_WORK_PER_LOOP 64
74#define RX_WORK_PER_LOOP 64
Linus Torvalds1da177e2005-04-16 15:20:36 -070075
76/*
77 * Hardware access:
78 */
79
Ayaz Abdulla9c662432008-08-06 12:11:42 -040080#define DEV_NEED_TIMERIRQ 0x000001 /* set the timer irq flag in the irq mask */
81#define DEV_NEED_LINKTIMER 0x000002 /* poll link settings. Relies on the timer irq */
82#define DEV_HAS_LARGEDESC 0x000004 /* device supports jumbo frames and needs packet format 2 */
83#define DEV_HAS_HIGH_DMA 0x000008 /* device supports 64bit dma */
84#define DEV_HAS_CHECKSUM 0x000010 /* device supports tx and rx checksum offloads */
85#define DEV_HAS_VLAN 0x000020 /* device supports vlan tagging and striping */
86#define DEV_HAS_MSI 0x000040 /* device supports MSI */
87#define DEV_HAS_MSI_X 0x000080 /* device supports MSI-X */
88#define DEV_HAS_POWER_CNTRL 0x000100 /* device supports power savings */
89#define DEV_HAS_STATISTICS_V1 0x000200 /* device supports hw statistics version 1 */
90#define DEV_HAS_STATISTICS_V2 0x000400 /* device supports hw statistics version 2 */
91#define DEV_HAS_STATISTICS_V3 0x000800 /* device supports hw statistics version 3 */
92#define DEV_HAS_TEST_EXTENDED 0x001000 /* device supports extended diagnostic test */
93#define DEV_HAS_MGMT_UNIT 0x002000 /* device supports management unit */
94#define DEV_HAS_CORRECT_MACADDR 0x004000 /* device supports correct mac address order */
95#define DEV_HAS_COLLISION_FIX 0x008000 /* device supports tx collision fix */
96#define DEV_HAS_PAUSEFRAME_TX_V1 0x010000 /* device supports tx pause frames version 1 */
97#define DEV_HAS_PAUSEFRAME_TX_V2 0x020000 /* device supports tx pause frames version 2 */
98#define DEV_HAS_PAUSEFRAME_TX_V3 0x040000 /* device supports tx pause frames version 3 */
99#define DEV_NEED_TX_LIMIT 0x080000 /* device needs to limit tx */
100#define DEV_HAS_GEAR_MODE 0x100000 /* device supports gear mode */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700101
102enum {
103 NvRegIrqStatus = 0x000,
104#define NVREG_IRQSTAT_MIIEVENT 0x040
Ayaz Abdullac5cf9102006-10-30 17:32:01 -0500105#define NVREG_IRQSTAT_MASK 0x81ff
Linus Torvalds1da177e2005-04-16 15:20:36 -0700106 NvRegIrqMask = 0x004,
107#define NVREG_IRQ_RX_ERROR 0x0001
108#define NVREG_IRQ_RX 0x0002
109#define NVREG_IRQ_RX_NOBUF 0x0004
110#define NVREG_IRQ_TX_ERR 0x0008
Manfred Spraulc2dba062005-07-31 18:29:47 +0200111#define NVREG_IRQ_TX_OK 0x0010
Linus Torvalds1da177e2005-04-16 15:20:36 -0700112#define NVREG_IRQ_TIMER 0x0020
113#define NVREG_IRQ_LINK 0x0040
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500114#define NVREG_IRQ_RX_FORCED 0x0080
115#define NVREG_IRQ_TX_FORCED 0x0100
Ayaz Abdullac5cf9102006-10-30 17:32:01 -0500116#define NVREG_IRQ_RECOVER_ERROR 0x8000
Ayaz Abdullaa971c322005-11-11 08:30:38 -0500117#define NVREG_IRQMASK_THROUGHPUT 0x00df
Ayaz Abdulla096a4582007-05-21 20:23:11 -0400118#define NVREG_IRQMASK_CPU 0x0060
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500119#define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
120#define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
Ayaz Abdullac5cf9102006-10-30 17:32:01 -0500121#define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
Manfred Spraulc2dba062005-07-31 18:29:47 +0200122
123#define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500124 NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \
Ayaz Abdullac5cf9102006-10-30 17:32:01 -0500125 NVREG_IRQ_TX_FORCED|NVREG_IRQ_RECOVER_ERROR))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700126
127 NvRegUnknownSetupReg6 = 0x008,
128#define NVREG_UNKSETUP6_VAL 3
129
130/*
131 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
132 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
133 */
134 NvRegPollingInterval = 0x00c,
Ayaz Abdulla4e16ed12007-01-23 12:00:56 -0500135#define NVREG_POLL_DEFAULT_THROUGHPUT 970 /* backup tx cleanup if loop max reached */
Ayaz Abdullaa971c322005-11-11 08:30:38 -0500136#define NVREG_POLL_DEFAULT_CPU 13
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500137 NvRegMSIMap0 = 0x020,
138 NvRegMSIMap1 = 0x024,
139 NvRegMSIIrqMask = 0x030,
140#define NVREG_MSI_VECTOR_0_ENABLED 0x01
Linus Torvalds1da177e2005-04-16 15:20:36 -0700141 NvRegMisc1 = 0x080,
Ayaz Abdullaeb91f612006-05-24 18:13:19 -0400142#define NVREG_MISC1_PAUSE_TX 0x01
Linus Torvalds1da177e2005-04-16 15:20:36 -0700143#define NVREG_MISC1_HD 0x02
144#define NVREG_MISC1_FORCE 0x3b0f3c
145
Ayaz Abdulla0a626772008-01-13 16:02:42 -0500146 NvRegMacReset = 0x34,
Ayaz Abdulla86a0f042006-04-24 18:41:31 -0400147#define NVREG_MAC_RESET_ASSERT 0x0F3
Linus Torvalds1da177e2005-04-16 15:20:36 -0700148 NvRegTransmitterControl = 0x084,
149#define NVREG_XMITCTL_START 0x01
Ayaz Abdulla7e680c22006-10-30 17:31:51 -0500150#define NVREG_XMITCTL_MGMT_ST 0x40000000
151#define NVREG_XMITCTL_SYNC_MASK 0x000f0000
152#define NVREG_XMITCTL_SYNC_NOT_READY 0x0
153#define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000
154#define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00
155#define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0
156#define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000
157#define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000
158#define NVREG_XMITCTL_HOST_LOADED 0x00004000
Ayaz Abdullaf35723e2003-02-20 03:03:54 -0500159#define NVREG_XMITCTL_TX_PATH_EN 0x01000000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700160 NvRegTransmitterStatus = 0x088,
161#define NVREG_XMITSTAT_BUSY 0x01
162
163 NvRegPacketFilterFlags = 0x8c,
Ayaz Abdullaeb91f612006-05-24 18:13:19 -0400164#define NVREG_PFF_PAUSE_RX 0x08
165#define NVREG_PFF_ALWAYS 0x7F0000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700166#define NVREG_PFF_PROMISC 0x80
167#define NVREG_PFF_MYADDR 0x20
Ayaz Abdulla9589c772006-06-10 22:48:13 -0400168#define NVREG_PFF_LOOPBACK 0x10
Linus Torvalds1da177e2005-04-16 15:20:36 -0700169
170 NvRegOffloadConfig = 0x90,
171#define NVREG_OFFLOAD_HOMEPHY 0x601
172#define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
173 NvRegReceiverControl = 0x094,
174#define NVREG_RCVCTL_START 0x01
Ayaz Abdullaf35723e2003-02-20 03:03:54 -0500175#define NVREG_RCVCTL_RX_PATH_EN 0x01000000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700176 NvRegReceiverStatus = 0x98,
177#define NVREG_RCVSTAT_BUSY 0x01
178
Ayaz Abdullaa4336862008-04-18 13:50:43 -0700179 NvRegSlotTime = 0x9c,
180#define NVREG_SLOTTIME_LEGBF_ENABLED 0x80000000
181#define NVREG_SLOTTIME_10_100_FULL 0x00007f00
182#define NVREG_SLOTTIME_1000_FULL 0x0003ff00
183#define NVREG_SLOTTIME_HALF 0x0000ff00
184#define NVREG_SLOTTIME_DEFAULT 0x00007f00
185#define NVREG_SLOTTIME_MASK 0x000000ff
Linus Torvalds1da177e2005-04-16 15:20:36 -0700186
Ayaz Abdulla9744e212006-07-06 16:45:58 -0400187 NvRegTxDeferral = 0xA0,
Ayaz Abdullafd9b5582008-02-05 12:29:49 -0500188#define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
189#define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f
190#define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f
191#define NVREG_TX_DEFERRAL_RGMII_STRETCH_10 0x16190f
192#define NVREG_TX_DEFERRAL_RGMII_STRETCH_100 0x16300f
193#define NVREG_TX_DEFERRAL_MII_STRETCH 0x152000
Ayaz Abdulla9744e212006-07-06 16:45:58 -0400194 NvRegRxDeferral = 0xA4,
195#define NVREG_RX_DEFERRAL_DEFAULT 0x16
Linus Torvalds1da177e2005-04-16 15:20:36 -0700196 NvRegMacAddrA = 0xA8,
197 NvRegMacAddrB = 0xAC,
198 NvRegMulticastAddrA = 0xB0,
199#define NVREG_MCASTADDRA_FORCE 0x01
200 NvRegMulticastAddrB = 0xB4,
201 NvRegMulticastMaskA = 0xB8,
Ayaz Abdullabb9a4fd2008-01-13 16:03:04 -0500202#define NVREG_MCASTMASKA_NONE 0xffffffff
Linus Torvalds1da177e2005-04-16 15:20:36 -0700203 NvRegMulticastMaskB = 0xBC,
Ayaz Abdullabb9a4fd2008-01-13 16:03:04 -0500204#define NVREG_MCASTMASKB_NONE 0xffff
Linus Torvalds1da177e2005-04-16 15:20:36 -0700205
206 NvRegPhyInterface = 0xC0,
207#define PHY_RGMII 0x10000000
Ayaz Abdullaa4336862008-04-18 13:50:43 -0700208 NvRegBackOffControl = 0xC4,
209#define NVREG_BKOFFCTRL_DEFAULT 0x70000000
210#define NVREG_BKOFFCTRL_SEED_MASK 0x000003ff
211#define NVREG_BKOFFCTRL_SELECT 24
212#define NVREG_BKOFFCTRL_GEAR 12
Linus Torvalds1da177e2005-04-16 15:20:36 -0700213
214 NvRegTxRingPhysAddr = 0x100,
215 NvRegRxRingPhysAddr = 0x104,
216 NvRegRingSizes = 0x108,
217#define NVREG_RINGSZ_TXSHIFT 0
218#define NVREG_RINGSZ_RXSHIFT 16
Ayaz Abdulla5070d342006-07-31 12:05:01 -0400219 NvRegTransmitPoll = 0x10c,
220#define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700221 NvRegLinkSpeed = 0x110,
222#define NVREG_LINKSPEED_FORCE 0x10000
223#define NVREG_LINKSPEED_10 1000
224#define NVREG_LINKSPEED_100 100
225#define NVREG_LINKSPEED_1000 50
226#define NVREG_LINKSPEED_MASK (0xFFF)
227 NvRegUnknownSetupReg5 = 0x130,
228#define NVREG_UNKSETUP5_BIT31 (1<<31)
Ayaz Abdulla95d161c2006-07-06 16:46:25 -0400229 NvRegTxWatermark = 0x13c,
230#define NVREG_TX_WM_DESC1_DEFAULT 0x0200010
231#define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
232#define NVREG_TX_WM_DESC2_3_1000 0xfe08000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700233 NvRegTxRxControl = 0x144,
234#define NVREG_TXRXCTL_KICK 0x0001
235#define NVREG_TXRXCTL_BIT1 0x0002
236#define NVREG_TXRXCTL_BIT2 0x0004
237#define NVREG_TXRXCTL_IDLE 0x0008
238#define NVREG_TXRXCTL_RESET 0x0010
239#define NVREG_TXRXCTL_RXCHECK 0x0400
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -0400240#define NVREG_TXRXCTL_DESC_1 0
Ayaz Abdullad2f78412007-01-09 13:30:02 -0500241#define NVREG_TXRXCTL_DESC_2 0x002100
242#define NVREG_TXRXCTL_DESC_3 0xc02200
Ayaz Abdullaee407b02006-02-04 13:13:17 -0500243#define NVREG_TXRXCTL_VLANSTRIP 0x00040
244#define NVREG_TXRXCTL_VLANINS 0x00080
Ayaz Abdulla0832b252006-02-04 13:13:26 -0500245 NvRegTxRingPhysAddrHigh = 0x148,
246 NvRegRxRingPhysAddrHigh = 0x14C,
Ayaz Abdullaeb91f612006-05-24 18:13:19 -0400247 NvRegTxPauseFrame = 0x170,
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -0500248#define NVREG_TX_PAUSEFRAME_DISABLE 0x0fff0080
249#define NVREG_TX_PAUSEFRAME_ENABLE_V1 0x01800010
250#define NVREG_TX_PAUSEFRAME_ENABLE_V2 0x056003f0
251#define NVREG_TX_PAUSEFRAME_ENABLE_V3 0x09f00880
Ayaz Abdulla9a33e882008-08-06 12:12:34 -0400252 NvRegTxPauseFrameLimit = 0x174,
253#define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700254 NvRegMIIStatus = 0x180,
255#define NVREG_MIISTAT_ERROR 0x0001
256#define NVREG_MIISTAT_LINKCHANGE 0x0008
Ayaz Abdullaeb798422008-02-04 15:14:04 -0500257#define NVREG_MIISTAT_MASK_RW 0x0007
258#define NVREG_MIISTAT_MASK_ALL 0x000f
Ayaz Abdulla7e680c22006-10-30 17:31:51 -0500259 NvRegMIIMask = 0x184,
260#define NVREG_MII_LINKCHANGE 0x0008
Linus Torvalds1da177e2005-04-16 15:20:36 -0700261
262 NvRegAdapterControl = 0x188,
263#define NVREG_ADAPTCTL_START 0x02
264#define NVREG_ADAPTCTL_LINKUP 0x04
265#define NVREG_ADAPTCTL_PHYVALID 0x40000
266#define NVREG_ADAPTCTL_RUNNING 0x100000
267#define NVREG_ADAPTCTL_PHYSHIFT 24
268 NvRegMIISpeed = 0x18c,
269#define NVREG_MIISPEED_BIT8 (1<<8)
270#define NVREG_MIIDELAY 5
271 NvRegMIIControl = 0x190,
272#define NVREG_MIICTL_INUSE 0x08000
273#define NVREG_MIICTL_WRITE 0x00400
274#define NVREG_MIICTL_ADDRSHIFT 5
275 NvRegMIIData = 0x194,
Ayaz Abdulla9c662432008-08-06 12:11:42 -0400276 NvRegTxUnicast = 0x1a0,
277 NvRegTxMulticast = 0x1a4,
278 NvRegTxBroadcast = 0x1a8,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700279 NvRegWakeUpFlags = 0x200,
280#define NVREG_WAKEUPFLAGS_VAL 0x7770
281#define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
282#define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
283#define NVREG_WAKEUPFLAGS_D3SHIFT 12
284#define NVREG_WAKEUPFLAGS_D2SHIFT 8
285#define NVREG_WAKEUPFLAGS_D1SHIFT 4
286#define NVREG_WAKEUPFLAGS_D0SHIFT 0
287#define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
288#define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
289#define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
290#define NVREG_WAKEUPFLAGS_ENABLE 0x1111
291
292 NvRegPatternCRC = 0x204,
293 NvRegPatternMask = 0x208,
294 NvRegPowerCap = 0x268,
295#define NVREG_POWERCAP_D3SUPP (1<<30)
296#define NVREG_POWERCAP_D2SUPP (1<<26)
297#define NVREG_POWERCAP_D1SUPP (1<<25)
298 NvRegPowerState = 0x26c,
299#define NVREG_POWERSTATE_POWEREDUP 0x8000
300#define NVREG_POWERSTATE_VALID 0x0100
301#define NVREG_POWERSTATE_MASK 0x0003
302#define NVREG_POWERSTATE_D0 0x0000
303#define NVREG_POWERSTATE_D1 0x0001
304#define NVREG_POWERSTATE_D2 0x0002
305#define NVREG_POWERSTATE_D3 0x0003
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400306 NvRegTxCnt = 0x280,
307 NvRegTxZeroReXmt = 0x284,
308 NvRegTxOneReXmt = 0x288,
309 NvRegTxManyReXmt = 0x28c,
310 NvRegTxLateCol = 0x290,
311 NvRegTxUnderflow = 0x294,
312 NvRegTxLossCarrier = 0x298,
313 NvRegTxExcessDef = 0x29c,
314 NvRegTxRetryErr = 0x2a0,
315 NvRegRxFrameErr = 0x2a4,
316 NvRegRxExtraByte = 0x2a8,
317 NvRegRxLateCol = 0x2ac,
318 NvRegRxRunt = 0x2b0,
319 NvRegRxFrameTooLong = 0x2b4,
320 NvRegRxOverflow = 0x2b8,
321 NvRegRxFCSErr = 0x2bc,
322 NvRegRxFrameAlignErr = 0x2c0,
323 NvRegRxLenErr = 0x2c4,
324 NvRegRxUnicast = 0x2c8,
325 NvRegRxMulticast = 0x2cc,
326 NvRegRxBroadcast = 0x2d0,
327 NvRegTxDef = 0x2d4,
328 NvRegTxFrame = 0x2d8,
329 NvRegRxCnt = 0x2dc,
330 NvRegTxPause = 0x2e0,
331 NvRegRxPause = 0x2e4,
332 NvRegRxDropFrame = 0x2e8,
Ayaz Abdullaee407b02006-02-04 13:13:17 -0500333 NvRegVlanControl = 0x300,
334#define NVREG_VLANCONTROL_ENABLE 0x2000
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500335 NvRegMSIXMap0 = 0x3e0,
336 NvRegMSIXMap1 = 0x3e4,
337 NvRegMSIXIrqStatus = 0x3f0,
Ayaz Abdulla86a0f042006-04-24 18:41:31 -0400338
339 NvRegPowerState2 = 0x600,
340#define NVREG_POWERSTATE2_POWERUP_MASK 0x0F11
341#define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
Ayaz Abdulla22ae03a2008-07-25 15:31:29 -0400342#define NVREG_POWERSTATE2_PHY_RESET 0x0004
Linus Torvalds1da177e2005-04-16 15:20:36 -0700343};
344
345/* Big endian: should work, but is untested */
346struct ring_desc {
Stephen Hemmingera8bed492006-07-27 18:50:09 -0700347 __le32 buf;
348 __le32 flaglen;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700349};
350
Manfred Spraulee733622005-07-31 18:32:26 +0200351struct ring_desc_ex {
Stephen Hemmingera8bed492006-07-27 18:50:09 -0700352 __le32 bufhigh;
353 __le32 buflow;
354 __le32 txvlan;
355 __le32 flaglen;
Manfred Spraulee733622005-07-31 18:32:26 +0200356};
357
Stephen Hemmingerf82a9352006-07-27 18:50:08 -0700358union ring_type {
Manfred Spraulee733622005-07-31 18:32:26 +0200359 struct ring_desc* orig;
360 struct ring_desc_ex* ex;
Stephen Hemmingerf82a9352006-07-27 18:50:08 -0700361};
Manfred Spraulee733622005-07-31 18:32:26 +0200362
Linus Torvalds1da177e2005-04-16 15:20:36 -0700363#define FLAG_MASK_V1 0xffff0000
364#define FLAG_MASK_V2 0xffffc000
365#define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
366#define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
367
368#define NV_TX_LASTPACKET (1<<16)
369#define NV_TX_RETRYERROR (1<<19)
Ayaz Abdullaa4336862008-04-18 13:50:43 -0700370#define NV_TX_RETRYCOUNT_MASK (0xF<<20)
Manfred Spraulc2dba062005-07-31 18:29:47 +0200371#define NV_TX_FORCED_INTERRUPT (1<<24)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700372#define NV_TX_DEFERRED (1<<26)
373#define NV_TX_CARRIERLOST (1<<27)
374#define NV_TX_LATECOLLISION (1<<28)
375#define NV_TX_UNDERFLOW (1<<29)
376#define NV_TX_ERROR (1<<30)
377#define NV_TX_VALID (1<<31)
378
379#define NV_TX2_LASTPACKET (1<<29)
380#define NV_TX2_RETRYERROR (1<<18)
Ayaz Abdullaa4336862008-04-18 13:50:43 -0700381#define NV_TX2_RETRYCOUNT_MASK (0xF<<19)
Manfred Spraulc2dba062005-07-31 18:29:47 +0200382#define NV_TX2_FORCED_INTERRUPT (1<<30)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700383#define NV_TX2_DEFERRED (1<<25)
384#define NV_TX2_CARRIERLOST (1<<26)
385#define NV_TX2_LATECOLLISION (1<<27)
386#define NV_TX2_UNDERFLOW (1<<28)
387/* error and valid are the same for both */
388#define NV_TX2_ERROR (1<<30)
389#define NV_TX2_VALID (1<<31)
Ayaz Abdullaac9c1892005-10-26 00:51:24 -0400390#define NV_TX2_TSO (1<<28)
391#define NV_TX2_TSO_SHIFT 14
Ayaz Abdullafa454592006-01-05 22:45:45 -0800392#define NV_TX2_TSO_MAX_SHIFT 14
393#define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT)
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -0400394#define NV_TX2_CHECKSUM_L3 (1<<27)
395#define NV_TX2_CHECKSUM_L4 (1<<26)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700396
Ayaz Abdullaee407b02006-02-04 13:13:17 -0500397#define NV_TX3_VLAN_TAG_PRESENT (1<<18)
398
Linus Torvalds1da177e2005-04-16 15:20:36 -0700399#define NV_RX_DESCRIPTORVALID (1<<16)
400#define NV_RX_MISSEDFRAME (1<<17)
401#define NV_RX_SUBSTRACT1 (1<<18)
402#define NV_RX_ERROR1 (1<<23)
403#define NV_RX_ERROR2 (1<<24)
404#define NV_RX_ERROR3 (1<<25)
405#define NV_RX_ERROR4 (1<<26)
406#define NV_RX_CRCERR (1<<27)
407#define NV_RX_OVERFLOW (1<<28)
408#define NV_RX_FRAMINGERR (1<<29)
409#define NV_RX_ERROR (1<<30)
410#define NV_RX_AVAIL (1<<31)
Ayaz Abdulla1ef68412008-08-06 12:11:03 -0400411#define NV_RX_ERROR_MASK (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700412
413#define NV_RX2_CHECKSUMMASK (0x1C000000)
Ayaz Abdullabfaffe82008-01-13 16:02:55 -0500414#define NV_RX2_CHECKSUM_IP (0x10000000)
415#define NV_RX2_CHECKSUM_IP_TCP (0x14000000)
416#define NV_RX2_CHECKSUM_IP_UDP (0x18000000)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700417#define NV_RX2_DESCRIPTORVALID (1<<29)
418#define NV_RX2_SUBSTRACT1 (1<<25)
419#define NV_RX2_ERROR1 (1<<18)
420#define NV_RX2_ERROR2 (1<<19)
421#define NV_RX2_ERROR3 (1<<20)
422#define NV_RX2_ERROR4 (1<<21)
423#define NV_RX2_CRCERR (1<<22)
424#define NV_RX2_OVERFLOW (1<<23)
425#define NV_RX2_FRAMINGERR (1<<24)
426/* error and avail are the same for both */
427#define NV_RX2_ERROR (1<<30)
428#define NV_RX2_AVAIL (1<<31)
Ayaz Abdulla1ef68412008-08-06 12:11:03 -0400429#define NV_RX2_ERROR_MASK (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700430
Ayaz Abdullaee407b02006-02-04 13:13:17 -0500431#define NV_RX3_VLAN_TAG_PRESENT (1<<16)
432#define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
433
Linus Torvalds1da177e2005-04-16 15:20:36 -0700434/* Miscelaneous hardware related defines: */
Ayaz Abdulla86a0f042006-04-24 18:41:31 -0400435#define NV_PCI_REGSZ_VER1 0x270
Ayaz Abdulla57fff692007-01-23 12:27:00 -0500436#define NV_PCI_REGSZ_VER2 0x2d4
437#define NV_PCI_REGSZ_VER3 0x604
Tobias Diedrich1a1ca862008-05-18 15:03:44 +0200438#define NV_PCI_REGSZ_MAX 0x604
Linus Torvalds1da177e2005-04-16 15:20:36 -0700439
440/* various timeout delays: all in usec */
441#define NV_TXRX_RESET_DELAY 4
442#define NV_TXSTOP_DELAY1 10
443#define NV_TXSTOP_DELAY1MAX 500000
444#define NV_TXSTOP_DELAY2 100
445#define NV_RXSTOP_DELAY1 10
446#define NV_RXSTOP_DELAY1MAX 500000
447#define NV_RXSTOP_DELAY2 100
448#define NV_SETUP5_DELAY 5
449#define NV_SETUP5_DELAYMAX 50000
450#define NV_POWERUP_DELAY 5
451#define NV_POWERUP_DELAYMAX 5000
452#define NV_MIIBUSY_DELAY 50
453#define NV_MIIPHY_DELAY 10
454#define NV_MIIPHY_DELAYMAX 10000
Ayaz Abdulla86a0f042006-04-24 18:41:31 -0400455#define NV_MAC_RESET_DELAY 64
Linus Torvalds1da177e2005-04-16 15:20:36 -0700456
457#define NV_WAKEUPPATTERNS 5
458#define NV_WAKEUPMASKENTRIES 4
459
460/* General driver defaults */
461#define NV_WATCHDOG_TIMEO (5*HZ)
462
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -0400463#define RX_RING_DEFAULT 128
464#define TX_RING_DEFAULT 256
465#define RX_RING_MIN 128
466#define TX_RING_MIN 64
467#define RING_MAX_DESC_VER_1 1024
468#define RING_MAX_DESC_VER_2_3 16384
Linus Torvalds1da177e2005-04-16 15:20:36 -0700469
470/* rx/tx mac addr + type + vlan + align + slack*/
Manfred Sprauld81c0982005-07-31 18:20:30 +0200471#define NV_RX_HEADERS (64)
472/* even more slack. */
473#define NV_RX_ALLOC_PAD (64)
474
475/* maximum mtu size */
476#define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
477#define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700478
479#define OOM_REFILL (1+HZ/20)
480#define POLL_WAIT (1+HZ/100)
481#define LINK_TIMEOUT (3*HZ)
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400482#define STATS_INTERVAL (10*HZ)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700483
Jeff Garzikf3b197a2006-05-26 21:39:03 -0400484/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700485 * desc_ver values:
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -0400486 * The nic supports three different descriptor types:
487 * - DESC_VER_1: Original
488 * - DESC_VER_2: support for jumbo frames.
489 * - DESC_VER_3: 64-bit format.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700490 */
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -0400491#define DESC_VER_1 1
492#define DESC_VER_2 2
493#define DESC_VER_3 3
Linus Torvalds1da177e2005-04-16 15:20:36 -0700494
495/* PHY defines */
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400496#define PHY_OUI_MARVELL 0x5043
497#define PHY_OUI_CICADA 0x03f1
498#define PHY_OUI_VITESSE 0x01c1
499#define PHY_OUI_REALTEK 0x0732
500#define PHY_OUI_REALTEK2 0x0020
Linus Torvalds1da177e2005-04-16 15:20:36 -0700501#define PHYID1_OUI_MASK 0x03ff
502#define PHYID1_OUI_SHFT 6
503#define PHYID2_OUI_MASK 0xfc00
504#define PHYID2_OUI_SHFT 10
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -0400505#define PHYID2_MODEL_MASK 0x03f0
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400506#define PHY_MODEL_REALTEK_8211 0x0110
507#define PHY_REV_MASK 0x0001
508#define PHY_REV_REALTEK_8211B 0x0000
509#define PHY_REV_REALTEK_8211C 0x0001
510#define PHY_MODEL_REALTEK_8201 0x0200
511#define PHY_MODEL_MARVELL_E3016 0x0220
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -0400512#define PHY_MARVELL_E3016_INITMASK 0x0300
Ayaz Abdulla14a67f32007-07-15 06:50:28 -0400513#define PHY_CICADA_INIT1 0x0f000
514#define PHY_CICADA_INIT2 0x0e00
515#define PHY_CICADA_INIT3 0x01000
516#define PHY_CICADA_INIT4 0x0200
517#define PHY_CICADA_INIT5 0x0004
518#define PHY_CICADA_INIT6 0x02000
Ayaz Abdullad215d8a2007-07-15 06:50:53 -0400519#define PHY_VITESSE_INIT_REG1 0x1f
520#define PHY_VITESSE_INIT_REG2 0x10
521#define PHY_VITESSE_INIT_REG3 0x11
522#define PHY_VITESSE_INIT_REG4 0x12
523#define PHY_VITESSE_INIT_MSK1 0xc
524#define PHY_VITESSE_INIT_MSK2 0x0180
525#define PHY_VITESSE_INIT1 0x52b5
526#define PHY_VITESSE_INIT2 0xaf8a
527#define PHY_VITESSE_INIT3 0x8
528#define PHY_VITESSE_INIT4 0x8f8a
529#define PHY_VITESSE_INIT5 0xaf86
530#define PHY_VITESSE_INIT6 0x8f86
531#define PHY_VITESSE_INIT7 0xaf82
532#define PHY_VITESSE_INIT8 0x0100
533#define PHY_VITESSE_INIT9 0x8f82
534#define PHY_VITESSE_INIT10 0x0
Ayaz Abdullac5e3ae82007-07-15 06:51:03 -0400535#define PHY_REALTEK_INIT_REG1 0x1f
536#define PHY_REALTEK_INIT_REG2 0x19
537#define PHY_REALTEK_INIT_REG3 0x13
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400538#define PHY_REALTEK_INIT_REG4 0x14
539#define PHY_REALTEK_INIT_REG5 0x18
540#define PHY_REALTEK_INIT_REG6 0x11
Ayaz Abdulla22ae03a2008-07-25 15:31:29 -0400541#define PHY_REALTEK_INIT_REG7 0x01
Ayaz Abdullac5e3ae82007-07-15 06:51:03 -0400542#define PHY_REALTEK_INIT1 0x0000
543#define PHY_REALTEK_INIT2 0x8e00
544#define PHY_REALTEK_INIT3 0x0001
545#define PHY_REALTEK_INIT4 0xad17
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400546#define PHY_REALTEK_INIT5 0xfb54
547#define PHY_REALTEK_INIT6 0xf5c7
548#define PHY_REALTEK_INIT7 0x1000
549#define PHY_REALTEK_INIT8 0x0003
Ayaz Abdulla22ae03a2008-07-25 15:31:29 -0400550#define PHY_REALTEK_INIT9 0x0008
551#define PHY_REALTEK_INIT10 0x0005
552#define PHY_REALTEK_INIT11 0x0200
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400553#define PHY_REALTEK_INIT_MSK1 0x0003
Ayaz Abdullad215d8a2007-07-15 06:50:53 -0400554
Linus Torvalds1da177e2005-04-16 15:20:36 -0700555#define PHY_GIGABIT 0x0100
556
557#define PHY_TIMEOUT 0x1
558#define PHY_ERROR 0x2
559
560#define PHY_100 0x1
561#define PHY_1000 0x2
562#define PHY_HALF 0x100
563
Ayaz Abdullaeb91f612006-05-24 18:13:19 -0400564#define NV_PAUSEFRAME_RX_CAPABLE 0x0001
565#define NV_PAUSEFRAME_TX_CAPABLE 0x0002
566#define NV_PAUSEFRAME_RX_ENABLE 0x0004
567#define NV_PAUSEFRAME_TX_ENABLE 0x0008
Ayaz Abdullab6d07732006-06-10 22:47:42 -0400568#define NV_PAUSEFRAME_RX_REQ 0x0010
569#define NV_PAUSEFRAME_TX_REQ 0x0020
570#define NV_PAUSEFRAME_AUTONEG 0x0040
Linus Torvalds1da177e2005-04-16 15:20:36 -0700571
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500572/* MSI/MSI-X defines */
573#define NV_MSI_X_MAX_VECTORS 8
574#define NV_MSI_X_VECTORS_MASK 0x000f
575#define NV_MSI_CAPABLE 0x0010
576#define NV_MSI_X_CAPABLE 0x0020
577#define NV_MSI_ENABLED 0x0040
578#define NV_MSI_X_ENABLED 0x0080
579
580#define NV_MSI_X_VECTOR_ALL 0x0
581#define NV_MSI_X_VECTOR_RX 0x0
582#define NV_MSI_X_VECTOR_TX 0x1
583#define NV_MSI_X_VECTOR_OTHER 0x2
Linus Torvalds1da177e2005-04-16 15:20:36 -0700584
Ayaz Abdullab2976d22008-02-04 15:13:59 -0500585#define NV_RESTART_TX 0x1
586#define NV_RESTART_RX 0x2
587
Ayaz Abdulla3b446c32008-03-10 14:58:21 -0500588#define NV_TX_LIMIT_COUNT 16
589
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400590/* statistics */
591struct nv_ethtool_str {
592 char name[ETH_GSTRING_LEN];
593};
594
595static const struct nv_ethtool_str nv_estats_str[] = {
596 { "tx_bytes" },
597 { "tx_zero_rexmt" },
598 { "tx_one_rexmt" },
599 { "tx_many_rexmt" },
600 { "tx_late_collision" },
601 { "tx_fifo_errors" },
602 { "tx_carrier_errors" },
603 { "tx_excess_deferral" },
604 { "tx_retry_error" },
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400605 { "rx_frame_error" },
606 { "rx_extra_byte" },
607 { "rx_late_collision" },
608 { "rx_runt" },
609 { "rx_frame_too_long" },
610 { "rx_over_errors" },
611 { "rx_crc_errors" },
612 { "rx_frame_align_error" },
613 { "rx_length_error" },
614 { "rx_unicast" },
615 { "rx_multicast" },
616 { "rx_broadcast" },
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400617 { "rx_packets" },
Ayaz Abdulla57fff692007-01-23 12:27:00 -0500618 { "rx_errors_total" },
619 { "tx_errors_total" },
620
621 /* version 2 stats */
622 { "tx_deferral" },
623 { "tx_packets" },
624 { "rx_bytes" },
625 { "tx_pause" },
626 { "rx_pause" },
Ayaz Abdulla9c662432008-08-06 12:11:42 -0400627 { "rx_drop_frame" },
628
629 /* version 3 stats */
630 { "tx_unicast" },
631 { "tx_multicast" },
632 { "tx_broadcast" }
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400633};
634
635struct nv_ethtool_stats {
636 u64 tx_bytes;
637 u64 tx_zero_rexmt;
638 u64 tx_one_rexmt;
639 u64 tx_many_rexmt;
640 u64 tx_late_collision;
641 u64 tx_fifo_errors;
642 u64 tx_carrier_errors;
643 u64 tx_excess_deferral;
644 u64 tx_retry_error;
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400645 u64 rx_frame_error;
646 u64 rx_extra_byte;
647 u64 rx_late_collision;
648 u64 rx_runt;
649 u64 rx_frame_too_long;
650 u64 rx_over_errors;
651 u64 rx_crc_errors;
652 u64 rx_frame_align_error;
653 u64 rx_length_error;
654 u64 rx_unicast;
655 u64 rx_multicast;
656 u64 rx_broadcast;
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400657 u64 rx_packets;
658 u64 rx_errors_total;
Ayaz Abdulla57fff692007-01-23 12:27:00 -0500659 u64 tx_errors_total;
660
661 /* version 2 stats */
662 u64 tx_deferral;
663 u64 tx_packets;
664 u64 rx_bytes;
665 u64 tx_pause;
666 u64 rx_pause;
667 u64 rx_drop_frame;
Ayaz Abdulla9c662432008-08-06 12:11:42 -0400668
669 /* version 3 stats */
670 u64 tx_unicast;
671 u64 tx_multicast;
672 u64 tx_broadcast;
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400673};
674
Ayaz Abdulla9c662432008-08-06 12:11:42 -0400675#define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
676#define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3)
Ayaz Abdulla57fff692007-01-23 12:27:00 -0500677#define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
678
Ayaz Abdulla9589c772006-06-10 22:48:13 -0400679/* diagnostics */
680#define NV_TEST_COUNT_BASE 3
681#define NV_TEST_COUNT_EXTENDED 4
682
683static const struct nv_ethtool_str nv_etests_str[] = {
684 { "link (online/offline)" },
685 { "register (offline) " },
686 { "interrupt (offline) " },
687 { "loopback (offline) " }
688};
689
690struct register_test {
Al Viro5bb7ea22007-12-09 16:06:41 +0000691 __u32 reg;
692 __u32 mask;
Ayaz Abdulla9589c772006-06-10 22:48:13 -0400693};
694
695static const struct register_test nv_registers_test[] = {
696 { NvRegUnknownSetupReg6, 0x01 },
697 { NvRegMisc1, 0x03c },
698 { NvRegOffloadConfig, 0x03ff },
699 { NvRegMulticastAddrA, 0xffffffff },
Ayaz Abdulla95d161c2006-07-06 16:46:25 -0400700 { NvRegTxWatermark, 0x0ff },
Ayaz Abdulla9589c772006-06-10 22:48:13 -0400701 { NvRegWakeUpFlags, 0x07777 },
702 { 0,0 }
703};
704
Ayaz Abdulla761fcd92007-01-09 13:30:07 -0500705struct nv_skb_map {
706 struct sk_buff *skb;
707 dma_addr_t dma;
708 unsigned int dma_len;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -0500709 struct ring_desc_ex *first_tx_desc;
710 struct nv_skb_map *next_tx_ctx;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -0500711};
712
Linus Torvalds1da177e2005-04-16 15:20:36 -0700713/*
714 * SMP locking:
715 * All hardware access under dev->priv->lock, except the performance
716 * critical parts:
717 * - rx is (pseudo-) lockless: it relies on the single-threading provided
718 * by the arch code for interrupts.
Herbert Xu932ff272006-06-09 12:20:56 -0700719 * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
Linus Torvalds1da177e2005-04-16 15:20:36 -0700720 * needs dev->priv->lock :-(
Herbert Xu932ff272006-06-09 12:20:56 -0700721 * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700722 */
723
724/* in dev: base, irq */
725struct fe_priv {
726 spinlock_t lock;
727
Stephen Hemmingerbea33482007-10-03 16:41:36 -0700728 struct net_device *dev;
729 struct napi_struct napi;
730
Linus Torvalds1da177e2005-04-16 15:20:36 -0700731 /* General data:
732 * Locking: spin_lock(&np->lock); */
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400733 struct nv_ethtool_stats estats;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700734 int in_shutdown;
735 u32 linkspeed;
736 int duplex;
737 int autoneg;
738 int fixed_mode;
739 int phyaddr;
740 int wolenabled;
741 unsigned int phy_oui;
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -0400742 unsigned int phy_model;
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400743 unsigned int phy_rev;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700744 u16 gigabit;
Ayaz Abdulla9589c772006-06-10 22:48:13 -0400745 int intr_test;
Ayaz Abdullac5cf9102006-10-30 17:32:01 -0500746 int recover_error;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700747
748 /* General data: RO fields */
749 dma_addr_t ring_addr;
750 struct pci_dev *pci_dev;
751 u32 orig_mac[2];
752 u32 irqmask;
753 u32 desc_ver;
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -0400754 u32 txrxctl_bits;
Ayaz Abdullaee407b02006-02-04 13:13:17 -0500755 u32 vlanctl_bits;
Ayaz Abdulla86a0f042006-04-24 18:41:31 -0400756 u32 driver_data;
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400757 u32 device_id;
Ayaz Abdulla86a0f042006-04-24 18:41:31 -0400758 u32 register_size;
Ayaz Abdullaf2ad2d92006-08-24 17:35:41 -0400759 int rx_csum;
Ayaz Abdulla7e680c22006-10-30 17:31:51 -0500760 u32 mac_in_use;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700761
762 void __iomem *base;
763
764 /* rx specific fields.
765 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
766 */
Ayaz Abdulla761fcd92007-01-09 13:30:07 -0500767 union ring_type get_rx, put_rx, first_rx, last_rx;
768 struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
769 struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
770 struct nv_skb_map *rx_skb;
771
Stephen Hemmingerf82a9352006-07-27 18:50:08 -0700772 union ring_type rx_ring;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700773 unsigned int rx_buf_sz;
Manfred Sprauld81c0982005-07-31 18:20:30 +0200774 unsigned int pkt_limit;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700775 struct timer_list oom_kick;
776 struct timer_list nic_poll;
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400777 struct timer_list stats_poll;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500778 u32 nic_poll_irq;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -0400779 int rx_ring_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700780
781 /* media detection workaround.
782 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
783 */
784 int need_linktimer;
785 unsigned long link_timeout;
786 /*
787 * tx specific fields.
788 */
Ayaz Abdulla761fcd92007-01-09 13:30:07 -0500789 union ring_type get_tx, put_tx, first_tx, last_tx;
790 struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
791 struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
792 struct nv_skb_map *tx_skb;
793
Stephen Hemmingerf82a9352006-07-27 18:50:08 -0700794 union ring_type tx_ring;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700795 u32 tx_flags;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -0400796 int tx_ring_size;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -0500797 int tx_limit;
798 u32 tx_pkts_in_progress;
799 struct nv_skb_map *tx_change_owner;
800 struct nv_skb_map *tx_end_flip;
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -0500801 int tx_stop;
Ayaz Abdullaee407b02006-02-04 13:13:17 -0500802
803 /* vlan fields */
804 struct vlan_group *vlangrp;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500805
806 /* msi/msi-x fields */
807 u32 msi_flags;
808 struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
Ayaz Abdullaeb91f612006-05-24 18:13:19 -0400809
810 /* flow control */
811 u32 pause_flags;
Tobias Diedrich1a1ca862008-05-18 15:03:44 +0200812
813 /* power saved state */
814 u32 saved_config_space[NV_PCI_REGSZ_MAX/4];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700815};
816
817/*
818 * Maximum number of loops until we assume that a bit in the irq mask
819 * is stuck. Overridable with module param.
820 */
821static int max_interrupt_work = 5;
822
Ayaz Abdullaa971c322005-11-11 08:30:38 -0500823/*
824 * Optimization can be either throuput mode or cpu mode
Jeff Garzikf3b197a2006-05-26 21:39:03 -0400825 *
Ayaz Abdullaa971c322005-11-11 08:30:38 -0500826 * Throughput Mode: Every tx and rx packet will generate an interrupt.
827 * CPU Mode: Interrupts are controlled by a timer.
828 */
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -0400829enum {
830 NV_OPTIMIZATION_MODE_THROUGHPUT,
831 NV_OPTIMIZATION_MODE_CPU
832};
Ayaz Abdullaa971c322005-11-11 08:30:38 -0500833static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
834
835/*
836 * Poll interval for timer irq
837 *
838 * This interval determines how frequent an interrupt is generated.
839 * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
840 * Min = 0, and Max = 65535
841 */
842static int poll_interval = -1;
843
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500844/*
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -0400845 * MSI interrupts
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500846 */
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -0400847enum {
848 NV_MSI_INT_DISABLED,
849 NV_MSI_INT_ENABLED
850};
851static int msi = NV_MSI_INT_ENABLED;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500852
853/*
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -0400854 * MSIX interrupts
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500855 */
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -0400856enum {
857 NV_MSIX_INT_DISABLED,
858 NV_MSIX_INT_ENABLED
859};
Ayaz Abdullacaf96462007-02-20 03:34:40 -0500860static int msix = NV_MSIX_INT_DISABLED;
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -0400861
862/*
863 * DMA 64bit
864 */
865enum {
866 NV_DMA_64BIT_DISABLED,
867 NV_DMA_64BIT_ENABLED
868};
869static int dma_64bit = NV_DMA_64BIT_ENABLED;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500870
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400871/*
872 * Crossover Detection
873 * Realtek 8201 phy + some OEM boards do not work properly.
874 */
875enum {
876 NV_CROSSOVER_DETECTION_DISABLED,
877 NV_CROSSOVER_DETECTION_ENABLED
878};
879static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED;
880
Linus Torvalds1da177e2005-04-16 15:20:36 -0700881static inline struct fe_priv *get_nvpriv(struct net_device *dev)
882{
883 return netdev_priv(dev);
884}
885
886static inline u8 __iomem *get_hwbase(struct net_device *dev)
887{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -0400888 return ((struct fe_priv *)netdev_priv(dev))->base;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700889}
890
891static inline void pci_push(u8 __iomem *base)
892{
893 /* force out pending posted writes */
894 readl(base);
895}
896
897static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
898{
Stephen Hemmingerf82a9352006-07-27 18:50:08 -0700899 return le32_to_cpu(prd->flaglen)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700900 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
901}
902
Manfred Spraulee733622005-07-31 18:32:26 +0200903static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
904{
Stephen Hemmingerf82a9352006-07-27 18:50:08 -0700905 return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
Manfred Spraulee733622005-07-31 18:32:26 +0200906}
907
Jeff Garzik36b30ea2007-10-16 01:40:30 -0400908static bool nv_optimized(struct fe_priv *np)
909{
910 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
911 return false;
912 return true;
913}
914
Linus Torvalds1da177e2005-04-16 15:20:36 -0700915static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
916 int delay, int delaymax, const char *msg)
917{
918 u8 __iomem *base = get_hwbase(dev);
919
920 pci_push(base);
921 do {
922 udelay(delay);
923 delaymax -= delay;
924 if (delaymax < 0) {
925 if (msg)
926 printk(msg);
927 return 1;
928 }
929 } while ((readl(base + offset) & mask) != target);
930 return 0;
931}
932
Ayaz Abdulla0832b252006-02-04 13:13:26 -0500933#define NV_SETUP_RX_RING 0x01
934#define NV_SETUP_TX_RING 0x02
935
Al Viro5bb7ea22007-12-09 16:06:41 +0000936static inline u32 dma_low(dma_addr_t addr)
937{
938 return addr;
939}
940
941static inline u32 dma_high(dma_addr_t addr)
942{
943 return addr>>31>>1; /* 0 if 32bit, shift down by 32 if 64bit */
944}
945
Ayaz Abdulla0832b252006-02-04 13:13:26 -0500946static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
947{
948 struct fe_priv *np = get_nvpriv(dev);
949 u8 __iomem *base = get_hwbase(dev);
950
Jeff Garzik36b30ea2007-10-16 01:40:30 -0400951 if (!nv_optimized(np)) {
Ayaz Abdulla0832b252006-02-04 13:13:26 -0500952 if (rxtx_flags & NV_SETUP_RX_RING) {
Al Viro5bb7ea22007-12-09 16:06:41 +0000953 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
Ayaz Abdulla0832b252006-02-04 13:13:26 -0500954 }
955 if (rxtx_flags & NV_SETUP_TX_RING) {
Al Viro5bb7ea22007-12-09 16:06:41 +0000956 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
Ayaz Abdulla0832b252006-02-04 13:13:26 -0500957 }
958 } else {
959 if (rxtx_flags & NV_SETUP_RX_RING) {
Al Viro5bb7ea22007-12-09 16:06:41 +0000960 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
961 writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
Ayaz Abdulla0832b252006-02-04 13:13:26 -0500962 }
963 if (rxtx_flags & NV_SETUP_TX_RING) {
Al Viro5bb7ea22007-12-09 16:06:41 +0000964 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
965 writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
Ayaz Abdulla0832b252006-02-04 13:13:26 -0500966 }
967 }
968}
969
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -0400970static void free_rings(struct net_device *dev)
971{
972 struct fe_priv *np = get_nvpriv(dev);
973
Jeff Garzik36b30ea2007-10-16 01:40:30 -0400974 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -0700975 if (np->rx_ring.orig)
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -0400976 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
977 np->rx_ring.orig, np->ring_addr);
978 } else {
979 if (np->rx_ring.ex)
980 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
981 np->rx_ring.ex, np->ring_addr);
982 }
Ayaz Abdulla761fcd92007-01-09 13:30:07 -0500983 if (np->rx_skb)
984 kfree(np->rx_skb);
985 if (np->tx_skb)
986 kfree(np->tx_skb);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -0400987}
988
Ayaz Abdulla84b39322006-05-20 14:59:48 -0700989static int using_multi_irqs(struct net_device *dev)
990{
991 struct fe_priv *np = get_nvpriv(dev);
992
993 if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
994 ((np->msi_flags & NV_MSI_X_ENABLED) &&
995 ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
996 return 0;
997 else
998 return 1;
999}
1000
1001static void nv_enable_irq(struct net_device *dev)
1002{
1003 struct fe_priv *np = get_nvpriv(dev);
1004
1005 if (!using_multi_irqs(dev)) {
1006 if (np->msi_flags & NV_MSI_X_ENABLED)
1007 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1008 else
Manfred Spraula7475902007-10-17 21:52:33 +02001009 enable_irq(np->pci_dev->irq);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07001010 } else {
1011 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1012 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1013 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1014 }
1015}
1016
1017static void nv_disable_irq(struct net_device *dev)
1018{
1019 struct fe_priv *np = get_nvpriv(dev);
1020
1021 if (!using_multi_irqs(dev)) {
1022 if (np->msi_flags & NV_MSI_X_ENABLED)
1023 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1024 else
Manfred Spraula7475902007-10-17 21:52:33 +02001025 disable_irq(np->pci_dev->irq);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07001026 } else {
1027 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1028 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1029 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1030 }
1031}
1032
1033/* In MSIX mode, a write to irqmask behaves as XOR */
1034static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
1035{
1036 u8 __iomem *base = get_hwbase(dev);
1037
1038 writel(mask, base + NvRegIrqMask);
1039}
1040
1041static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
1042{
1043 struct fe_priv *np = get_nvpriv(dev);
1044 u8 __iomem *base = get_hwbase(dev);
1045
1046 if (np->msi_flags & NV_MSI_X_ENABLED) {
1047 writel(mask, base + NvRegIrqMask);
1048 } else {
1049 if (np->msi_flags & NV_MSI_ENABLED)
1050 writel(0, base + NvRegMSIIrqMask);
1051 writel(0, base + NvRegIrqMask);
1052 }
1053}
1054
Linus Torvalds1da177e2005-04-16 15:20:36 -07001055#define MII_READ (-1)
1056/* mii_rw: read/write a register on the PHY.
1057 *
1058 * Caller must guarantee serialization
1059 */
1060static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1061{
1062 u8 __iomem *base = get_hwbase(dev);
1063 u32 reg;
1064 int retval;
1065
Ayaz Abdullaeb798422008-02-04 15:14:04 -05001066 writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001067
1068 reg = readl(base + NvRegMIIControl);
1069 if (reg & NVREG_MIICTL_INUSE) {
1070 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1071 udelay(NV_MIIBUSY_DELAY);
1072 }
1073
1074 reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1075 if (value != MII_READ) {
1076 writel(value, base + NvRegMIIData);
1077 reg |= NVREG_MIICTL_WRITE;
1078 }
1079 writel(reg, base + NvRegMIIControl);
1080
1081 if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1082 NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
1083 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
1084 dev->name, miireg, addr);
1085 retval = -1;
1086 } else if (value != MII_READ) {
1087 /* it was a write operation - fewer failures are detectable */
1088 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1089 dev->name, value, miireg, addr);
1090 retval = 0;
1091 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1092 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
1093 dev->name, miireg, addr);
1094 retval = -1;
1095 } else {
1096 retval = readl(base + NvRegMIIData);
1097 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1098 dev->name, miireg, addr, retval);
1099 }
1100
1101 return retval;
1102}
1103
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04001104static int phy_reset(struct net_device *dev, u32 bmcr_setup)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001105{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001106 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001107 u32 miicontrol;
1108 unsigned int tries = 0;
1109
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04001110 miicontrol = BMCR_RESET | bmcr_setup;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001111 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
1112 return -1;
1113 }
1114
1115 /* wait for 500ms */
1116 msleep(500);
1117
1118 /* must wait till reset is deasserted */
1119 while (miicontrol & BMCR_RESET) {
1120 msleep(10);
1121 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1122 /* FIXME: 100 tries seem excessive */
1123 if (tries++ > 100)
1124 return -1;
1125 }
1126 return 0;
1127}
1128
1129static int phy_init(struct net_device *dev)
1130{
1131 struct fe_priv *np = get_nvpriv(dev);
1132 u8 __iomem *base = get_hwbase(dev);
1133 u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1134
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04001135 /* phy errata for E3016 phy */
1136 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1137 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1138 reg &= ~PHY_MARVELL_E3016_INITMASK;
1139 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1140 printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
1141 return PHY_ERROR;
1142 }
1143 }
Ayaz Abdullac5e3ae82007-07-15 06:51:03 -04001144 if (np->phy_oui == PHY_OUI_REALTEK) {
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04001145 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1146 np->phy_rev == PHY_REV_REALTEK_8211B) {
1147 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1148 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1149 return PHY_ERROR;
1150 }
1151 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1152 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1153 return PHY_ERROR;
1154 }
1155 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1156 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1157 return PHY_ERROR;
1158 }
1159 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1160 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1161 return PHY_ERROR;
1162 }
1163 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1164 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1165 return PHY_ERROR;
1166 }
1167 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1168 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1169 return PHY_ERROR;
1170 }
1171 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1172 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1173 return PHY_ERROR;
1174 }
Ayaz Abdullac5e3ae82007-07-15 06:51:03 -04001175 }
Ayaz Abdulla22ae03a2008-07-25 15:31:29 -04001176 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1177 np->phy_rev == PHY_REV_REALTEK_8211C) {
1178 u32 powerstate = readl(base + NvRegPowerState2);
1179
1180 /* need to perform hw phy reset */
1181 powerstate |= NVREG_POWERSTATE2_PHY_RESET;
1182 writel(powerstate, base + NvRegPowerState2);
1183 msleep(25);
1184
1185 powerstate &= ~NVREG_POWERSTATE2_PHY_RESET;
1186 writel(powerstate, base + NvRegPowerState2);
1187 msleep(25);
1188
1189 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1190 reg |= PHY_REALTEK_INIT9;
1191 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg)) {
1192 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1193 return PHY_ERROR;
1194 }
1195 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10)) {
1196 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1197 return PHY_ERROR;
1198 }
1199 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
1200 if (!(reg & PHY_REALTEK_INIT11)) {
1201 reg |= PHY_REALTEK_INIT11;
1202 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg)) {
1203 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1204 return PHY_ERROR;
1205 }
1206 }
1207 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1208 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1209 return PHY_ERROR;
1210 }
1211 }
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04001212 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1213 if (np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_32 ||
1214 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_33 ||
1215 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_34 ||
1216 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_35 ||
1217 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_36 ||
1218 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_37 ||
1219 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_38 ||
1220 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_39) {
1221 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1222 phy_reserved |= PHY_REALTEK_INIT7;
1223 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1224 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1225 return PHY_ERROR;
1226 }
1227 }
Ayaz Abdullac5e3ae82007-07-15 06:51:03 -04001228 }
1229 }
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04001230
Linus Torvalds1da177e2005-04-16 15:20:36 -07001231 /* set advertise register */
1232 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04001233 reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001234 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1235 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1236 return PHY_ERROR;
1237 }
1238
1239 /* get phy interface type */
1240 phyinterface = readl(base + NvRegPhyInterface);
1241
1242 /* see if gigabit phy */
1243 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1244 if (mii_status & PHY_GIGABIT) {
1245 np->gigabit = PHY_GIGABIT;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04001246 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001247 mii_control_1000 &= ~ADVERTISE_1000HALF;
1248 if (phyinterface & PHY_RGMII)
1249 mii_control_1000 |= ADVERTISE_1000FULL;
1250 else
1251 mii_control_1000 &= ~ADVERTISE_1000FULL;
1252
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04001253 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001254 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1255 return PHY_ERROR;
1256 }
1257 }
1258 else
1259 np->gigabit = 0;
1260
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04001261 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1262 mii_control |= BMCR_ANENABLE;
1263
Ayaz Abdulla22ae03a2008-07-25 15:31:29 -04001264 if (np->phy_oui == PHY_OUI_REALTEK &&
1265 np->phy_model == PHY_MODEL_REALTEK_8211 &&
1266 np->phy_rev == PHY_REV_REALTEK_8211C) {
1267 /* start autoneg since we already performed hw reset above */
1268 mii_control |= BMCR_ANRESTART;
1269 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1270 printk(KERN_INFO "%s: phy init failed\n", pci_name(np->pci_dev));
1271 return PHY_ERROR;
1272 }
1273 } else {
1274 /* reset the phy
1275 * (certain phys need bmcr to be setup with reset)
1276 */
1277 if (phy_reset(dev, mii_control)) {
1278 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1279 return PHY_ERROR;
1280 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001281 }
1282
1283 /* phy vendor specific configuration */
1284 if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
1285 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
Ayaz Abdulla14a67f32007-07-15 06:50:28 -04001286 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1287 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001288 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1289 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1290 return PHY_ERROR;
1291 }
1292 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
Ayaz Abdulla14a67f32007-07-15 06:50:28 -04001293 phy_reserved |= PHY_CICADA_INIT5;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001294 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1295 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1296 return PHY_ERROR;
1297 }
1298 }
1299 if (np->phy_oui == PHY_OUI_CICADA) {
1300 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
Ayaz Abdulla14a67f32007-07-15 06:50:28 -04001301 phy_reserved |= PHY_CICADA_INIT6;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001302 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1303 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1304 return PHY_ERROR;
1305 }
1306 }
Ayaz Abdullad215d8a2007-07-15 06:50:53 -04001307 if (np->phy_oui == PHY_OUI_VITESSE) {
1308 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) {
1309 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1310 return PHY_ERROR;
1311 }
1312 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) {
1313 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1314 return PHY_ERROR;
1315 }
1316 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1317 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1318 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1319 return PHY_ERROR;
1320 }
1321 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1322 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1323 phy_reserved |= PHY_VITESSE_INIT3;
1324 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1325 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1326 return PHY_ERROR;
1327 }
1328 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) {
1329 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1330 return PHY_ERROR;
1331 }
1332 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) {
1333 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1334 return PHY_ERROR;
1335 }
1336 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1337 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1338 phy_reserved |= PHY_VITESSE_INIT3;
1339 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1340 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1341 return PHY_ERROR;
1342 }
1343 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1344 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1345 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1346 return PHY_ERROR;
1347 }
1348 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) {
1349 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1350 return PHY_ERROR;
1351 }
1352 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) {
1353 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1354 return PHY_ERROR;
1355 }
1356 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1357 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1358 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1359 return PHY_ERROR;
1360 }
1361 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1362 phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1363 phy_reserved |= PHY_VITESSE_INIT8;
1364 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1365 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1366 return PHY_ERROR;
1367 }
1368 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) {
1369 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1370 return PHY_ERROR;
1371 }
1372 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) {
1373 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1374 return PHY_ERROR;
1375 }
1376 }
Ayaz Abdullac5e3ae82007-07-15 06:51:03 -04001377 if (np->phy_oui == PHY_OUI_REALTEK) {
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04001378 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1379 np->phy_rev == PHY_REV_REALTEK_8211B) {
1380 /* reset could have cleared these out, set them back */
1381 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1382 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1383 return PHY_ERROR;
1384 }
1385 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1386 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1387 return PHY_ERROR;
1388 }
1389 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1390 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1391 return PHY_ERROR;
1392 }
1393 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1394 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1395 return PHY_ERROR;
1396 }
1397 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1398 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1399 return PHY_ERROR;
1400 }
1401 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1402 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1403 return PHY_ERROR;
1404 }
1405 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1406 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1407 return PHY_ERROR;
1408 }
Ayaz Abdullac5e3ae82007-07-15 06:51:03 -04001409 }
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04001410 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1411 if (np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_32 ||
1412 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_33 ||
1413 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_34 ||
1414 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_35 ||
1415 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_36 ||
1416 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_37 ||
1417 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_38 ||
1418 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_39) {
1419 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1420 phy_reserved |= PHY_REALTEK_INIT7;
1421 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1422 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1423 return PHY_ERROR;
1424 }
1425 }
1426 if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
1427 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1428 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1429 return PHY_ERROR;
1430 }
1431 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
1432 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
1433 phy_reserved |= PHY_REALTEK_INIT3;
1434 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved)) {
1435 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1436 return PHY_ERROR;
1437 }
1438 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1439 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1440 return PHY_ERROR;
1441 }
1442 }
Ayaz Abdullac5e3ae82007-07-15 06:51:03 -04001443 }
1444 }
1445
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04001446 /* some phys clear out pause advertisment on reset, set it back */
1447 mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001448
1449 /* restart auto negotiation */
1450 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1451 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1452 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1453 return PHY_ERROR;
1454 }
1455
1456 return 0;
1457}
1458
1459static void nv_start_rx(struct net_device *dev)
1460{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001461 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001462 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001463 u32 rx_ctrl = readl(base + NvRegReceiverControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001464
1465 dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1466 /* Already running? Stop it. */
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001467 if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1468 rx_ctrl &= ~NVREG_RCVCTL_START;
1469 writel(rx_ctrl, base + NvRegReceiverControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001470 pci_push(base);
1471 }
1472 writel(np->linkspeed, base + NvRegLinkSpeed);
1473 pci_push(base);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001474 rx_ctrl |= NVREG_RCVCTL_START;
1475 if (np->mac_in_use)
1476 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1477 writel(rx_ctrl, base + NvRegReceiverControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001478 dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1479 dev->name, np->duplex, np->linkspeed);
1480 pci_push(base);
1481}
1482
1483static void nv_stop_rx(struct net_device *dev)
1484{
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001485 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001486 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001487 u32 rx_ctrl = readl(base + NvRegReceiverControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001488
1489 dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001490 if (!np->mac_in_use)
1491 rx_ctrl &= ~NVREG_RCVCTL_START;
1492 else
1493 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1494 writel(rx_ctrl, base + NvRegReceiverControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001495 reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1496 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1497 KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1498
1499 udelay(NV_RXSTOP_DELAY2);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001500 if (!np->mac_in_use)
1501 writel(0, base + NvRegLinkSpeed);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001502}
1503
1504static void nv_start_tx(struct net_device *dev)
1505{
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001506 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001507 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001508 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001509
1510 dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001511 tx_ctrl |= NVREG_XMITCTL_START;
1512 if (np->mac_in_use)
1513 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1514 writel(tx_ctrl, base + NvRegTransmitterControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001515 pci_push(base);
1516}
1517
1518static void nv_stop_tx(struct net_device *dev)
1519{
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001520 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001521 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001522 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001523
1524 dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001525 if (!np->mac_in_use)
1526 tx_ctrl &= ~NVREG_XMITCTL_START;
1527 else
1528 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1529 writel(tx_ctrl, base + NvRegTransmitterControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001530 reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1531 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1532 KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1533
1534 udelay(NV_TXSTOP_DELAY2);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001535 if (!np->mac_in_use)
1536 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1537 base + NvRegTransmitPoll);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001538}
1539
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001540static void nv_start_rxtx(struct net_device *dev)
1541{
1542 nv_start_rx(dev);
1543 nv_start_tx(dev);
1544}
1545
1546static void nv_stop_rxtx(struct net_device *dev)
1547{
1548 nv_stop_rx(dev);
1549 nv_stop_tx(dev);
1550}
1551
Linus Torvalds1da177e2005-04-16 15:20:36 -07001552static void nv_txrx_reset(struct net_device *dev)
1553{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001554 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001555 u8 __iomem *base = get_hwbase(dev);
1556
1557 dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04001558 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001559 pci_push(base);
1560 udelay(NV_TXRX_RESET_DELAY);
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04001561 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001562 pci_push(base);
1563}
1564
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04001565static void nv_mac_reset(struct net_device *dev)
1566{
1567 struct fe_priv *np = netdev_priv(dev);
1568 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdulla4e84f9b2008-02-04 15:14:09 -05001569 u32 temp1, temp2, temp3;
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04001570
1571 dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
Ayaz Abdulla4e84f9b2008-02-04 15:14:09 -05001572
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04001573 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1574 pci_push(base);
Ayaz Abdulla4e84f9b2008-02-04 15:14:09 -05001575
1576 /* save registers since they will be cleared on reset */
1577 temp1 = readl(base + NvRegMacAddrA);
1578 temp2 = readl(base + NvRegMacAddrB);
1579 temp3 = readl(base + NvRegTransmitPoll);
1580
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04001581 writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1582 pci_push(base);
1583 udelay(NV_MAC_RESET_DELAY);
1584 writel(0, base + NvRegMacReset);
1585 pci_push(base);
1586 udelay(NV_MAC_RESET_DELAY);
Ayaz Abdulla4e84f9b2008-02-04 15:14:09 -05001587
1588 /* restore saved registers */
1589 writel(temp1, base + NvRegMacAddrA);
1590 writel(temp2, base + NvRegMacAddrB);
1591 writel(temp3, base + NvRegTransmitPoll);
1592
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04001593 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1594 pci_push(base);
1595}
1596
Ayaz Abdulla57fff692007-01-23 12:27:00 -05001597static void nv_get_hw_stats(struct net_device *dev)
1598{
1599 struct fe_priv *np = netdev_priv(dev);
1600 u8 __iomem *base = get_hwbase(dev);
1601
1602 np->estats.tx_bytes += readl(base + NvRegTxCnt);
1603 np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1604 np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1605 np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1606 np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1607 np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1608 np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1609 np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1610 np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1611 np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1612 np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1613 np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1614 np->estats.rx_runt += readl(base + NvRegRxRunt);
1615 np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1616 np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1617 np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1618 np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1619 np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1620 np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1621 np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1622 np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1623 np->estats.rx_packets =
1624 np->estats.rx_unicast +
1625 np->estats.rx_multicast +
1626 np->estats.rx_broadcast;
1627 np->estats.rx_errors_total =
1628 np->estats.rx_crc_errors +
1629 np->estats.rx_over_errors +
1630 np->estats.rx_frame_error +
1631 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1632 np->estats.rx_late_collision +
1633 np->estats.rx_runt +
1634 np->estats.rx_frame_too_long;
1635 np->estats.tx_errors_total =
1636 np->estats.tx_late_collision +
1637 np->estats.tx_fifo_errors +
1638 np->estats.tx_carrier_errors +
1639 np->estats.tx_excess_deferral +
1640 np->estats.tx_retry_error;
1641
1642 if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1643 np->estats.tx_deferral += readl(base + NvRegTxDef);
1644 np->estats.tx_packets += readl(base + NvRegTxFrame);
1645 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1646 np->estats.tx_pause += readl(base + NvRegTxPause);
1647 np->estats.rx_pause += readl(base + NvRegRxPause);
1648 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1649 }
Ayaz Abdulla9c662432008-08-06 12:11:42 -04001650
1651 if (np->driver_data & DEV_HAS_STATISTICS_V3) {
1652 np->estats.tx_unicast += readl(base + NvRegTxUnicast);
1653 np->estats.tx_multicast += readl(base + NvRegTxMulticast);
1654 np->estats.tx_broadcast += readl(base + NvRegTxBroadcast);
1655 }
Ayaz Abdulla57fff692007-01-23 12:27:00 -05001656}
1657
Linus Torvalds1da177e2005-04-16 15:20:36 -07001658/*
1659 * nv_get_stats: dev->get_stats function
1660 * Get latest stats value from the nic.
1661 * Called with read_lock(&dev_base_lock) held for read -
1662 * only synchronized against unregister_netdevice.
1663 */
1664static struct net_device_stats *nv_get_stats(struct net_device *dev)
1665{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001666 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001667
Ayaz Abdulla21828162007-01-23 12:27:21 -05001668 /* If the nic supports hw counters then retrieve latest values */
Ayaz Abdulla9c662432008-08-06 12:11:42 -04001669 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) {
Ayaz Abdulla21828162007-01-23 12:27:21 -05001670 nv_get_hw_stats(dev);
1671
1672 /* copy to net_device stats */
Jeff Garzik8148ff42007-10-16 20:56:09 -04001673 dev->stats.tx_bytes = np->estats.tx_bytes;
1674 dev->stats.tx_fifo_errors = np->estats.tx_fifo_errors;
1675 dev->stats.tx_carrier_errors = np->estats.tx_carrier_errors;
1676 dev->stats.rx_crc_errors = np->estats.rx_crc_errors;
1677 dev->stats.rx_over_errors = np->estats.rx_over_errors;
1678 dev->stats.rx_errors = np->estats.rx_errors_total;
1679 dev->stats.tx_errors = np->estats.tx_errors_total;
Ayaz Abdulla21828162007-01-23 12:27:21 -05001680 }
Jeff Garzik8148ff42007-10-16 20:56:09 -04001681
1682 return &dev->stats;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001683}
1684
1685/*
1686 * nv_alloc_rx: fill rx ring entries.
1687 * Return 1 if the allocations for the skbs failed and the
1688 * rx engine is without Available descriptors
1689 */
1690static int nv_alloc_rx(struct net_device *dev)
1691{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001692 struct fe_priv *np = netdev_priv(dev);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001693 struct ring_desc* less_rx;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001694
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001695 less_rx = np->get_rx.orig;
1696 if (less_rx-- == np->first_rx.orig)
1697 less_rx = np->last_rx.orig;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001698
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001699 while (np->put_rx.orig != less_rx) {
1700 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05001701 if (skb) {
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001702 np->put_rx_ctx->skb = skb;
Arnaldo Carvalho de Melo4305b542007-04-19 20:43:29 -07001703 np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1704 skb->data,
Arnaldo Carvalho de Melo8b5be262007-03-20 12:08:20 -03001705 skb_tailroom(skb),
Arnaldo Carvalho de Melo4305b542007-04-19 20:43:29 -07001706 PCI_DMA_FROMDEVICE);
Arnaldo Carvalho de Melo8b5be262007-03-20 12:08:20 -03001707 np->put_rx_ctx->dma_len = skb_tailroom(skb);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001708 np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1709 wmb();
1710 np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
Ayaz Abdullab01867c2007-01-21 18:10:52 -05001711 if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001712 np->put_rx.orig = np->first_rx.orig;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05001713 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001714 np->put_rx_ctx = np->first_rx_ctx;
1715 } else {
1716 return 1;
1717 }
1718 }
1719 return 0;
1720}
1721
1722static int nv_alloc_rx_optimized(struct net_device *dev)
1723{
1724 struct fe_priv *np = netdev_priv(dev);
1725 struct ring_desc_ex* less_rx;
1726
1727 less_rx = np->get_rx.ex;
1728 if (less_rx-- == np->first_rx.ex)
1729 less_rx = np->last_rx.ex;
1730
1731 while (np->put_rx.ex != less_rx) {
1732 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1733 if (skb) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001734 np->put_rx_ctx->skb = skb;
Arnaldo Carvalho de Melo4305b542007-04-19 20:43:29 -07001735 np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1736 skb->data,
Arnaldo Carvalho de Melo8b5be262007-03-20 12:08:20 -03001737 skb_tailroom(skb),
Arnaldo Carvalho de Melo4305b542007-04-19 20:43:29 -07001738 PCI_DMA_FROMDEVICE);
Arnaldo Carvalho de Melo8b5be262007-03-20 12:08:20 -03001739 np->put_rx_ctx->dma_len = skb_tailroom(skb);
Al Viro5bb7ea22007-12-09 16:06:41 +00001740 np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));
1741 np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001742 wmb();
1743 np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
Ayaz Abdullab01867c2007-01-21 18:10:52 -05001744 if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001745 np->put_rx.ex = np->first_rx.ex;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05001746 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05001747 np->put_rx_ctx = np->first_rx_ctx;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001748 } else {
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05001749 return 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001750 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001751 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001752 return 0;
1753}
1754
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07001755/* If rx bufs are exhausted called after 50ms to attempt to refresh */
1756#ifdef CONFIG_FORCEDETH_NAPI
1757static void nv_do_rx_refill(unsigned long data)
1758{
1759 struct net_device *dev = (struct net_device *) data;
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001760 struct fe_priv *np = netdev_priv(dev);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07001761
1762 /* Just reschedule NAPI rx processing */
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001763 netif_rx_schedule(dev, &np->napi);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07001764}
1765#else
Linus Torvalds1da177e2005-04-16 15:20:36 -07001766static void nv_do_rx_refill(unsigned long data)
1767{
1768 struct net_device *dev = (struct net_device *) data;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001769 struct fe_priv *np = netdev_priv(dev);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001770 int retcode;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001771
Ayaz Abdulla84b39322006-05-20 14:59:48 -07001772 if (!using_multi_irqs(dev)) {
1773 if (np->msi_flags & NV_MSI_X_ENABLED)
1774 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1775 else
Manfred Spraula7475902007-10-17 21:52:33 +02001776 disable_irq(np->pci_dev->irq);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05001777 } else {
1778 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1779 }
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001780 if (!nv_optimized(np))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001781 retcode = nv_alloc_rx(dev);
1782 else
1783 retcode = nv_alloc_rx_optimized(dev);
1784 if (retcode) {
Ayaz Abdulla84b39322006-05-20 14:59:48 -07001785 spin_lock_irq(&np->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001786 if (!np->in_shutdown)
1787 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07001788 spin_unlock_irq(&np->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001789 }
Ayaz Abdulla84b39322006-05-20 14:59:48 -07001790 if (!using_multi_irqs(dev)) {
1791 if (np->msi_flags & NV_MSI_X_ENABLED)
1792 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1793 else
Manfred Spraula7475902007-10-17 21:52:33 +02001794 enable_irq(np->pci_dev->irq);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05001795 } else {
1796 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1797 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001798}
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07001799#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001800
Jeff Garzikf3b197a2006-05-26 21:39:03 -04001801static void nv_init_rx(struct net_device *dev)
Manfred Sprauld81c0982005-07-31 18:20:30 +02001802{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001803 struct fe_priv *np = netdev_priv(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02001804 int i;
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001805
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001806 np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001807
1808 if (!nv_optimized(np))
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001809 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1810 else
1811 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1812 np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1813 np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
Manfred Sprauld81c0982005-07-31 18:20:30 +02001814
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001815 for (i = 0; i < np->rx_ring_size; i++) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001816 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001817 np->rx_ring.orig[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001818 np->rx_ring.orig[i].buf = 0;
1819 } else {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001820 np->rx_ring.ex[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001821 np->rx_ring.ex[i].txvlan = 0;
1822 np->rx_ring.ex[i].bufhigh = 0;
1823 np->rx_ring.ex[i].buflow = 0;
1824 }
1825 np->rx_skb[i].skb = NULL;
1826 np->rx_skb[i].dma = 0;
1827 }
Manfred Sprauld81c0982005-07-31 18:20:30 +02001828}
1829
1830static void nv_init_tx(struct net_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001831{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001832 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001833 int i;
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001834
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001835 np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001836
1837 if (!nv_optimized(np))
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001838 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1839 else
1840 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1841 np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1842 np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05001843 np->tx_pkts_in_progress = 0;
1844 np->tx_change_owner = NULL;
1845 np->tx_end_flip = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001846
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04001847 for (i = 0; i < np->tx_ring_size; i++) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001848 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001849 np->tx_ring.orig[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001850 np->tx_ring.orig[i].buf = 0;
1851 } else {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001852 np->tx_ring.ex[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001853 np->tx_ring.ex[i].txvlan = 0;
1854 np->tx_ring.ex[i].bufhigh = 0;
1855 np->tx_ring.ex[i].buflow = 0;
1856 }
1857 np->tx_skb[i].skb = NULL;
1858 np->tx_skb[i].dma = 0;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05001859 np->tx_skb[i].dma_len = 0;
1860 np->tx_skb[i].first_tx_desc = NULL;
1861 np->tx_skb[i].next_tx_ctx = NULL;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001862 }
Manfred Sprauld81c0982005-07-31 18:20:30 +02001863}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001864
Manfred Sprauld81c0982005-07-31 18:20:30 +02001865static int nv_init_ring(struct net_device *dev)
1866{
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001867 struct fe_priv *np = netdev_priv(dev);
1868
Manfred Sprauld81c0982005-07-31 18:20:30 +02001869 nv_init_tx(dev);
1870 nv_init_rx(dev);
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001871
1872 if (!nv_optimized(np))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001873 return nv_alloc_rx(dev);
1874 else
1875 return nv_alloc_rx_optimized(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001876}
1877
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001878static int nv_release_txskb(struct net_device *dev, struct nv_skb_map* tx_skb)
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001879{
1880 struct fe_priv *np = netdev_priv(dev);
Ayaz Abdullafa454592006-01-05 22:45:45 -08001881
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001882 if (tx_skb->dma) {
1883 pci_unmap_page(np->pci_dev, tx_skb->dma,
1884 tx_skb->dma_len,
Ayaz Abdullafa454592006-01-05 22:45:45 -08001885 PCI_DMA_TODEVICE);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001886 tx_skb->dma = 0;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001887 }
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001888 if (tx_skb->skb) {
1889 dev_kfree_skb_any(tx_skb->skb);
1890 tx_skb->skb = NULL;
Ayaz Abdullafa454592006-01-05 22:45:45 -08001891 return 1;
1892 } else {
1893 return 0;
1894 }
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001895}
1896
Linus Torvalds1da177e2005-04-16 15:20:36 -07001897static void nv_drain_tx(struct net_device *dev)
1898{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001899 struct fe_priv *np = netdev_priv(dev);
1900 unsigned int i;
Jeff Garzikf3b197a2006-05-26 21:39:03 -04001901
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04001902 for (i = 0; i < np->tx_ring_size; i++) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001903 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001904 np->tx_ring.orig[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001905 np->tx_ring.orig[i].buf = 0;
1906 } else {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001907 np->tx_ring.ex[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001908 np->tx_ring.ex[i].txvlan = 0;
1909 np->tx_ring.ex[i].bufhigh = 0;
1910 np->tx_ring.ex[i].buflow = 0;
1911 }
1912 if (nv_release_txskb(dev, &np->tx_skb[i]))
Jeff Garzik8148ff42007-10-16 20:56:09 -04001913 dev->stats.tx_dropped++;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05001914 np->tx_skb[i].dma = 0;
1915 np->tx_skb[i].dma_len = 0;
1916 np->tx_skb[i].first_tx_desc = NULL;
1917 np->tx_skb[i].next_tx_ctx = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001918 }
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05001919 np->tx_pkts_in_progress = 0;
1920 np->tx_change_owner = NULL;
1921 np->tx_end_flip = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001922}
1923
1924static void nv_drain_rx(struct net_device *dev)
1925{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001926 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001927 int i;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001928
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04001929 for (i = 0; i < np->rx_ring_size; i++) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001930 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001931 np->rx_ring.orig[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001932 np->rx_ring.orig[i].buf = 0;
1933 } else {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001934 np->rx_ring.ex[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001935 np->rx_ring.ex[i].txvlan = 0;
1936 np->rx_ring.ex[i].bufhigh = 0;
1937 np->rx_ring.ex[i].buflow = 0;
1938 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001939 wmb();
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001940 if (np->rx_skb[i].skb) {
1941 pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
Arnaldo Carvalho de Melo4305b542007-04-19 20:43:29 -07001942 (skb_end_pointer(np->rx_skb[i].skb) -
1943 np->rx_skb[i].skb->data),
1944 PCI_DMA_FROMDEVICE);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001945 dev_kfree_skb(np->rx_skb[i].skb);
1946 np->rx_skb[i].skb = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001947 }
1948 }
1949}
1950
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001951static void nv_drain_rxtx(struct net_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001952{
1953 nv_drain_tx(dev);
1954 nv_drain_rx(dev);
1955}
1956
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001957static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
1958{
1959 return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
1960}
1961
Ayaz Abdullaa4336862008-04-18 13:50:43 -07001962static void nv_legacybackoff_reseed(struct net_device *dev)
1963{
1964 u8 __iomem *base = get_hwbase(dev);
1965 u32 reg;
1966 u32 low;
1967 int tx_status = 0;
1968
1969 reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK;
1970 get_random_bytes(&low, sizeof(low));
1971 reg |= low & NVREG_SLOTTIME_MASK;
1972
1973 /* Need to stop tx before change takes effect.
1974 * Caller has already gained np->lock.
1975 */
1976 tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START;
1977 if (tx_status)
1978 nv_stop_tx(dev);
1979 nv_stop_rx(dev);
1980 writel(reg, base + NvRegSlotTime);
1981 if (tx_status)
1982 nv_start_tx(dev);
1983 nv_start_rx(dev);
1984}
1985
1986/* Gear Backoff Seeds */
1987#define BACKOFF_SEEDSET_ROWS 8
1988#define BACKOFF_SEEDSET_LFSRS 15
1989
1990/* Known Good seed sets */
1991static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
1992 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
1993 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
1994 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
1995 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
1996 {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
1997 {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
1998 {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800, 84},
1999 {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184}};
2000
2001static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2002 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2003 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2004 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
2005 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2006 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2007 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2008 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2009 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}};
2010
2011static void nv_gear_backoff_reseed(struct net_device *dev)
2012{
2013 u8 __iomem *base = get_hwbase(dev);
2014 u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed;
2015 u32 temp, seedset, combinedSeed;
2016 int i;
2017
2018 /* Setup seed for free running LFSR */
2019 /* We are going to read the time stamp counter 3 times
2020 and swizzle bits around to increase randomness */
2021 get_random_bytes(&miniseed1, sizeof(miniseed1));
2022 miniseed1 &= 0x0fff;
2023 if (miniseed1 == 0)
2024 miniseed1 = 0xabc;
2025
2026 get_random_bytes(&miniseed2, sizeof(miniseed2));
2027 miniseed2 &= 0x0fff;
2028 if (miniseed2 == 0)
2029 miniseed2 = 0xabc;
2030 miniseed2_reversed =
2031 ((miniseed2 & 0xF00) >> 8) |
2032 (miniseed2 & 0x0F0) |
2033 ((miniseed2 & 0x00F) << 8);
2034
2035 get_random_bytes(&miniseed3, sizeof(miniseed3));
2036 miniseed3 &= 0x0fff;
2037 if (miniseed3 == 0)
2038 miniseed3 = 0xabc;
2039 miniseed3_reversed =
2040 ((miniseed3 & 0xF00) >> 8) |
2041 (miniseed3 & 0x0F0) |
2042 ((miniseed3 & 0x00F) << 8);
2043
2044 combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) |
2045 (miniseed2 ^ miniseed3_reversed);
2046
2047 /* Seeds can not be zero */
2048 if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0)
2049 combinedSeed |= 0x08;
2050 if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0)
2051 combinedSeed |= 0x8000;
2052
2053 /* No need to disable tx here */
2054 temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT);
2055 temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK;
2056 temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR;
2057 writel(temp,base + NvRegBackOffControl);
2058
2059 /* Setup seeds for all gear LFSRs. */
2060 get_random_bytes(&seedset, sizeof(seedset));
2061 seedset = seedset % BACKOFF_SEEDSET_ROWS;
2062 for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++)
2063 {
2064 temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT);
2065 temp |= main_seedset[seedset][i-1] & 0x3ff;
2066 temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR);
2067 writel(temp, base + NvRegBackOffControl);
2068 }
2069}
2070
Linus Torvalds1da177e2005-04-16 15:20:36 -07002071/*
2072 * nv_start_xmit: dev->hard_start_xmit function
Herbert Xu932ff272006-06-09 12:20:56 -07002073 * Called with netif_tx_lock held.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002074 */
2075static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
2076{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002077 struct fe_priv *np = netdev_priv(dev);
Ayaz Abdullafa454592006-01-05 22:45:45 -08002078 u32 tx_flags = 0;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002079 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
2080 unsigned int fragments = skb_shinfo(skb)->nr_frags;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002081 unsigned int i;
Ayaz Abdullafa454592006-01-05 22:45:45 -08002082 u32 offset = 0;
2083 u32 bcnt;
2084 u32 size = skb->len-skb->data_len;
2085 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002086 u32 empty_slots;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002087 struct ring_desc* put_tx;
2088 struct ring_desc* start_tx;
2089 struct ring_desc* prev_tx;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002090 struct nv_skb_map* prev_tx_ctx;
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002091 unsigned long flags;
Ayaz Abdullafa454592006-01-05 22:45:45 -08002092
2093 /* add fragments to entries count */
2094 for (i = 0; i < fragments; i++) {
2095 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2096 ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2097 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002098
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002099 empty_slots = nv_get_empty_tx_slots(np);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002100 if (unlikely(empty_slots <= entries)) {
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002101 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002102 netif_stop_queue(dev);
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002103 np->tx_stop = 1;
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002104 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002105 return NETDEV_TX_BUSY;
2106 }
2107
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002108 start_tx = put_tx = np->put_tx.orig;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002109
Ayaz Abdullafa454592006-01-05 22:45:45 -08002110 /* setup the header buffer */
2111 do {
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002112 prev_tx = put_tx;
2113 prev_tx_ctx = np->put_tx_ctx;
Ayaz Abdullafa454592006-01-05 22:45:45 -08002114 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002115 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
Ayaz Abdullafa454592006-01-05 22:45:45 -08002116 PCI_DMA_TODEVICE);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002117 np->put_tx_ctx->dma_len = bcnt;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002118 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2119 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002120
Ayaz Abdullafa454592006-01-05 22:45:45 -08002121 tx_flags = np->tx_flags;
2122 offset += bcnt;
2123 size -= bcnt;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002124 if (unlikely(put_tx++ == np->last_tx.orig))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002125 put_tx = np->first_tx.orig;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002126 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002127 np->put_tx_ctx = np->first_tx_ctx;
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002128 } while (size);
Ayaz Abdullafa454592006-01-05 22:45:45 -08002129
2130 /* setup the fragments */
2131 for (i = 0; i < fragments; i++) {
2132 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2133 u32 size = frag->size;
2134 offset = 0;
2135
2136 do {
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002137 prev_tx = put_tx;
2138 prev_tx_ctx = np->put_tx_ctx;
Ayaz Abdullafa454592006-01-05 22:45:45 -08002139 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002140 np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2141 PCI_DMA_TODEVICE);
2142 np->put_tx_ctx->dma_len = bcnt;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002143 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2144 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002145
Ayaz Abdullafa454592006-01-05 22:45:45 -08002146 offset += bcnt;
2147 size -= bcnt;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002148 if (unlikely(put_tx++ == np->last_tx.orig))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002149 put_tx = np->first_tx.orig;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002150 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002151 np->put_tx_ctx = np->first_tx_ctx;
Ayaz Abdullafa454592006-01-05 22:45:45 -08002152 } while (size);
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002153 }
2154
Ayaz Abdullafa454592006-01-05 22:45:45 -08002155 /* set last fragment flag */
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002156 prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
Ayaz Abdullafa454592006-01-05 22:45:45 -08002157
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002158 /* save skb in this slot's context area */
2159 prev_tx_ctx->skb = skb;
Ayaz Abdullafa454592006-01-05 22:45:45 -08002160
Herbert Xu89114af2006-07-08 13:34:32 -07002161 if (skb_is_gso(skb))
Herbert Xu79671682006-06-22 02:40:14 -07002162 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
Manfred Spraulee733622005-07-31 18:32:26 +02002163 else
Arjan van de Ven1d39ed52006-12-12 14:06:23 +01002164 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
Patrick McHardy84fa7932006-08-29 16:44:56 -07002165 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002166
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002167 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdulla164a86e2007-01-09 13:30:10 -05002168
Ayaz Abdullafa454592006-01-05 22:45:45 -08002169 /* set tx flags */
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002170 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2171 np->put_tx.orig = put_tx;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002172
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002173 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002174
2175 dprintk(KERN_DEBUG "%s: nv_start_xmit: entries %d queued for transmission. tx_flags_extra: %x\n",
2176 dev->name, entries, tx_flags_extra);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002177 {
2178 int j;
2179 for (j=0; j<64; j++) {
2180 if ((j%16) == 0)
2181 dprintk("\n%03x:", j);
2182 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2183 }
2184 dprintk("\n");
2185 }
2186
Linus Torvalds1da177e2005-04-16 15:20:36 -07002187 dev->trans_start = jiffies;
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04002188 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002189 return NETDEV_TX_OK;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002190}
2191
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002192static int nv_start_xmit_optimized(struct sk_buff *skb, struct net_device *dev)
2193{
2194 struct fe_priv *np = netdev_priv(dev);
2195 u32 tx_flags = 0;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002196 u32 tx_flags_extra;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002197 unsigned int fragments = skb_shinfo(skb)->nr_frags;
2198 unsigned int i;
2199 u32 offset = 0;
2200 u32 bcnt;
2201 u32 size = skb->len-skb->data_len;
2202 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2203 u32 empty_slots;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002204 struct ring_desc_ex* put_tx;
2205 struct ring_desc_ex* start_tx;
2206 struct ring_desc_ex* prev_tx;
2207 struct nv_skb_map* prev_tx_ctx;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05002208 struct nv_skb_map* start_tx_ctx;
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002209 unsigned long flags;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002210
2211 /* add fragments to entries count */
2212 for (i = 0; i < fragments; i++) {
2213 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2214 ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2215 }
2216
2217 empty_slots = nv_get_empty_tx_slots(np);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002218 if (unlikely(empty_slots <= entries)) {
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002219 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002220 netif_stop_queue(dev);
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002221 np->tx_stop = 1;
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002222 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002223 return NETDEV_TX_BUSY;
2224 }
2225
2226 start_tx = put_tx = np->put_tx.ex;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05002227 start_tx_ctx = np->put_tx_ctx;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002228
2229 /* setup the header buffer */
2230 do {
2231 prev_tx = put_tx;
2232 prev_tx_ctx = np->put_tx_ctx;
2233 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2234 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2235 PCI_DMA_TODEVICE);
2236 np->put_tx_ctx->dma_len = bcnt;
Al Viro5bb7ea22007-12-09 16:06:41 +00002237 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2238 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002239 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002240
2241 tx_flags = NV_TX2_VALID;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002242 offset += bcnt;
2243 size -= bcnt;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002244 if (unlikely(put_tx++ == np->last_tx.ex))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002245 put_tx = np->first_tx.ex;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002246 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002247 np->put_tx_ctx = np->first_tx_ctx;
2248 } while (size);
2249
2250 /* setup the fragments */
2251 for (i = 0; i < fragments; i++) {
2252 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2253 u32 size = frag->size;
2254 offset = 0;
2255
2256 do {
2257 prev_tx = put_tx;
2258 prev_tx_ctx = np->put_tx_ctx;
2259 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2260 np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2261 PCI_DMA_TODEVICE);
2262 np->put_tx_ctx->dma_len = bcnt;
Al Viro5bb7ea22007-12-09 16:06:41 +00002263 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2264 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002265 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002266
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002267 offset += bcnt;
2268 size -= bcnt;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002269 if (unlikely(put_tx++ == np->last_tx.ex))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002270 put_tx = np->first_tx.ex;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002271 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002272 np->put_tx_ctx = np->first_tx_ctx;
2273 } while (size);
2274 }
2275
2276 /* set last fragment flag */
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002277 prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002278
2279 /* save skb in this slot's context area */
2280 prev_tx_ctx->skb = skb;
2281
2282 if (skb_is_gso(skb))
2283 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2284 else
2285 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2286 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2287
2288 /* vlan tag */
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002289 if (likely(!np->vlangrp)) {
2290 start_tx->txvlan = 0;
2291 } else {
2292 if (vlan_tx_tag_present(skb))
2293 start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb));
2294 else
2295 start_tx->txvlan = 0;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002296 }
2297
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002298 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002299
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05002300 if (np->tx_limit) {
2301 /* Limit the number of outstanding tx. Setup all fragments, but
2302 * do not set the VALID bit on the first descriptor. Save a pointer
2303 * to that descriptor and also for next skb_map element.
2304 */
2305
2306 if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) {
2307 if (!np->tx_change_owner)
2308 np->tx_change_owner = start_tx_ctx;
2309
2310 /* remove VALID bit */
2311 tx_flags &= ~NV_TX2_VALID;
2312 start_tx_ctx->first_tx_desc = start_tx;
2313 start_tx_ctx->next_tx_ctx = np->put_tx_ctx;
2314 np->tx_end_flip = np->put_tx_ctx;
2315 } else {
2316 np->tx_pkts_in_progress++;
2317 }
2318 }
2319
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002320 /* set tx flags */
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002321 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2322 np->put_tx.ex = put_tx;
2323
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002324 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002325
2326 dprintk(KERN_DEBUG "%s: nv_start_xmit_optimized: entries %d queued for transmission. tx_flags_extra: %x\n",
2327 dev->name, entries, tx_flags_extra);
2328 {
2329 int j;
2330 for (j=0; j<64; j++) {
2331 if ((j%16) == 0)
2332 dprintk("\n%03x:", j);
2333 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2334 }
2335 dprintk("\n");
2336 }
2337
2338 dev->trans_start = jiffies;
2339 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002340 return NETDEV_TX_OK;
2341}
2342
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05002343static inline void nv_tx_flip_ownership(struct net_device *dev)
2344{
2345 struct fe_priv *np = netdev_priv(dev);
2346
2347 np->tx_pkts_in_progress--;
2348 if (np->tx_change_owner) {
Al Viro30ecce92008-03-26 05:57:12 +00002349 np->tx_change_owner->first_tx_desc->flaglen |=
2350 cpu_to_le32(NV_TX2_VALID);
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05002351 np->tx_pkts_in_progress++;
2352
2353 np->tx_change_owner = np->tx_change_owner->next_tx_ctx;
2354 if (np->tx_change_owner == np->tx_end_flip)
2355 np->tx_change_owner = NULL;
2356
2357 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2358 }
2359}
2360
Linus Torvalds1da177e2005-04-16 15:20:36 -07002361/*
2362 * nv_tx_done: check for completed packets, release the skbs.
2363 *
2364 * Caller must own np->lock.
2365 */
2366static void nv_tx_done(struct net_device *dev)
2367{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002368 struct fe_priv *np = netdev_priv(dev);
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002369 u32 flags;
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002370 struct ring_desc* orig_get_tx = np->get_tx.orig;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002371
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002372 while ((np->get_tx.orig != np->put_tx.orig) &&
2373 !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002374
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002375 dprintk(KERN_DEBUG "%s: nv_tx_done: flags 0x%x.\n",
2376 dev->name, flags);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002377
2378 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
2379 np->get_tx_ctx->dma_len,
2380 PCI_DMA_TODEVICE);
2381 np->get_tx_ctx->dma = 0;
2382
Linus Torvalds1da177e2005-04-16 15:20:36 -07002383 if (np->desc_ver == DESC_VER_1) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002384 if (flags & NV_TX_LASTPACKET) {
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002385 if (flags & NV_TX_ERROR) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002386 if (flags & NV_TX_UNDERFLOW)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002387 dev->stats.tx_fifo_errors++;
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002388 if (flags & NV_TX_CARRIERLOST)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002389 dev->stats.tx_carrier_errors++;
Ayaz Abdullaa4336862008-04-18 13:50:43 -07002390 if ((flags & NV_TX_RETRYERROR) && !(flags & NV_TX_RETRYCOUNT_MASK))
2391 nv_legacybackoff_reseed(dev);
Jeff Garzik8148ff42007-10-16 20:56:09 -04002392 dev->stats.tx_errors++;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002393 } else {
Jeff Garzik8148ff42007-10-16 20:56:09 -04002394 dev->stats.tx_packets++;
2395 dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002396 }
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002397 dev_kfree_skb_any(np->get_tx_ctx->skb);
2398 np->get_tx_ctx->skb = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002399 }
2400 } else {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002401 if (flags & NV_TX2_LASTPACKET) {
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002402 if (flags & NV_TX2_ERROR) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002403 if (flags & NV_TX2_UNDERFLOW)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002404 dev->stats.tx_fifo_errors++;
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002405 if (flags & NV_TX2_CARRIERLOST)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002406 dev->stats.tx_carrier_errors++;
Ayaz Abdullaa4336862008-04-18 13:50:43 -07002407 if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK))
2408 nv_legacybackoff_reseed(dev);
Jeff Garzik8148ff42007-10-16 20:56:09 -04002409 dev->stats.tx_errors++;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002410 } else {
Jeff Garzik8148ff42007-10-16 20:56:09 -04002411 dev->stats.tx_packets++;
2412 dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
Jeff Garzikf3b197a2006-05-26 21:39:03 -04002413 }
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002414 dev_kfree_skb_any(np->get_tx_ctx->skb);
2415 np->get_tx_ctx->skb = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002416 }
2417 }
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002418 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002419 np->get_tx.orig = np->first_tx.orig;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002420 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002421 np->get_tx_ctx = np->first_tx_ctx;
2422 }
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002423 if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002424 np->tx_stop = 0;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002425 netif_wake_queue(dev);
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002426 }
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002427}
2428
Ayaz Abdulla4e16ed12007-01-23 12:00:56 -05002429static void nv_tx_done_optimized(struct net_device *dev, int limit)
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002430{
2431 struct fe_priv *np = netdev_priv(dev);
2432 u32 flags;
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002433 struct ring_desc_ex* orig_get_tx = np->get_tx.ex;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002434
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002435 while ((np->get_tx.ex != np->put_tx.ex) &&
Ayaz Abdulla4e16ed12007-01-23 12:00:56 -05002436 !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX_VALID) &&
2437 (limit-- > 0)) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002438
2439 dprintk(KERN_DEBUG "%s: nv_tx_done_optimized: flags 0x%x.\n",
2440 dev->name, flags);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002441
2442 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
2443 np->get_tx_ctx->dma_len,
2444 PCI_DMA_TODEVICE);
2445 np->get_tx_ctx->dma = 0;
2446
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002447 if (flags & NV_TX2_LASTPACKET) {
Ayaz Abdulla21828162007-01-23 12:27:21 -05002448 if (!(flags & NV_TX2_ERROR))
Jeff Garzik8148ff42007-10-16 20:56:09 -04002449 dev->stats.tx_packets++;
Ayaz Abdullaa4336862008-04-18 13:50:43 -07002450 else {
2451 if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK)) {
2452 if (np->driver_data & DEV_HAS_GEAR_MODE)
2453 nv_gear_backoff_reseed(dev);
2454 else
2455 nv_legacybackoff_reseed(dev);
2456 }
2457 }
2458
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002459 dev_kfree_skb_any(np->get_tx_ctx->skb);
2460 np->get_tx_ctx->skb = NULL;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05002461
2462 if (np->tx_limit) {
2463 nv_tx_flip_ownership(dev);
2464 }
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002465 }
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002466 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002467 np->get_tx.ex = np->first_tx.ex;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002468 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002469 np->get_tx_ctx = np->first_tx_ctx;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002470 }
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002471 if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002472 np->tx_stop = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002473 netif_wake_queue(dev);
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002474 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002475}
2476
2477/*
2478 * nv_tx_timeout: dev->tx_timeout function
Herbert Xu932ff272006-06-09 12:20:56 -07002479 * Called with netif_tx_lock held.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002480 */
2481static void nv_tx_timeout(struct net_device *dev)
2482{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002483 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002484 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05002485 u32 status;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002486
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05002487 if (np->msi_flags & NV_MSI_X_ENABLED)
2488 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2489 else
2490 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2491
2492 printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002493
Manfred Spraulc2dba062005-07-31 18:29:47 +02002494 {
2495 int i;
2496
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002497 printk(KERN_INFO "%s: Ring at %lx\n",
2498 dev->name, (unsigned long)np->ring_addr);
Manfred Spraulc2dba062005-07-31 18:29:47 +02002499 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04002500 for (i=0;i<=np->register_size;i+= 32) {
Manfred Spraulc2dba062005-07-31 18:29:47 +02002501 printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
2502 i,
2503 readl(base + i + 0), readl(base + i + 4),
2504 readl(base + i + 8), readl(base + i + 12),
2505 readl(base + i + 16), readl(base + i + 20),
2506 readl(base + i + 24), readl(base + i + 28));
2507 }
2508 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04002509 for (i=0;i<np->tx_ring_size;i+= 4) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04002510 if (!nv_optimized(np)) {
Manfred Spraulee733622005-07-31 18:32:26 +02002511 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
Jeff Garzikf3b197a2006-05-26 21:39:03 -04002512 i,
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002513 le32_to_cpu(np->tx_ring.orig[i].buf),
2514 le32_to_cpu(np->tx_ring.orig[i].flaglen),
2515 le32_to_cpu(np->tx_ring.orig[i+1].buf),
2516 le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2517 le32_to_cpu(np->tx_ring.orig[i+2].buf),
2518 le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2519 le32_to_cpu(np->tx_ring.orig[i+3].buf),
2520 le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
Manfred Spraulee733622005-07-31 18:32:26 +02002521 } else {
2522 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
Jeff Garzikf3b197a2006-05-26 21:39:03 -04002523 i,
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002524 le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2525 le32_to_cpu(np->tx_ring.ex[i].buflow),
2526 le32_to_cpu(np->tx_ring.ex[i].flaglen),
2527 le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2528 le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2529 le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2530 le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2531 le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2532 le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2533 le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2534 le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2535 le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
Manfred Spraulee733622005-07-31 18:32:26 +02002536 }
Manfred Spraulc2dba062005-07-31 18:29:47 +02002537 }
2538 }
2539
Linus Torvalds1da177e2005-04-16 15:20:36 -07002540 spin_lock_irq(&np->lock);
2541
2542 /* 1) stop tx engine */
2543 nv_stop_tx(dev);
2544
2545 /* 2) check that the packets were not sent already: */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04002546 if (!nv_optimized(np))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002547 nv_tx_done(dev);
2548 else
Ayaz Abdulla4e16ed12007-01-23 12:00:56 -05002549 nv_tx_done_optimized(dev, np->tx_ring_size);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002550
2551 /* 3) if there are dead entries: clear everything */
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002552 if (np->get_tx_ctx != np->put_tx_ctx) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002553 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
2554 nv_drain_tx(dev);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002555 nv_init_tx(dev);
Ayaz Abdulla0832b252006-02-04 13:13:26 -05002556 setup_hw_rings(dev, NV_SETUP_TX_RING);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002557 }
2558
Ayaz Abdulla3ba4d092007-03-23 05:50:02 -05002559 netif_wake_queue(dev);
2560
Linus Torvalds1da177e2005-04-16 15:20:36 -07002561 /* 4) restart tx engine */
2562 nv_start_tx(dev);
2563 spin_unlock_irq(&np->lock);
2564}
2565
Manfred Spraul22c6d142005-04-19 21:17:09 +02002566/*
2567 * Called when the nic notices a mismatch between the actual data len on the
2568 * wire and the len indicated in the 802 header
2569 */
2570static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2571{
2572 int hdrlen; /* length of the 802 header */
2573 int protolen; /* length as stored in the proto field */
2574
2575 /* 1) calculate len according to header */
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002576 if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
Manfred Spraul22c6d142005-04-19 21:17:09 +02002577 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
2578 hdrlen = VLAN_HLEN;
2579 } else {
2580 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
2581 hdrlen = ETH_HLEN;
2582 }
2583 dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
2584 dev->name, datalen, protolen, hdrlen);
2585 if (protolen > ETH_DATA_LEN)
2586 return datalen; /* Value in proto field not a len, no checks possible */
2587
2588 protolen += hdrlen;
2589 /* consistency checks: */
2590 if (datalen > ETH_ZLEN) {
2591 if (datalen >= protolen) {
2592 /* more data on wire than in 802 header, trim of
2593 * additional data.
2594 */
2595 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2596 dev->name, protolen);
2597 return protolen;
2598 } else {
2599 /* less data on wire than mentioned in header.
2600 * Discard the packet.
2601 */
2602 dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
2603 dev->name);
2604 return -1;
2605 }
2606 } else {
2607 /* short packet. Accept only if 802 values are also short */
2608 if (protolen > ETH_ZLEN) {
2609 dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
2610 dev->name);
2611 return -1;
2612 }
2613 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2614 dev->name, datalen);
2615 return datalen;
2616 }
2617}
2618
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07002619static int nv_rx_process(struct net_device *dev, int limit)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002620{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002621 struct fe_priv *np = netdev_priv(dev);
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002622 u32 flags;
Ingo Molnarbcb5feb2007-10-16 20:44:59 -04002623 int rx_work = 0;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002624 struct sk_buff *skb;
2625 int len;
Ayaz Abdullaee407b02006-02-04 13:13:17 -05002626
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002627 while((np->get_rx.orig != np->put_rx.orig) &&
2628 !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
Ingo Molnarbcb5feb2007-10-16 20:44:59 -04002629 (rx_work < limit)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002630
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002631 dprintk(KERN_DEBUG "%s: nv_rx_process: flags 0x%x.\n",
2632 dev->name, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002633
Linus Torvalds1da177e2005-04-16 15:20:36 -07002634 /*
2635 * the packet is for us - immediately tear down the pci mapping.
2636 * TODO: check if a prefetch of the first cacheline improves
2637 * the performance.
2638 */
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002639 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2640 np->get_rx_ctx->dma_len,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002641 PCI_DMA_FROMDEVICE);
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05002642 skb = np->get_rx_ctx->skb;
2643 np->get_rx_ctx->skb = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002644
2645 {
2646 int j;
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002647 dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002648 for (j=0; j<64; j++) {
2649 if ((j%16) == 0)
2650 dprintk("\n%03x:", j);
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05002651 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002652 }
2653 dprintk("\n");
2654 }
2655 /* look at what we actually got: */
2656 if (np->desc_ver == DESC_VER_1) {
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002657 if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2658 len = flags & LEN_MASK_V1;
2659 if (unlikely(flags & NV_RX_ERROR)) {
Ayaz Abdulla1ef68412008-08-06 12:11:03 -04002660 if ((flags & NV_RX_ERROR_MASK) == NV_RX_ERROR4) {
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002661 len = nv_getlen(dev, skb->data, len);
2662 if (len < 0) {
Jeff Garzik8148ff42007-10-16 20:56:09 -04002663 dev->stats.rx_errors++;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002664 dev_kfree_skb(skb);
2665 goto next_pkt;
2666 }
2667 }
2668 /* framing errors are soft errors */
Ayaz Abdulla1ef68412008-08-06 12:11:03 -04002669 else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) {
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002670 if (flags & NV_RX_SUBSTRACT1) {
2671 len--;
2672 }
2673 }
2674 /* the rest are hard errors */
2675 else {
2676 if (flags & NV_RX_MISSEDFRAME)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002677 dev->stats.rx_missed_errors++;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002678 if (flags & NV_RX_CRCERR)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002679 dev->stats.rx_crc_errors++;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002680 if (flags & NV_RX_OVERFLOW)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002681 dev->stats.rx_over_errors++;
2682 dev->stats.rx_errors++;
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05002683 dev_kfree_skb(skb);
Ayaz Abdullaa971c322005-11-11 08:30:38 -05002684 goto next_pkt;
2685 }
2686 }
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002687 } else {
2688 dev_kfree_skb(skb);
2689 goto next_pkt;
Manfred Spraul22c6d142005-04-19 21:17:09 +02002690 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002691 } else {
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002692 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2693 len = flags & LEN_MASK_V2;
2694 if (unlikely(flags & NV_RX2_ERROR)) {
Ayaz Abdulla1ef68412008-08-06 12:11:03 -04002695 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002696 len = nv_getlen(dev, skb->data, len);
2697 if (len < 0) {
Jeff Garzik8148ff42007-10-16 20:56:09 -04002698 dev->stats.rx_errors++;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002699 dev_kfree_skb(skb);
2700 goto next_pkt;
2701 }
2702 }
2703 /* framing errors are soft errors */
Ayaz Abdulla1ef68412008-08-06 12:11:03 -04002704 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002705 if (flags & NV_RX2_SUBSTRACT1) {
2706 len--;
2707 }
2708 }
2709 /* the rest are hard errors */
2710 else {
2711 if (flags & NV_RX2_CRCERR)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002712 dev->stats.rx_crc_errors++;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002713 if (flags & NV_RX2_OVERFLOW)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002714 dev->stats.rx_over_errors++;
2715 dev->stats.rx_errors++;
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05002716 dev_kfree_skb(skb);
Ayaz Abdullaa971c322005-11-11 08:30:38 -05002717 goto next_pkt;
2718 }
2719 }
Ayaz Abdullabfaffe82008-01-13 16:02:55 -05002720 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2721 ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05002722 skb->ip_summed = CHECKSUM_UNNECESSARY;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002723 } else {
2724 dev_kfree_skb(skb);
2725 goto next_pkt;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002726 }
2727 }
2728 /* got a valid packet - forward it to the network core */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002729 skb_put(skb, len);
2730 skb->protocol = eth_type_trans(skb, dev);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002731 dprintk(KERN_DEBUG "%s: nv_rx_process: %d bytes, proto %d accepted.\n",
2732 dev->name, len, skb->protocol);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07002733#ifdef CONFIG_FORCEDETH_NAPI
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002734 netif_receive_skb(skb);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07002735#else
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002736 netif_rx(skb);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07002737#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07002738 dev->last_rx = jiffies;
Jeff Garzik8148ff42007-10-16 20:56:09 -04002739 dev->stats.rx_packets++;
2740 dev->stats.rx_bytes += len;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002741next_pkt:
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002742 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002743 np->get_rx.orig = np->first_rx.orig;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002744 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002745 np->get_rx_ctx = np->first_rx_ctx;
Ingo Molnarbcb5feb2007-10-16 20:44:59 -04002746
2747 rx_work++;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002748 }
2749
Ingo Molnarbcb5feb2007-10-16 20:44:59 -04002750 return rx_work;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002751}
2752
2753static int nv_rx_process_optimized(struct net_device *dev, int limit)
2754{
2755 struct fe_priv *np = netdev_priv(dev);
2756 u32 flags;
2757 u32 vlanflags = 0;
Ingo Molnarc1b71512007-10-17 12:18:23 +02002758 int rx_work = 0;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002759 struct sk_buff *skb;
2760 int len;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002761
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002762 while((np->get_rx.ex != np->put_rx.ex) &&
2763 !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
Ingo Molnarc1b71512007-10-17 12:18:23 +02002764 (rx_work < limit)) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002765
2766 dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: flags 0x%x.\n",
2767 dev->name, flags);
2768
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002769 /*
2770 * the packet is for us - immediately tear down the pci mapping.
2771 * TODO: check if a prefetch of the first cacheline improves
2772 * the performance.
2773 */
2774 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2775 np->get_rx_ctx->dma_len,
2776 PCI_DMA_FROMDEVICE);
2777 skb = np->get_rx_ctx->skb;
2778 np->get_rx_ctx->skb = NULL;
2779
2780 {
2781 int j;
2782 dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2783 for (j=0; j<64; j++) {
2784 if ((j%16) == 0)
2785 dprintk("\n%03x:", j);
2786 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2787 }
2788 dprintk("\n");
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002789 }
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002790 /* look at what we actually got: */
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002791 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2792 len = flags & LEN_MASK_V2;
2793 if (unlikely(flags & NV_RX2_ERROR)) {
Ayaz Abdulla1ef68412008-08-06 12:11:03 -04002794 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002795 len = nv_getlen(dev, skb->data, len);
2796 if (len < 0) {
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002797 dev_kfree_skb(skb);
2798 goto next_pkt;
2799 }
2800 }
2801 /* framing errors are soft errors */
Ayaz Abdulla1ef68412008-08-06 12:11:03 -04002802 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002803 if (flags & NV_RX2_SUBSTRACT1) {
2804 len--;
2805 }
2806 }
2807 /* the rest are hard errors */
2808 else {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002809 dev_kfree_skb(skb);
2810 goto next_pkt;
2811 }
2812 }
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002813
Ayaz Abdullabfaffe82008-01-13 16:02:55 -05002814 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2815 ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002816 skb->ip_summed = CHECKSUM_UNNECESSARY;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002817
2818 /* got a valid packet - forward it to the network core */
2819 skb_put(skb, len);
2820 skb->protocol = eth_type_trans(skb, dev);
2821 prefetch(skb->data);
2822
2823 dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: %d bytes, proto %d accepted.\n",
2824 dev->name, len, skb->protocol);
2825
2826 if (likely(!np->vlangrp)) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002827#ifdef CONFIG_FORCEDETH_NAPI
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002828 netif_receive_skb(skb);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002829#else
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002830 netif_rx(skb);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002831#endif
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002832 } else {
2833 vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2834 if (vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
2835#ifdef CONFIG_FORCEDETH_NAPI
2836 vlan_hwaccel_receive_skb(skb, np->vlangrp,
2837 vlanflags & NV_RX3_VLAN_TAG_MASK);
2838#else
2839 vlan_hwaccel_rx(skb, np->vlangrp,
2840 vlanflags & NV_RX3_VLAN_TAG_MASK);
2841#endif
2842 } else {
2843#ifdef CONFIG_FORCEDETH_NAPI
2844 netif_receive_skb(skb);
2845#else
2846 netif_rx(skb);
2847#endif
2848 }
2849 }
2850
2851 dev->last_rx = jiffies;
Jeff Garzik8148ff42007-10-16 20:56:09 -04002852 dev->stats.rx_packets++;
2853 dev->stats.rx_bytes += len;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002854 } else {
2855 dev_kfree_skb(skb);
2856 }
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002857next_pkt:
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002858 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002859 np->get_rx.ex = np->first_rx.ex;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002860 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002861 np->get_rx_ctx = np->first_rx_ctx;
Ingo Molnarc1b71512007-10-17 12:18:23 +02002862
2863 rx_work++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002864 }
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07002865
Ingo Molnarc1b71512007-10-17 12:18:23 +02002866 return rx_work;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002867}
2868
Manfred Sprauld81c0982005-07-31 18:20:30 +02002869static void set_bufsize(struct net_device *dev)
2870{
2871 struct fe_priv *np = netdev_priv(dev);
2872
2873 if (dev->mtu <= ETH_DATA_LEN)
2874 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2875 else
2876 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2877}
2878
Linus Torvalds1da177e2005-04-16 15:20:36 -07002879/*
2880 * nv_change_mtu: dev->change_mtu function
2881 * Called with dev_base_lock held for read.
2882 */
2883static int nv_change_mtu(struct net_device *dev, int new_mtu)
2884{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002885 struct fe_priv *np = netdev_priv(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02002886 int old_mtu;
2887
2888 if (new_mtu < 64 || new_mtu > np->pkt_limit)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002889 return -EINVAL;
Manfred Sprauld81c0982005-07-31 18:20:30 +02002890
2891 old_mtu = dev->mtu;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002892 dev->mtu = new_mtu;
Manfred Sprauld81c0982005-07-31 18:20:30 +02002893
2894 /* return early if the buffer sizes will not change */
2895 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2896 return 0;
2897 if (old_mtu == new_mtu)
2898 return 0;
2899
2900 /* synchronized against open : rtnl_lock() held by caller */
2901 if (netif_running(dev)) {
viro@ftp.linux.org.uk25097d42005-09-06 01:36:58 +01002902 u8 __iomem *base = get_hwbase(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02002903 /*
2904 * It seems that the nic preloads valid ring entries into an
2905 * internal buffer. The procedure for flushing everything is
2906 * guessed, there is probably a simpler approach.
2907 * Changing the MTU is a rare event, it shouldn't matter.
2908 */
Ayaz Abdulla84b39322006-05-20 14:59:48 -07002909 nv_disable_irq(dev);
Herbert Xu932ff272006-06-09 12:20:56 -07002910 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07002911 netif_addr_lock(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02002912 spin_lock(&np->lock);
2913 /* stop engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04002914 nv_stop_rxtx(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02002915 nv_txrx_reset(dev);
2916 /* drain rx queue */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04002917 nv_drain_rxtx(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02002918 /* reinit driver view of the rx queue */
Manfred Sprauld81c0982005-07-31 18:20:30 +02002919 set_bufsize(dev);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04002920 if (nv_init_ring(dev)) {
Manfred Sprauld81c0982005-07-31 18:20:30 +02002921 if (!np->in_shutdown)
2922 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2923 }
2924 /* reinit nic view of the rx queue */
2925 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
Ayaz Abdulla0832b252006-02-04 13:13:26 -05002926 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04002927 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
Manfred Sprauld81c0982005-07-31 18:20:30 +02002928 base + NvRegRingSizes);
2929 pci_push(base);
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04002930 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
Manfred Sprauld81c0982005-07-31 18:20:30 +02002931 pci_push(base);
2932
2933 /* restart rx engine */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04002934 nv_start_rxtx(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02002935 spin_unlock(&np->lock);
David S. Millere308a5d2008-07-15 00:13:44 -07002936 netif_addr_unlock(dev);
Herbert Xu932ff272006-06-09 12:20:56 -07002937 netif_tx_unlock_bh(dev);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07002938 nv_enable_irq(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02002939 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002940 return 0;
2941}
2942
Manfred Spraul72b31782005-07-31 18:33:34 +02002943static void nv_copy_mac_to_hw(struct net_device *dev)
2944{
viro@ftp.linux.org.uk25097d42005-09-06 01:36:58 +01002945 u8 __iomem *base = get_hwbase(dev);
Manfred Spraul72b31782005-07-31 18:33:34 +02002946 u32 mac[2];
2947
2948 mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
2949 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
2950 mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
2951
2952 writel(mac[0], base + NvRegMacAddrA);
2953 writel(mac[1], base + NvRegMacAddrB);
2954}
2955
2956/*
2957 * nv_set_mac_address: dev->set_mac_address function
2958 * Called with rtnl_lock() held.
2959 */
2960static int nv_set_mac_address(struct net_device *dev, void *addr)
2961{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002962 struct fe_priv *np = netdev_priv(dev);
Manfred Spraul72b31782005-07-31 18:33:34 +02002963 struct sockaddr *macaddr = (struct sockaddr*)addr;
2964
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002965 if (!is_valid_ether_addr(macaddr->sa_data))
Manfred Spraul72b31782005-07-31 18:33:34 +02002966 return -EADDRNOTAVAIL;
2967
2968 /* synchronized against open : rtnl_lock() held by caller */
2969 memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
2970
2971 if (netif_running(dev)) {
Herbert Xu932ff272006-06-09 12:20:56 -07002972 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07002973 netif_addr_lock(dev);
Manfred Spraul72b31782005-07-31 18:33:34 +02002974 spin_lock_irq(&np->lock);
2975
2976 /* stop rx engine */
2977 nv_stop_rx(dev);
2978
2979 /* set mac address */
2980 nv_copy_mac_to_hw(dev);
2981
2982 /* restart rx engine */
2983 nv_start_rx(dev);
2984 spin_unlock_irq(&np->lock);
David S. Millere308a5d2008-07-15 00:13:44 -07002985 netif_addr_unlock(dev);
Herbert Xu932ff272006-06-09 12:20:56 -07002986 netif_tx_unlock_bh(dev);
Manfred Spraul72b31782005-07-31 18:33:34 +02002987 } else {
2988 nv_copy_mac_to_hw(dev);
2989 }
2990 return 0;
2991}
2992
Linus Torvalds1da177e2005-04-16 15:20:36 -07002993/*
2994 * nv_set_multicast: dev->set_multicast function
Herbert Xu932ff272006-06-09 12:20:56 -07002995 * Called with netif_tx_lock held.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002996 */
2997static void nv_set_multicast(struct net_device *dev)
2998{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002999 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003000 u8 __iomem *base = get_hwbase(dev);
3001 u32 addr[2];
3002 u32 mask[2];
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003003 u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003004
3005 memset(addr, 0, sizeof(addr));
3006 memset(mask, 0, sizeof(mask));
3007
3008 if (dev->flags & IFF_PROMISC) {
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003009 pff |= NVREG_PFF_PROMISC;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003010 } else {
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003011 pff |= NVREG_PFF_MYADDR;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003012
3013 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
3014 u32 alwaysOff[2];
3015 u32 alwaysOn[2];
3016
3017 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
3018 if (dev->flags & IFF_ALLMULTI) {
3019 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
3020 } else {
3021 struct dev_mc_list *walk;
3022
3023 walk = dev->mc_list;
3024 while (walk != NULL) {
3025 u32 a, b;
Al Viro5bb7ea22007-12-09 16:06:41 +00003026 a = le32_to_cpu(*(__le32 *) walk->dmi_addr);
3027 b = le16_to_cpu(*(__le16 *) (&walk->dmi_addr[4]));
Linus Torvalds1da177e2005-04-16 15:20:36 -07003028 alwaysOn[0] &= a;
3029 alwaysOff[0] &= ~a;
3030 alwaysOn[1] &= b;
3031 alwaysOff[1] &= ~b;
3032 walk = walk->next;
3033 }
3034 }
3035 addr[0] = alwaysOn[0];
3036 addr[1] = alwaysOn[1];
3037 mask[0] = alwaysOn[0] | alwaysOff[0];
3038 mask[1] = alwaysOn[1] | alwaysOff[1];
Ayaz Abdullabb9a4fd2008-01-13 16:03:04 -05003039 } else {
3040 mask[0] = NVREG_MCASTMASKA_NONE;
3041 mask[1] = NVREG_MCASTMASKB_NONE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003042 }
3043 }
3044 addr[0] |= NVREG_MCASTADDRA_FORCE;
3045 pff |= NVREG_PFF_ALWAYS;
3046 spin_lock_irq(&np->lock);
3047 nv_stop_rx(dev);
3048 writel(addr[0], base + NvRegMulticastAddrA);
3049 writel(addr[1], base + NvRegMulticastAddrB);
3050 writel(mask[0], base + NvRegMulticastMaskA);
3051 writel(mask[1], base + NvRegMulticastMaskB);
3052 writel(pff, base + NvRegPacketFilterFlags);
3053 dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
3054 dev->name);
3055 nv_start_rx(dev);
3056 spin_unlock_irq(&np->lock);
3057}
3058
Adrian Bunkc7985052006-06-22 12:03:29 +02003059static void nv_update_pause(struct net_device *dev, u32 pause_flags)
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003060{
3061 struct fe_priv *np = netdev_priv(dev);
3062 u8 __iomem *base = get_hwbase(dev);
3063
3064 np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
3065
3066 if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
3067 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
3068 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
3069 writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
3070 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3071 } else {
3072 writel(pff, base + NvRegPacketFilterFlags);
3073 }
3074 }
3075 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
3076 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
3077 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -05003078 u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
3079 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2)
3080 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
Ayaz Abdulla9a33e882008-08-06 12:12:34 -04003081 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) {
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -05003082 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
Ayaz Abdulla9a33e882008-08-06 12:12:34 -04003083 /* limit the number of tx pause frames to a default of 8 */
3084 writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit);
3085 }
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -05003086 writel(pause_enable, base + NvRegTxPauseFrame);
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003087 writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
3088 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3089 } else {
3090 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
3091 writel(regmisc, base + NvRegMisc1);
3092 }
3093 }
3094}
3095
Ayaz Abdulla4ea7f292005-11-11 08:29:59 -05003096/**
3097 * nv_update_linkspeed: Setup the MAC according to the link partner
3098 * @dev: Network device to be configured
3099 *
3100 * The function queries the PHY and checks if there is a link partner.
3101 * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
3102 * set to 10 MBit HD.
3103 *
3104 * The function returns 0 if there is no link partner and 1 if there is
3105 * a good link partner.
3106 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07003107static int nv_update_linkspeed(struct net_device *dev)
3108{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04003109 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003110 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003111 int adv = 0;
3112 int lpa = 0;
3113 int adv_lpa, adv_pause, lpa_pause;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003114 int newls = np->linkspeed;
3115 int newdup = np->duplex;
3116 int mii_status;
3117 int retval = 0;
Ayaz Abdulla9744e212006-07-06 16:45:58 -04003118 u32 control_1000, status_1000, phyreg, pause_flags, txreg;
Ayaz Abdullab2976d22008-02-04 15:13:59 -05003119 u32 txrxFlags = 0;
Ayaz Abdullafd9b5582008-02-05 12:29:49 -05003120 u32 phy_exp;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003121
3122 /* BMSR_LSTATUS is latched, read it twice:
3123 * we want the current value.
3124 */
3125 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3126 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3127
3128 if (!(mii_status & BMSR_LSTATUS)) {
3129 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
3130 dev->name);
3131 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3132 newdup = 0;
3133 retval = 0;
3134 goto set_speed;
3135 }
3136
3137 if (np->autoneg == 0) {
3138 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
3139 dev->name, np->fixed_mode);
3140 if (np->fixed_mode & LPA_100FULL) {
3141 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3142 newdup = 1;
3143 } else if (np->fixed_mode & LPA_100HALF) {
3144 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3145 newdup = 0;
3146 } else if (np->fixed_mode & LPA_10FULL) {
3147 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3148 newdup = 1;
3149 } else {
3150 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3151 newdup = 0;
3152 }
3153 retval = 1;
3154 goto set_speed;
3155 }
3156 /* check auto negotiation is complete */
3157 if (!(mii_status & BMSR_ANEGCOMPLETE)) {
3158 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
3159 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3160 newdup = 0;
3161 retval = 0;
3162 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
3163 goto set_speed;
3164 }
3165
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003166 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3167 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
3168 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
3169 dev->name, adv, lpa);
3170
Linus Torvalds1da177e2005-04-16 15:20:36 -07003171 retval = 1;
3172 if (np->gigabit == PHY_GIGABIT) {
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003173 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3174 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003175
3176 if ((control_1000 & ADVERTISE_1000FULL) &&
3177 (status_1000 & LPA_1000FULL)) {
3178 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
3179 dev->name);
3180 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
3181 newdup = 1;
3182 goto set_speed;
3183 }
3184 }
3185
Linus Torvalds1da177e2005-04-16 15:20:36 -07003186 /* FIXME: handle parallel detection properly */
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003187 adv_lpa = lpa & adv;
3188 if (adv_lpa & LPA_100FULL) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003189 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3190 newdup = 1;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003191 } else if (adv_lpa & LPA_100HALF) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003192 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3193 newdup = 0;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003194 } else if (adv_lpa & LPA_10FULL) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003195 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3196 newdup = 1;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003197 } else if (adv_lpa & LPA_10HALF) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003198 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3199 newdup = 0;
3200 } else {
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003201 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003202 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3203 newdup = 0;
3204 }
3205
3206set_speed:
3207 if (np->duplex == newdup && np->linkspeed == newls)
3208 return retval;
3209
3210 dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
3211 dev->name, np->linkspeed, np->duplex, newls, newdup);
3212
3213 np->duplex = newdup;
3214 np->linkspeed = newls;
3215
Ayaz Abdullab2976d22008-02-04 15:13:59 -05003216 /* The transmitter and receiver must be restarted for safe update */
3217 if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
3218 txrxFlags |= NV_RESTART_TX;
3219 nv_stop_tx(dev);
3220 }
3221 if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
3222 txrxFlags |= NV_RESTART_RX;
3223 nv_stop_rx(dev);
3224 }
3225
Linus Torvalds1da177e2005-04-16 15:20:36 -07003226 if (np->gigabit == PHY_GIGABIT) {
Ayaz Abdullaa4336862008-04-18 13:50:43 -07003227 phyreg = readl(base + NvRegSlotTime);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003228 phyreg &= ~(0x3FF00);
Ayaz Abdullaa4336862008-04-18 13:50:43 -07003229 if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) ||
3230 ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100))
3231 phyreg |= NVREG_SLOTTIME_10_100_FULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003232 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
Ayaz Abdullaa4336862008-04-18 13:50:43 -07003233 phyreg |= NVREG_SLOTTIME_1000_FULL;
3234 writel(phyreg, base + NvRegSlotTime);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003235 }
3236
3237 phyreg = readl(base + NvRegPhyInterface);
3238 phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3239 if (np->duplex == 0)
3240 phyreg |= PHY_HALF;
3241 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3242 phyreg |= PHY_100;
3243 else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3244 phyreg |= PHY_1000;
3245 writel(phyreg, base + NvRegPhyInterface);
3246
Ayaz Abdullafd9b5582008-02-05 12:29:49 -05003247 phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
Ayaz Abdulla9744e212006-07-06 16:45:58 -04003248 if (phyreg & PHY_RGMII) {
Ayaz Abdullafd9b5582008-02-05 12:29:49 -05003249 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) {
Ayaz Abdulla9744e212006-07-06 16:45:58 -04003250 txreg = NVREG_TX_DEFERRAL_RGMII_1000;
Ayaz Abdullafd9b5582008-02-05 12:29:49 -05003251 } else {
3252 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) {
3253 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10)
3254 txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
3255 else
3256 txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
3257 } else {
3258 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3259 }
3260 }
Ayaz Abdulla9744e212006-07-06 16:45:58 -04003261 } else {
Ayaz Abdullafd9b5582008-02-05 12:29:49 -05003262 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX))
3263 txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
3264 else
3265 txreg = NVREG_TX_DEFERRAL_DEFAULT;
Ayaz Abdulla9744e212006-07-06 16:45:58 -04003266 }
3267 writel(txreg, base + NvRegTxDeferral);
3268
Ayaz Abdulla95d161c2006-07-06 16:46:25 -04003269 if (np->desc_ver == DESC_VER_1) {
3270 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3271 } else {
3272 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3273 txreg = NVREG_TX_WM_DESC2_3_1000;
3274 else
3275 txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3276 }
3277 writel(txreg, base + NvRegTxWatermark);
3278
Linus Torvalds1da177e2005-04-16 15:20:36 -07003279 writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
3280 base + NvRegMisc1);
3281 pci_push(base);
3282 writel(np->linkspeed, base + NvRegLinkSpeed);
3283 pci_push(base);
3284
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003285 pause_flags = 0;
3286 /* setup pause frame */
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003287 if (np->duplex != 0) {
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003288 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
3289 adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
3290 lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003291
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003292 switch (adv_pause) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07003293 case ADVERTISE_PAUSE_CAP:
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003294 if (lpa_pause & LPA_PAUSE_CAP) {
3295 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3296 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3297 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3298 }
3299 break;
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07003300 case ADVERTISE_PAUSE_ASYM:
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003301 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
3302 {
3303 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3304 }
3305 break;
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07003306 case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM:
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003307 if (lpa_pause & LPA_PAUSE_CAP)
3308 {
3309 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3310 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3311 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3312 }
3313 if (lpa_pause == LPA_PAUSE_ASYM)
3314 {
3315 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3316 }
3317 break;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003318 }
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003319 } else {
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003320 pause_flags = np->pause_flags;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003321 }
3322 }
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003323 nv_update_pause(dev, pause_flags);
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003324
Ayaz Abdullab2976d22008-02-04 15:13:59 -05003325 if (txrxFlags & NV_RESTART_TX)
3326 nv_start_tx(dev);
3327 if (txrxFlags & NV_RESTART_RX)
3328 nv_start_rx(dev);
3329
Linus Torvalds1da177e2005-04-16 15:20:36 -07003330 return retval;
3331}
3332
3333static void nv_linkchange(struct net_device *dev)
3334{
3335 if (nv_update_linkspeed(dev)) {
Ayaz Abdulla4ea7f292005-11-11 08:29:59 -05003336 if (!netif_carrier_ok(dev)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003337 netif_carrier_on(dev);
3338 printk(KERN_INFO "%s: link up.\n", dev->name);
Ayaz Abdulla4ea7f292005-11-11 08:29:59 -05003339 nv_start_rx(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003340 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003341 } else {
3342 if (netif_carrier_ok(dev)) {
3343 netif_carrier_off(dev);
3344 printk(KERN_INFO "%s: link down.\n", dev->name);
3345 nv_stop_rx(dev);
3346 }
3347 }
3348}
3349
3350static void nv_link_irq(struct net_device *dev)
3351{
3352 u8 __iomem *base = get_hwbase(dev);
3353 u32 miistat;
3354
3355 miistat = readl(base + NvRegMIIStatus);
Ayaz Abdullaeb798422008-02-04 15:14:04 -05003356 writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003357 dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
3358
3359 if (miistat & (NVREG_MIISTAT_LINKCHANGE))
3360 nv_linkchange(dev);
3361 dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
3362}
3363
Ayaz Abdulla4db0ee172008-06-09 16:51:06 -07003364static void nv_msi_workaround(struct fe_priv *np)
3365{
3366
3367 /* Need to toggle the msi irq mask within the ethernet device,
3368 * otherwise, future interrupts will not be detected.
3369 */
3370 if (np->msi_flags & NV_MSI_ENABLED) {
3371 u8 __iomem *base = np->base;
3372
3373 writel(0, base + NvRegMSIIrqMask);
3374 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3375 }
3376}
3377
David Howells7d12e782006-10-05 14:55:46 +01003378static irqreturn_t nv_nic_irq(int foo, void *data)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003379{
3380 struct net_device *dev = (struct net_device *) data;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04003381 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003382 u8 __iomem *base = get_hwbase(dev);
3383 u32 events;
3384 int i;
3385
3386 dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
3387
3388 for (i=0; ; i++) {
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003389 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3390 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3391 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3392 } else {
3393 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3394 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3395 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003396 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3397 if (!(events & np->irqmask))
3398 break;
3399
Ayaz Abdulla4db0ee172008-06-09 16:51:06 -07003400 nv_msi_workaround(np);
3401
Ayaz Abdullaa971c322005-11-11 08:30:38 -05003402 spin_lock(&np->lock);
3403 nv_tx_done(dev);
3404 spin_unlock(&np->lock);
Jeff Garzikf3b197a2006-05-26 21:39:03 -04003405
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003406#ifdef CONFIG_FORCEDETH_NAPI
3407 if (events & NVREG_IRQ_RX_ALL) {
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003408 netif_rx_schedule(dev, &np->napi);
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003409
3410 /* Disable furthur receive irq's */
3411 spin_lock(&np->lock);
3412 np->irqmask &= ~NVREG_IRQ_RX_ALL;
3413
3414 if (np->msi_flags & NV_MSI_X_ENABLED)
3415 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3416 else
3417 writel(np->irqmask, base + NvRegIrqMask);
3418 spin_unlock(&np->lock);
3419 }
3420#else
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003421 if (nv_rx_process(dev, RX_WORK_PER_LOOP)) {
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003422 if (unlikely(nv_alloc_rx(dev))) {
3423 spin_lock(&np->lock);
3424 if (!np->in_shutdown)
3425 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3426 spin_unlock(&np->lock);
3427 }
3428 }
3429#endif
3430 if (unlikely(events & NVREG_IRQ_LINK)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003431 spin_lock(&np->lock);
3432 nv_link_irq(dev);
3433 spin_unlock(&np->lock);
3434 }
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003435 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003436 spin_lock(&np->lock);
3437 nv_linkchange(dev);
3438 spin_unlock(&np->lock);
3439 np->link_timeout = jiffies + LINK_TIMEOUT;
3440 }
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003441 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003442 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3443 dev->name, events);
3444 }
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003445 if (unlikely(events & (NVREG_IRQ_UNKNOWN))) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003446 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3447 dev->name, events);
3448 }
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05003449 if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
3450 spin_lock(&np->lock);
3451 /* disable interrupts on the nic */
3452 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3453 writel(0, base + NvRegIrqMask);
3454 else
3455 writel(np->irqmask, base + NvRegIrqMask);
3456 pci_push(base);
3457
3458 if (!np->in_shutdown) {
3459 np->nic_poll_irq = np->irqmask;
3460 np->recover_error = 1;
3461 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3462 }
3463 spin_unlock(&np->lock);
3464 break;
3465 }
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003466 if (unlikely(i > max_interrupt_work)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003467 spin_lock(&np->lock);
3468 /* disable interrupts on the nic */
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003469 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3470 writel(0, base + NvRegIrqMask);
3471 else
3472 writel(np->irqmask, base + NvRegIrqMask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003473 pci_push(base);
3474
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003475 if (!np->in_shutdown) {
3476 np->nic_poll_irq = np->irqmask;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003477 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003478 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003479 spin_unlock(&np->lock);
Timo Jantunen1a2b7332007-08-14 21:56:57 +03003480 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003481 break;
3482 }
3483
3484 }
3485 dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
3486
3487 return IRQ_RETVAL(i);
3488}
3489
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003490/**
3491 * All _optimized functions are used to help increase performance
3492 * (reduce CPU and increase throughput). They use descripter version 3,
3493 * compiler directives, and reduce memory accesses.
3494 */
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003495static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3496{
3497 struct net_device *dev = (struct net_device *) data;
3498 struct fe_priv *np = netdev_priv(dev);
3499 u8 __iomem *base = get_hwbase(dev);
3500 u32 events;
3501 int i;
3502
3503 dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized\n", dev->name);
3504
3505 for (i=0; ; i++) {
3506 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3507 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3508 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3509 } else {
3510 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3511 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3512 }
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003513 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3514 if (!(events & np->irqmask))
3515 break;
3516
Ayaz Abdulla4db0ee172008-06-09 16:51:06 -07003517 nv_msi_workaround(np);
3518
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003519 spin_lock(&np->lock);
Ayaz Abdulla4e16ed12007-01-23 12:00:56 -05003520 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003521 spin_unlock(&np->lock);
3522
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003523#ifdef CONFIG_FORCEDETH_NAPI
3524 if (events & NVREG_IRQ_RX_ALL) {
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003525 netif_rx_schedule(dev, &np->napi);
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003526
3527 /* Disable furthur receive irq's */
3528 spin_lock(&np->lock);
3529 np->irqmask &= ~NVREG_IRQ_RX_ALL;
3530
3531 if (np->msi_flags & NV_MSI_X_ENABLED)
3532 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3533 else
3534 writel(np->irqmask, base + NvRegIrqMask);
3535 spin_unlock(&np->lock);
3536 }
3537#else
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003538 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003539 if (unlikely(nv_alloc_rx_optimized(dev))) {
3540 spin_lock(&np->lock);
3541 if (!np->in_shutdown)
3542 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3543 spin_unlock(&np->lock);
3544 }
3545 }
3546#endif
3547 if (unlikely(events & NVREG_IRQ_LINK)) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003548 spin_lock(&np->lock);
3549 nv_link_irq(dev);
3550 spin_unlock(&np->lock);
3551 }
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003552 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003553 spin_lock(&np->lock);
3554 nv_linkchange(dev);
3555 spin_unlock(&np->lock);
3556 np->link_timeout = jiffies + LINK_TIMEOUT;
3557 }
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003558 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003559 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3560 dev->name, events);
3561 }
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003562 if (unlikely(events & (NVREG_IRQ_UNKNOWN))) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003563 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3564 dev->name, events);
3565 }
3566 if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
3567 spin_lock(&np->lock);
3568 /* disable interrupts on the nic */
3569 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3570 writel(0, base + NvRegIrqMask);
3571 else
3572 writel(np->irqmask, base + NvRegIrqMask);
3573 pci_push(base);
3574
3575 if (!np->in_shutdown) {
3576 np->nic_poll_irq = np->irqmask;
3577 np->recover_error = 1;
3578 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3579 }
3580 spin_unlock(&np->lock);
3581 break;
3582 }
3583
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003584 if (unlikely(i > max_interrupt_work)) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003585 spin_lock(&np->lock);
3586 /* disable interrupts on the nic */
3587 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3588 writel(0, base + NvRegIrqMask);
3589 else
3590 writel(np->irqmask, base + NvRegIrqMask);
3591 pci_push(base);
3592
3593 if (!np->in_shutdown) {
3594 np->nic_poll_irq = np->irqmask;
3595 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3596 }
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003597 spin_unlock(&np->lock);
Timo Jantunen1a2b7332007-08-14 21:56:57 +03003598 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003599 break;
3600 }
3601
3602 }
3603 dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized completed\n", dev->name);
3604
3605 return IRQ_RETVAL(i);
3606}
3607
David Howells7d12e782006-10-05 14:55:46 +01003608static irqreturn_t nv_nic_irq_tx(int foo, void *data)
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003609{
3610 struct net_device *dev = (struct net_device *) data;
3611 struct fe_priv *np = netdev_priv(dev);
3612 u8 __iomem *base = get_hwbase(dev);
3613 u32 events;
3614 int i;
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003615 unsigned long flags;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003616
3617 dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
3618
3619 for (i=0; ; i++) {
3620 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3621 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003622 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
3623 if (!(events & np->irqmask))
3624 break;
3625
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003626 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdulla4e16ed12007-01-23 12:00:56 -05003627 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003628 spin_unlock_irqrestore(&np->lock, flags);
Jeff Garzikf3b197a2006-05-26 21:39:03 -04003629
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003630 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003631 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3632 dev->name, events);
3633 }
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003634 if (unlikely(i > max_interrupt_work)) {
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003635 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003636 /* disable interrupts on the nic */
3637 writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3638 pci_push(base);
3639
3640 if (!np->in_shutdown) {
3641 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3642 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3643 }
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003644 spin_unlock_irqrestore(&np->lock, flags);
Timo Jantunen1a2b7332007-08-14 21:56:57 +03003645 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003646 break;
3647 }
3648
3649 }
3650 dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
3651
3652 return IRQ_RETVAL(i);
3653}
3654
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003655#ifdef CONFIG_FORCEDETH_NAPI
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003656static int nv_napi_poll(struct napi_struct *napi, int budget)
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003657{
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003658 struct fe_priv *np = container_of(napi, struct fe_priv, napi);
3659 struct net_device *dev = np->dev;
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003660 u8 __iomem *base = get_hwbase(dev);
Francois Romieud15e9c42006-12-17 23:03:15 +01003661 unsigned long flags;
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003662 int pkts, retcode;
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003663
Jeff Garzik36b30ea2007-10-16 01:40:30 -04003664 if (!nv_optimized(np)) {
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003665 pkts = nv_rx_process(dev, budget);
Ayaz Abdullae0379a12007-02-20 03:34:30 -05003666 retcode = nv_alloc_rx(dev);
3667 } else {
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003668 pkts = nv_rx_process_optimized(dev, budget);
Ayaz Abdullae0379a12007-02-20 03:34:30 -05003669 retcode = nv_alloc_rx_optimized(dev);
3670 }
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003671
Ayaz Abdullae0379a12007-02-20 03:34:30 -05003672 if (retcode) {
Francois Romieud15e9c42006-12-17 23:03:15 +01003673 spin_lock_irqsave(&np->lock, flags);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003674 if (!np->in_shutdown)
3675 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
Francois Romieud15e9c42006-12-17 23:03:15 +01003676 spin_unlock_irqrestore(&np->lock, flags);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003677 }
3678
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003679 if (pkts < budget) {
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003680 /* re-enable receive interrupts */
Francois Romieud15e9c42006-12-17 23:03:15 +01003681 spin_lock_irqsave(&np->lock, flags);
3682
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003683 __netif_rx_complete(dev, napi);
3684
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003685 np->irqmask |= NVREG_IRQ_RX_ALL;
3686 if (np->msi_flags & NV_MSI_X_ENABLED)
3687 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3688 else
3689 writel(np->irqmask, base + NvRegIrqMask);
Francois Romieud15e9c42006-12-17 23:03:15 +01003690
3691 spin_unlock_irqrestore(&np->lock, flags);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003692 }
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003693 return pkts;
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003694}
3695#endif
3696
3697#ifdef CONFIG_FORCEDETH_NAPI
David Howells7d12e782006-10-05 14:55:46 +01003698static irqreturn_t nv_nic_irq_rx(int foo, void *data)
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003699{
3700 struct net_device *dev = (struct net_device *) data;
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003701 struct fe_priv *np = netdev_priv(dev);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003702 u8 __iomem *base = get_hwbase(dev);
3703 u32 events;
3704
3705 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3706 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3707
3708 if (events) {
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003709 netif_rx_schedule(dev, &np->napi);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003710 /* disable receive interrupts on the nic */
3711 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3712 pci_push(base);
3713 }
3714 return IRQ_HANDLED;
3715}
3716#else
David Howells7d12e782006-10-05 14:55:46 +01003717static irqreturn_t nv_nic_irq_rx(int foo, void *data)
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003718{
3719 struct net_device *dev = (struct net_device *) data;
3720 struct fe_priv *np = netdev_priv(dev);
3721 u8 __iomem *base = get_hwbase(dev);
3722 u32 events;
3723 int i;
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003724 unsigned long flags;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003725
3726 dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
3727
3728 for (i=0; ; i++) {
3729 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3730 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003731 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
3732 if (!(events & np->irqmask))
3733 break;
Jeff Garzikf3b197a2006-05-26 21:39:03 -04003734
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003735 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003736 if (unlikely(nv_alloc_rx_optimized(dev))) {
3737 spin_lock_irqsave(&np->lock, flags);
3738 if (!np->in_shutdown)
3739 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3740 spin_unlock_irqrestore(&np->lock, flags);
3741 }
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003742 }
Jeff Garzikf3b197a2006-05-26 21:39:03 -04003743
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003744 if (unlikely(i > max_interrupt_work)) {
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003745 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003746 /* disable interrupts on the nic */
3747 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3748 pci_push(base);
3749
3750 if (!np->in_shutdown) {
3751 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3752 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3753 }
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003754 spin_unlock_irqrestore(&np->lock, flags);
Timo Jantunen1a2b7332007-08-14 21:56:57 +03003755 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003756 break;
3757 }
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003758 }
3759 dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
3760
3761 return IRQ_RETVAL(i);
3762}
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003763#endif
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003764
David Howells7d12e782006-10-05 14:55:46 +01003765static irqreturn_t nv_nic_irq_other(int foo, void *data)
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003766{
3767 struct net_device *dev = (struct net_device *) data;
3768 struct fe_priv *np = netdev_priv(dev);
3769 u8 __iomem *base = get_hwbase(dev);
3770 u32 events;
3771 int i;
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003772 unsigned long flags;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003773
3774 dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
3775
3776 for (i=0; ; i++) {
3777 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3778 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003779 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3780 if (!(events & np->irqmask))
3781 break;
Jeff Garzikf3b197a2006-05-26 21:39:03 -04003782
Ayaz Abdulla4e16ed12007-01-23 12:00:56 -05003783 /* check tx in case we reached max loop limit in tx isr */
3784 spin_lock_irqsave(&np->lock, flags);
3785 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3786 spin_unlock_irqrestore(&np->lock, flags);
3787
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003788 if (events & NVREG_IRQ_LINK) {
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003789 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003790 nv_link_irq(dev);
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003791 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003792 }
3793 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003794 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003795 nv_linkchange(dev);
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003796 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003797 np->link_timeout = jiffies + LINK_TIMEOUT;
3798 }
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05003799 if (events & NVREG_IRQ_RECOVER_ERROR) {
3800 spin_lock_irq(&np->lock);
3801 /* disable interrupts on the nic */
3802 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3803 pci_push(base);
3804
3805 if (!np->in_shutdown) {
3806 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3807 np->recover_error = 1;
3808 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3809 }
3810 spin_unlock_irq(&np->lock);
3811 break;
3812 }
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003813 if (events & (NVREG_IRQ_UNKNOWN)) {
3814 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3815 dev->name, events);
3816 }
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003817 if (unlikely(i > max_interrupt_work)) {
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003818 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003819 /* disable interrupts on the nic */
3820 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3821 pci_push(base);
3822
3823 if (!np->in_shutdown) {
3824 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3825 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3826 }
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003827 spin_unlock_irqrestore(&np->lock, flags);
Timo Jantunen1a2b7332007-08-14 21:56:57 +03003828 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003829 break;
3830 }
3831
3832 }
3833 dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
3834
3835 return IRQ_RETVAL(i);
3836}
3837
David Howells7d12e782006-10-05 14:55:46 +01003838static irqreturn_t nv_nic_irq_test(int foo, void *data)
Ayaz Abdulla9589c772006-06-10 22:48:13 -04003839{
3840 struct net_device *dev = (struct net_device *) data;
3841 struct fe_priv *np = netdev_priv(dev);
3842 u8 __iomem *base = get_hwbase(dev);
3843 u32 events;
3844
3845 dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
3846
3847 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3848 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3849 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3850 } else {
3851 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3852 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3853 }
3854 pci_push(base);
3855 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3856 if (!(events & NVREG_IRQ_TIMER))
3857 return IRQ_RETVAL(0);
3858
Ayaz Abdulla4db0ee172008-06-09 16:51:06 -07003859 nv_msi_workaround(np);
3860
Ayaz Abdulla9589c772006-06-10 22:48:13 -04003861 spin_lock(&np->lock);
3862 np->intr_test = 1;
3863 spin_unlock(&np->lock);
3864
3865 dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
3866
3867 return IRQ_RETVAL(1);
3868}
3869
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003870static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3871{
3872 u8 __iomem *base = get_hwbase(dev);
3873 int i;
3874 u32 msixmap = 0;
3875
3876 /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3877 * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3878 * the remaining 8 interrupts.
3879 */
3880 for (i = 0; i < 8; i++) {
3881 if ((irqmask >> i) & 0x1) {
3882 msixmap |= vector << (i << 2);
3883 }
3884 }
3885 writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3886
3887 msixmap = 0;
3888 for (i = 0; i < 8; i++) {
3889 if ((irqmask >> (i + 8)) & 0x1) {
3890 msixmap |= vector << (i << 2);
3891 }
3892 }
3893 writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3894}
3895
Ayaz Abdulla9589c772006-06-10 22:48:13 -04003896static int nv_request_irq(struct net_device *dev, int intr_test)
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003897{
3898 struct fe_priv *np = get_nvpriv(dev);
3899 u8 __iomem *base = get_hwbase(dev);
3900 int ret = 1;
3901 int i;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003902 irqreturn_t (*handler)(int foo, void *data);
3903
3904 if (intr_test) {
3905 handler = nv_nic_irq_test;
3906 } else {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04003907 if (nv_optimized(np))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003908 handler = nv_nic_irq_optimized;
3909 else
3910 handler = nv_nic_irq;
3911 }
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003912
3913 if (np->msi_flags & NV_MSI_X_CAPABLE) {
3914 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3915 np->msi_x_entry[i].entry = i;
3916 }
3917 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
3918 np->msi_flags |= NV_MSI_X_ENABLED;
Ayaz Abdulla9589c772006-06-10 22:48:13 -04003919 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003920 /* Request irq for rx handling */
Thomas Gleixner1fb9df52006-07-01 19:29:39 -07003921 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, &nv_nic_irq_rx, IRQF_SHARED, dev->name, dev) != 0) {
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003922 printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
3923 pci_disable_msix(np->pci_dev);
3924 np->msi_flags &= ~NV_MSI_X_ENABLED;
3925 goto out_err;
3926 }
3927 /* Request irq for tx handling */
Thomas Gleixner1fb9df52006-07-01 19:29:39 -07003928 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, &nv_nic_irq_tx, IRQF_SHARED, dev->name, dev) != 0) {
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003929 printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
3930 pci_disable_msix(np->pci_dev);
3931 np->msi_flags &= ~NV_MSI_X_ENABLED;
3932 goto out_free_rx;
3933 }
3934 /* Request irq for link and timer handling */
Thomas Gleixner1fb9df52006-07-01 19:29:39 -07003935 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, &nv_nic_irq_other, IRQF_SHARED, dev->name, dev) != 0) {
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003936 printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
3937 pci_disable_msix(np->pci_dev);
3938 np->msi_flags &= ~NV_MSI_X_ENABLED;
3939 goto out_free_tx;
3940 }
3941 /* map interrupts to their respective vector */
3942 writel(0, base + NvRegMSIXMap0);
3943 writel(0, base + NvRegMSIXMap1);
3944 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
3945 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
3946 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
3947 } else {
3948 /* Request irq for all interrupts */
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003949 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003950 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3951 pci_disable_msix(np->pci_dev);
3952 np->msi_flags &= ~NV_MSI_X_ENABLED;
3953 goto out_err;
3954 }
3955
3956 /* map interrupts to vector 0 */
3957 writel(0, base + NvRegMSIXMap0);
3958 writel(0, base + NvRegMSIXMap1);
3959 }
3960 }
3961 }
3962 if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
3963 if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
3964 np->msi_flags |= NV_MSI_ENABLED;
Manfred Spraula7475902007-10-17 21:52:33 +02003965 dev->irq = np->pci_dev->irq;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003966 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003967 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3968 pci_disable_msi(np->pci_dev);
3969 np->msi_flags &= ~NV_MSI_ENABLED;
Manfred Spraula7475902007-10-17 21:52:33 +02003970 dev->irq = np->pci_dev->irq;
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003971 goto out_err;
3972 }
3973
3974 /* map interrupts to vector 0 */
3975 writel(0, base + NvRegMSIMap0);
3976 writel(0, base + NvRegMSIMap1);
3977 /* enable msi vector 0 */
3978 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3979 }
3980 }
3981 if (ret != 0) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003982 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003983 goto out_err;
Ayaz Abdulla9589c772006-06-10 22:48:13 -04003984
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003985 }
3986
3987 return 0;
3988out_free_tx:
3989 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
3990out_free_rx:
3991 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
3992out_err:
3993 return 1;
3994}
3995
3996static void nv_free_irq(struct net_device *dev)
3997{
3998 struct fe_priv *np = get_nvpriv(dev);
3999 int i;
4000
4001 if (np->msi_flags & NV_MSI_X_ENABLED) {
4002 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
4003 free_irq(np->msi_x_entry[i].vector, dev);
4004 }
4005 pci_disable_msix(np->pci_dev);
4006 np->msi_flags &= ~NV_MSI_X_ENABLED;
4007 } else {
4008 free_irq(np->pci_dev->irq, dev);
4009 if (np->msi_flags & NV_MSI_ENABLED) {
4010 pci_disable_msi(np->pci_dev);
4011 np->msi_flags &= ~NV_MSI_ENABLED;
4012 }
4013 }
4014}
4015
Linus Torvalds1da177e2005-04-16 15:20:36 -07004016static void nv_do_nic_poll(unsigned long data)
4017{
4018 struct net_device *dev = (struct net_device *) data;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04004019 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004020 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05004021 u32 mask = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004022
Linus Torvalds1da177e2005-04-16 15:20:36 -07004023 /*
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05004024 * First disable irq(s) and then
Linus Torvalds1da177e2005-04-16 15:20:36 -07004025 * reenable interrupts on the nic, we have to do this before calling
4026 * nv_nic_irq because that may decide to do otherwise
4027 */
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05004028
Ayaz Abdulla84b39322006-05-20 14:59:48 -07004029 if (!using_multi_irqs(dev)) {
4030 if (np->msi_flags & NV_MSI_X_ENABLED)
Ingo Molnar8688cfc2006-07-03 00:25:39 -07004031 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07004032 else
Manfred Spraula7475902007-10-17 21:52:33 +02004033 disable_irq_lockdep(np->pci_dev->irq);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05004034 mask = np->irqmask;
4035 } else {
4036 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
Ingo Molnar8688cfc2006-07-03 00:25:39 -07004037 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05004038 mask |= NVREG_IRQ_RX_ALL;
4039 }
4040 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
Ingo Molnar8688cfc2006-07-03 00:25:39 -07004041 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05004042 mask |= NVREG_IRQ_TX_ALL;
4043 }
4044 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
Ingo Molnar8688cfc2006-07-03 00:25:39 -07004045 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05004046 mask |= NVREG_IRQ_OTHER;
4047 }
4048 }
4049 np->nic_poll_irq = 0;
4050
Manfred Spraula7475902007-10-17 21:52:33 +02004051 /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
4052
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05004053 if (np->recover_error) {
4054 np->recover_error = 0;
4055 printk(KERN_INFO "forcedeth: MAC in recoverable error state\n");
4056 if (netif_running(dev)) {
4057 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07004058 netif_addr_lock(dev);
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05004059 spin_lock(&np->lock);
4060 /* stop engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004061 nv_stop_rxtx(dev);
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05004062 nv_txrx_reset(dev);
4063 /* drain rx queue */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004064 nv_drain_rxtx(dev);
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05004065 /* reinit driver view of the rx queue */
4066 set_bufsize(dev);
4067 if (nv_init_ring(dev)) {
4068 if (!np->in_shutdown)
4069 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4070 }
4071 /* reinit nic view of the rx queue */
4072 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4073 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4074 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4075 base + NvRegRingSizes);
4076 pci_push(base);
4077 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4078 pci_push(base);
4079
4080 /* restart rx engine */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004081 nv_start_rxtx(dev);
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05004082 spin_unlock(&np->lock);
David S. Millere308a5d2008-07-15 00:13:44 -07004083 netif_addr_unlock(dev);
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05004084 netif_tx_unlock_bh(dev);
4085 }
4086 }
4087
Jeff Garzikf3b197a2006-05-26 21:39:03 -04004088
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05004089 writel(mask, base + NvRegIrqMask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004090 pci_push(base);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05004091
Ayaz Abdulla84b39322006-05-20 14:59:48 -07004092 if (!using_multi_irqs(dev)) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004093 if (nv_optimized(np))
Ayaz Abdullafcc5f262007-03-23 05:49:37 -05004094 nv_nic_irq_optimized(0, dev);
4095 else
4096 nv_nic_irq(0, dev);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07004097 if (np->msi_flags & NV_MSI_X_ENABLED)
Ingo Molnar8688cfc2006-07-03 00:25:39 -07004098 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07004099 else
Manfred Spraula7475902007-10-17 21:52:33 +02004100 enable_irq_lockdep(np->pci_dev->irq);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05004101 } else {
4102 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
David Howells7d12e782006-10-05 14:55:46 +01004103 nv_nic_irq_rx(0, dev);
Ingo Molnar8688cfc2006-07-03 00:25:39 -07004104 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05004105 }
4106 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
David Howells7d12e782006-10-05 14:55:46 +01004107 nv_nic_irq_tx(0, dev);
Ingo Molnar8688cfc2006-07-03 00:25:39 -07004108 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05004109 }
4110 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
David Howells7d12e782006-10-05 14:55:46 +01004111 nv_nic_irq_other(0, dev);
Ingo Molnar8688cfc2006-07-03 00:25:39 -07004112 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05004113 }
4114 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004115}
4116
Michal Schmidt2918c352005-05-12 19:42:06 -04004117#ifdef CONFIG_NET_POLL_CONTROLLER
4118static void nv_poll_controller(struct net_device *dev)
4119{
4120 nv_do_nic_poll((unsigned long) dev);
4121}
4122#endif
4123
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004124static void nv_do_stats_poll(unsigned long data)
4125{
4126 struct net_device *dev = (struct net_device *) data;
4127 struct fe_priv *np = netdev_priv(dev);
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004128
Ayaz Abdulla57fff692007-01-23 12:27:00 -05004129 nv_get_hw_stats(dev);
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004130
4131 if (!np->in_shutdown)
Daniel Drakebfebbb82008-03-18 11:07:18 +00004132 mod_timer(&np->stats_poll,
4133 round_jiffies(jiffies + STATS_INTERVAL));
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004134}
4135
Linus Torvalds1da177e2005-04-16 15:20:36 -07004136static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4137{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04004138 struct fe_priv *np = netdev_priv(dev);
Jeff Garzik3f88ce42007-10-16 04:09:09 -04004139 strcpy(info->driver, DRV_NAME);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004140 strcpy(info->version, FORCEDETH_VERSION);
4141 strcpy(info->bus_info, pci_name(np->pci_dev));
4142}
4143
4144static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4145{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04004146 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004147 wolinfo->supported = WAKE_MAGIC;
4148
4149 spin_lock_irq(&np->lock);
4150 if (np->wolenabled)
4151 wolinfo->wolopts = WAKE_MAGIC;
4152 spin_unlock_irq(&np->lock);
4153}
4154
4155static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4156{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04004157 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004158 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullac42d9df2006-06-10 22:47:52 -04004159 u32 flags = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004160
Linus Torvalds1da177e2005-04-16 15:20:36 -07004161 if (wolinfo->wolopts == 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07004162 np->wolenabled = 0;
Ayaz Abdullac42d9df2006-06-10 22:47:52 -04004163 } else if (wolinfo->wolopts & WAKE_MAGIC) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07004164 np->wolenabled = 1;
Ayaz Abdullac42d9df2006-06-10 22:47:52 -04004165 flags = NVREG_WAKEUPFLAGS_ENABLE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004166 }
Ayaz Abdullac42d9df2006-06-10 22:47:52 -04004167 if (netif_running(dev)) {
4168 spin_lock_irq(&np->lock);
4169 writel(flags, base + NvRegWakeUpFlags);
4170 spin_unlock_irq(&np->lock);
4171 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004172 return 0;
4173}
4174
4175static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4176{
4177 struct fe_priv *np = netdev_priv(dev);
4178 int adv;
4179
4180 spin_lock_irq(&np->lock);
4181 ecmd->port = PORT_MII;
4182 if (!netif_running(dev)) {
4183 /* We do not track link speed / duplex setting if the
4184 * interface is disabled. Force a link check */
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004185 if (nv_update_linkspeed(dev)) {
4186 if (!netif_carrier_ok(dev))
4187 netif_carrier_on(dev);
4188 } else {
4189 if (netif_carrier_ok(dev))
4190 netif_carrier_off(dev);
4191 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004192 }
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004193
4194 if (netif_carrier_ok(dev)) {
4195 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07004196 case NVREG_LINKSPEED_10:
4197 ecmd->speed = SPEED_10;
4198 break;
4199 case NVREG_LINKSPEED_100:
4200 ecmd->speed = SPEED_100;
4201 break;
4202 case NVREG_LINKSPEED_1000:
4203 ecmd->speed = SPEED_1000;
4204 break;
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004205 }
4206 ecmd->duplex = DUPLEX_HALF;
4207 if (np->duplex)
4208 ecmd->duplex = DUPLEX_FULL;
4209 } else {
4210 ecmd->speed = -1;
4211 ecmd->duplex = -1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004212 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004213
4214 ecmd->autoneg = np->autoneg;
4215
4216 ecmd->advertising = ADVERTISED_MII;
4217 if (np->autoneg) {
4218 ecmd->advertising |= ADVERTISED_Autoneg;
4219 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004220 if (adv & ADVERTISE_10HALF)
4221 ecmd->advertising |= ADVERTISED_10baseT_Half;
4222 if (adv & ADVERTISE_10FULL)
4223 ecmd->advertising |= ADVERTISED_10baseT_Full;
4224 if (adv & ADVERTISE_100HALF)
4225 ecmd->advertising |= ADVERTISED_100baseT_Half;
4226 if (adv & ADVERTISE_100FULL)
4227 ecmd->advertising |= ADVERTISED_100baseT_Full;
4228 if (np->gigabit == PHY_GIGABIT) {
4229 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4230 if (adv & ADVERTISE_1000FULL)
4231 ecmd->advertising |= ADVERTISED_1000baseT_Full;
4232 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004233 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004234 ecmd->supported = (SUPPORTED_Autoneg |
4235 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
4236 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
4237 SUPPORTED_MII);
4238 if (np->gigabit == PHY_GIGABIT)
4239 ecmd->supported |= SUPPORTED_1000baseT_Full;
4240
4241 ecmd->phy_address = np->phyaddr;
4242 ecmd->transceiver = XCVR_EXTERNAL;
4243
4244 /* ignore maxtxpkt, maxrxpkt for now */
4245 spin_unlock_irq(&np->lock);
4246 return 0;
4247}
4248
4249static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4250{
4251 struct fe_priv *np = netdev_priv(dev);
4252
4253 if (ecmd->port != PORT_MII)
4254 return -EINVAL;
4255 if (ecmd->transceiver != XCVR_EXTERNAL)
4256 return -EINVAL;
4257 if (ecmd->phy_address != np->phyaddr) {
4258 /* TODO: support switching between multiple phys. Should be
4259 * trivial, but not enabled due to lack of test hardware. */
4260 return -EINVAL;
4261 }
4262 if (ecmd->autoneg == AUTONEG_ENABLE) {
4263 u32 mask;
4264
4265 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4266 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4267 if (np->gigabit == PHY_GIGABIT)
4268 mask |= ADVERTISED_1000baseT_Full;
4269
4270 if ((ecmd->advertising & mask) == 0)
4271 return -EINVAL;
4272
4273 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
4274 /* Note: autonegotiation disable, speed 1000 intentionally
4275 * forbidden - noone should need that. */
4276
4277 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
4278 return -EINVAL;
4279 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
4280 return -EINVAL;
4281 } else {
4282 return -EINVAL;
4283 }
4284
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004285 netif_carrier_off(dev);
4286 if (netif_running(dev)) {
Tobias Diedrich97bff092008-07-03 23:54:56 -07004287 unsigned long flags;
4288
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004289 nv_disable_irq(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004290 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07004291 netif_addr_lock(dev);
Tobias Diedrich97bff092008-07-03 23:54:56 -07004292 /* with plain spinlock lockdep complains */
4293 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004294 /* stop engines */
Tobias Diedrich97bff092008-07-03 23:54:56 -07004295 /* FIXME:
4296 * this can take some time, and interrupts are disabled
4297 * due to spin_lock_irqsave, but let's hope no daemon
4298 * is going to change the settings very often...
4299 * Worst case:
4300 * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX
4301 * + some minor delays, which is up to a second approximately
4302 */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004303 nv_stop_rxtx(dev);
Tobias Diedrich97bff092008-07-03 23:54:56 -07004304 spin_unlock_irqrestore(&np->lock, flags);
David S. Millere308a5d2008-07-15 00:13:44 -07004305 netif_addr_unlock(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004306 netif_tx_unlock_bh(dev);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004307 }
4308
Linus Torvalds1da177e2005-04-16 15:20:36 -07004309 if (ecmd->autoneg == AUTONEG_ENABLE) {
4310 int adv, bmcr;
4311
4312 np->autoneg = 1;
4313
4314 /* advertise only what has been requested */
4315 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04004316 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004317 if (ecmd->advertising & ADVERTISED_10baseT_Half)
4318 adv |= ADVERTISE_10HALF;
4319 if (ecmd->advertising & ADVERTISED_10baseT_Full)
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004320 adv |= ADVERTISE_10FULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004321 if (ecmd->advertising & ADVERTISED_100baseT_Half)
4322 adv |= ADVERTISE_100HALF;
4323 if (ecmd->advertising & ADVERTISED_100baseT_Full)
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004324 adv |= ADVERTISE_100FULL;
4325 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
4326 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4327 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4328 adv |= ADVERTISE_PAUSE_ASYM;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004329 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4330
4331 if (np->gigabit == PHY_GIGABIT) {
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04004332 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004333 adv &= ~ADVERTISE_1000FULL;
4334 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
4335 adv |= ADVERTISE_1000FULL;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04004336 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004337 }
4338
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004339 if (netif_running(dev))
4340 printk(KERN_INFO "%s: link down.\n", dev->name);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004341 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04004342 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4343 bmcr |= BMCR_ANENABLE;
4344 /* reset the phy in order for settings to stick,
4345 * and cause autoneg to start */
4346 if (phy_reset(dev, bmcr)) {
4347 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4348 return -EINVAL;
4349 }
4350 } else {
4351 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4352 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4353 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004354 } else {
4355 int adv, bmcr;
4356
4357 np->autoneg = 0;
4358
4359 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04004360 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004361 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
4362 adv |= ADVERTISE_10HALF;
4363 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004364 adv |= ADVERTISE_10FULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004365 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
4366 adv |= ADVERTISE_100HALF;
4367 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004368 adv |= ADVERTISE_100FULL;
4369 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4370 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
4371 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4372 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4373 }
4374 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
4375 adv |= ADVERTISE_PAUSE_ASYM;
4376 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4377 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004378 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4379 np->fixed_mode = adv;
4380
4381 if (np->gigabit == PHY_GIGABIT) {
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04004382 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004383 adv &= ~ADVERTISE_1000FULL;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04004384 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004385 }
4386
4387 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004388 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
4389 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
Linus Torvalds1da177e2005-04-16 15:20:36 -07004390 bmcr |= BMCR_FULLDPLX;
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004391 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
Linus Torvalds1da177e2005-04-16 15:20:36 -07004392 bmcr |= BMCR_SPEED100;
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004393 if (np->phy_oui == PHY_OUI_MARVELL) {
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04004394 /* reset the phy in order for forced mode settings to stick */
4395 if (phy_reset(dev, bmcr)) {
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004396 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4397 return -EINVAL;
4398 }
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04004399 } else {
4400 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4401 if (netif_running(dev)) {
4402 /* Wait a bit and then reconfigure the nic. */
4403 udelay(10);
4404 nv_linkchange(dev);
4405 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004406 }
4407 }
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004408
4409 if (netif_running(dev)) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004410 nv_start_rxtx(dev);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004411 nv_enable_irq(dev);
4412 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004413
4414 return 0;
4415}
4416
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004417#define FORCEDETH_REGS_VER 1
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004418
4419static int nv_get_regs_len(struct net_device *dev)
4420{
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04004421 struct fe_priv *np = netdev_priv(dev);
4422 return np->register_size;
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004423}
4424
4425static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
4426{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04004427 struct fe_priv *np = netdev_priv(dev);
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004428 u8 __iomem *base = get_hwbase(dev);
4429 u32 *rbuf = buf;
4430 int i;
4431
4432 regs->version = FORCEDETH_REGS_VER;
4433 spin_lock_irq(&np->lock);
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04004434 for (i = 0;i <= np->register_size/sizeof(u32); i++)
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004435 rbuf[i] = readl(base + i*sizeof(u32));
4436 spin_unlock_irq(&np->lock);
4437}
4438
4439static int nv_nway_reset(struct net_device *dev)
4440{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04004441 struct fe_priv *np = netdev_priv(dev);
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004442 int ret;
4443
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004444 if (np->autoneg) {
4445 int bmcr;
4446
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004447 netif_carrier_off(dev);
4448 if (netif_running(dev)) {
4449 nv_disable_irq(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004450 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07004451 netif_addr_lock(dev);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004452 spin_lock(&np->lock);
4453 /* stop engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004454 nv_stop_rxtx(dev);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004455 spin_unlock(&np->lock);
David S. Millere308a5d2008-07-15 00:13:44 -07004456 netif_addr_unlock(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004457 netif_tx_unlock_bh(dev);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004458 printk(KERN_INFO "%s: link down.\n", dev->name);
4459 }
4460
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004461 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04004462 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4463 bmcr |= BMCR_ANENABLE;
4464 /* reset the phy in order for settings to stick*/
4465 if (phy_reset(dev, bmcr)) {
4466 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4467 return -EINVAL;
4468 }
4469 } else {
4470 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4471 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4472 }
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004473
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004474 if (netif_running(dev)) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004475 nv_start_rxtx(dev);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004476 nv_enable_irq(dev);
4477 }
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004478 ret = 0;
4479 } else {
4480 ret = -EINVAL;
4481 }
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004482
4483 return ret;
4484}
4485
Zachary Amsden0674d592006-06-04 02:51:38 -07004486static int nv_set_tso(struct net_device *dev, u32 value)
4487{
4488 struct fe_priv *np = netdev_priv(dev);
4489
4490 if ((np->driver_data & DEV_HAS_CHECKSUM))
4491 return ethtool_op_set_tso(dev, value);
4492 else
Ayaz Abdulla6a788142006-06-10 22:47:26 -04004493 return -EOPNOTSUPP;
Zachary Amsden0674d592006-06-04 02:51:38 -07004494}
Zachary Amsden0674d592006-06-04 02:51:38 -07004495
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004496static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4497{
4498 struct fe_priv *np = netdev_priv(dev);
4499
4500 ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4501 ring->rx_mini_max_pending = 0;
4502 ring->rx_jumbo_max_pending = 0;
4503 ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4504
4505 ring->rx_pending = np->rx_ring_size;
4506 ring->rx_mini_pending = 0;
4507 ring->rx_jumbo_pending = 0;
4508 ring->tx_pending = np->tx_ring_size;
4509}
4510
4511static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4512{
4513 struct fe_priv *np = netdev_priv(dev);
4514 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05004515 u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004516 dma_addr_t ring_addr;
4517
4518 if (ring->rx_pending < RX_RING_MIN ||
4519 ring->tx_pending < TX_RING_MIN ||
4520 ring->rx_mini_pending != 0 ||
4521 ring->rx_jumbo_pending != 0 ||
4522 (np->desc_ver == DESC_VER_1 &&
4523 (ring->rx_pending > RING_MAX_DESC_VER_1 ||
4524 ring->tx_pending > RING_MAX_DESC_VER_1)) ||
4525 (np->desc_ver != DESC_VER_1 &&
4526 (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
4527 ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
4528 return -EINVAL;
4529 }
4530
4531 /* allocate new rings */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004532 if (!nv_optimized(np)) {
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004533 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4534 sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4535 &ring_addr);
4536 } else {
4537 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4538 sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4539 &ring_addr);
4540 }
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05004541 rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
4542 tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
4543 if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004544 /* fall back to old rings */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004545 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07004546 if (rxtx_ring)
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004547 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4548 rxtx_ring, ring_addr);
4549 } else {
4550 if (rxtx_ring)
4551 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4552 rxtx_ring, ring_addr);
4553 }
4554 if (rx_skbuff)
4555 kfree(rx_skbuff);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004556 if (tx_skbuff)
4557 kfree(tx_skbuff);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004558 goto exit;
4559 }
4560
4561 if (netif_running(dev)) {
4562 nv_disable_irq(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004563 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07004564 netif_addr_lock(dev);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004565 spin_lock(&np->lock);
4566 /* stop engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004567 nv_stop_rxtx(dev);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004568 nv_txrx_reset(dev);
4569 /* drain queues */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004570 nv_drain_rxtx(dev);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004571 /* delete queues */
4572 free_rings(dev);
4573 }
4574
4575 /* set new values */
4576 np->rx_ring_size = ring->rx_pending;
4577 np->tx_ring_size = ring->tx_pending;
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004578
4579 if (!nv_optimized(np)) {
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004580 np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
4581 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4582 } else {
4583 np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
4584 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4585 }
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05004586 np->rx_skb = (struct nv_skb_map*)rx_skbuff;
4587 np->tx_skb = (struct nv_skb_map*)tx_skbuff;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004588 np->ring_addr = ring_addr;
4589
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05004590 memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4591 memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004592
4593 if (netif_running(dev)) {
4594 /* reinit driver view of the queues */
4595 set_bufsize(dev);
4596 if (nv_init_ring(dev)) {
4597 if (!np->in_shutdown)
4598 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4599 }
4600
4601 /* reinit nic view of the queues */
4602 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4603 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4604 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4605 base + NvRegRingSizes);
4606 pci_push(base);
4607 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4608 pci_push(base);
4609
4610 /* restart engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004611 nv_start_rxtx(dev);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004612 spin_unlock(&np->lock);
David S. Millere308a5d2008-07-15 00:13:44 -07004613 netif_addr_unlock(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004614 netif_tx_unlock_bh(dev);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004615 nv_enable_irq(dev);
4616 }
4617 return 0;
4618exit:
4619 return -ENOMEM;
4620}
4621
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004622static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4623{
4624 struct fe_priv *np = netdev_priv(dev);
4625
4626 pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4627 pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4628 pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4629}
4630
4631static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4632{
4633 struct fe_priv *np = netdev_priv(dev);
4634 int adv, bmcr;
4635
4636 if ((!np->autoneg && np->duplex == 0) ||
4637 (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4638 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
4639 dev->name);
4640 return -EINVAL;
4641 }
4642 if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4643 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
4644 return -EINVAL;
4645 }
4646
4647 netif_carrier_off(dev);
4648 if (netif_running(dev)) {
4649 nv_disable_irq(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004650 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07004651 netif_addr_lock(dev);
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004652 spin_lock(&np->lock);
4653 /* stop engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004654 nv_stop_rxtx(dev);
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004655 spin_unlock(&np->lock);
David S. Millere308a5d2008-07-15 00:13:44 -07004656 netif_addr_unlock(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004657 netif_tx_unlock_bh(dev);
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004658 }
4659
4660 np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4661 if (pause->rx_pause)
4662 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4663 if (pause->tx_pause)
4664 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4665
4666 if (np->autoneg && pause->autoneg) {
4667 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4668
4669 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4670 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4671 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
4672 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4673 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4674 adv |= ADVERTISE_PAUSE_ASYM;
4675 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4676
4677 if (netif_running(dev))
4678 printk(KERN_INFO "%s: link down.\n", dev->name);
4679 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4680 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4681 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4682 } else {
4683 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4684 if (pause->rx_pause)
4685 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4686 if (pause->tx_pause)
4687 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4688
4689 if (!netif_running(dev))
4690 nv_update_linkspeed(dev);
4691 else
4692 nv_update_pause(dev, np->pause_flags);
4693 }
4694
4695 if (netif_running(dev)) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004696 nv_start_rxtx(dev);
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004697 nv_enable_irq(dev);
4698 }
4699 return 0;
4700}
4701
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004702static u32 nv_get_rx_csum(struct net_device *dev)
4703{
4704 struct fe_priv *np = netdev_priv(dev);
Ayaz Abdullaf2ad2d92006-08-24 17:35:41 -04004705 return (np->rx_csum) != 0;
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004706}
4707
4708static int nv_set_rx_csum(struct net_device *dev, u32 data)
4709{
4710 struct fe_priv *np = netdev_priv(dev);
4711 u8 __iomem *base = get_hwbase(dev);
4712 int retcode = 0;
4713
4714 if (np->driver_data & DEV_HAS_CHECKSUM) {
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004715 if (data) {
Ayaz Abdullaf2ad2d92006-08-24 17:35:41 -04004716 np->rx_csum = 1;
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004717 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004718 } else {
Ayaz Abdullaf2ad2d92006-08-24 17:35:41 -04004719 np->rx_csum = 0;
4720 /* vlan is dependent on rx checksum offload */
4721 if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
4722 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004723 }
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004724 if (netif_running(dev)) {
4725 spin_lock_irq(&np->lock);
4726 writel(np->txrxctl_bits, base + NvRegTxRxControl);
4727 spin_unlock_irq(&np->lock);
4728 }
4729 } else {
4730 return -EINVAL;
4731 }
4732
4733 return retcode;
4734}
4735
4736static int nv_set_tx_csum(struct net_device *dev, u32 data)
4737{
4738 struct fe_priv *np = netdev_priv(dev);
4739
4740 if (np->driver_data & DEV_HAS_CHECKSUM)
4741 return ethtool_op_set_tx_hw_csum(dev, data);
4742 else
4743 return -EOPNOTSUPP;
4744}
4745
4746static int nv_set_sg(struct net_device *dev, u32 data)
4747{
4748 struct fe_priv *np = netdev_priv(dev);
4749
4750 if (np->driver_data & DEV_HAS_CHECKSUM)
4751 return ethtool_op_set_sg(dev, data);
4752 else
4753 return -EOPNOTSUPP;
4754}
4755
Jeff Garzikb9f2c042007-10-03 18:07:32 -07004756static int nv_get_sset_count(struct net_device *dev, int sset)
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004757{
4758 struct fe_priv *np = netdev_priv(dev);
4759
Jeff Garzikb9f2c042007-10-03 18:07:32 -07004760 switch (sset) {
4761 case ETH_SS_TEST:
4762 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4763 return NV_TEST_COUNT_EXTENDED;
4764 else
4765 return NV_TEST_COUNT_BASE;
4766 case ETH_SS_STATS:
4767 if (np->driver_data & DEV_HAS_STATISTICS_V1)
4768 return NV_DEV_STATISTICS_V1_COUNT;
4769 else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4770 return NV_DEV_STATISTICS_V2_COUNT;
Ayaz Abdulla9c662432008-08-06 12:11:42 -04004771 else if (np->driver_data & DEV_HAS_STATISTICS_V3)
4772 return NV_DEV_STATISTICS_V3_COUNT;
Jeff Garzikb9f2c042007-10-03 18:07:32 -07004773 else
4774 return 0;
4775 default:
4776 return -EOPNOTSUPP;
4777 }
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004778}
4779
4780static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
4781{
4782 struct fe_priv *np = netdev_priv(dev);
4783
4784 /* update stats */
4785 nv_do_stats_poll((unsigned long)dev);
4786
Jeff Garzikb9f2c042007-10-03 18:07:32 -07004787 memcpy(buffer, &np->estats, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004788}
4789
4790static int nv_link_test(struct net_device *dev)
4791{
4792 struct fe_priv *np = netdev_priv(dev);
4793 int mii_status;
4794
4795 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4796 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4797
4798 /* check phy link status */
4799 if (!(mii_status & BMSR_LSTATUS))
4800 return 0;
4801 else
4802 return 1;
4803}
4804
4805static int nv_register_test(struct net_device *dev)
4806{
4807 u8 __iomem *base = get_hwbase(dev);
4808 int i = 0;
4809 u32 orig_read, new_read;
4810
4811 do {
4812 orig_read = readl(base + nv_registers_test[i].reg);
4813
4814 /* xor with mask to toggle bits */
4815 orig_read ^= nv_registers_test[i].mask;
4816
4817 writel(orig_read, base + nv_registers_test[i].reg);
4818
4819 new_read = readl(base + nv_registers_test[i].reg);
4820
4821 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4822 return 0;
4823
4824 /* restore original value */
4825 orig_read ^= nv_registers_test[i].mask;
4826 writel(orig_read, base + nv_registers_test[i].reg);
4827
4828 } while (nv_registers_test[++i].reg != 0);
4829
4830 return 1;
4831}
4832
4833static int nv_interrupt_test(struct net_device *dev)
4834{
4835 struct fe_priv *np = netdev_priv(dev);
4836 u8 __iomem *base = get_hwbase(dev);
4837 int ret = 1;
4838 int testcnt;
4839 u32 save_msi_flags, save_poll_interval = 0;
4840
4841 if (netif_running(dev)) {
4842 /* free current irq */
4843 nv_free_irq(dev);
4844 save_poll_interval = readl(base+NvRegPollingInterval);
4845 }
4846
4847 /* flag to test interrupt handler */
4848 np->intr_test = 0;
4849
4850 /* setup test irq */
4851 save_msi_flags = np->msi_flags;
4852 np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4853 np->msi_flags |= 0x001; /* setup 1 vector */
4854 if (nv_request_irq(dev, 1))
4855 return 0;
4856
4857 /* setup timer interrupt */
4858 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4859 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4860
4861 nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4862
4863 /* wait for at least one interrupt */
4864 msleep(100);
4865
4866 spin_lock_irq(&np->lock);
4867
4868 /* flag should be set within ISR */
4869 testcnt = np->intr_test;
4870 if (!testcnt)
4871 ret = 2;
4872
4873 nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4874 if (!(np->msi_flags & NV_MSI_X_ENABLED))
4875 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4876 else
4877 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4878
4879 spin_unlock_irq(&np->lock);
4880
4881 nv_free_irq(dev);
4882
4883 np->msi_flags = save_msi_flags;
4884
4885 if (netif_running(dev)) {
4886 writel(save_poll_interval, base + NvRegPollingInterval);
4887 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4888 /* restore original irq */
4889 if (nv_request_irq(dev, 0))
4890 return 0;
4891 }
4892
4893 return ret;
4894}
4895
4896static int nv_loopback_test(struct net_device *dev)
4897{
4898 struct fe_priv *np = netdev_priv(dev);
4899 u8 __iomem *base = get_hwbase(dev);
4900 struct sk_buff *tx_skb, *rx_skb;
4901 dma_addr_t test_dma_addr;
4902 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07004903 u32 flags;
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004904 int len, i, pkt_len;
4905 u8 *pkt_data;
4906 u32 filter_flags = 0;
4907 u32 misc1_flags = 0;
4908 int ret = 1;
4909
4910 if (netif_running(dev)) {
4911 nv_disable_irq(dev);
4912 filter_flags = readl(base + NvRegPacketFilterFlags);
4913 misc1_flags = readl(base + NvRegMisc1);
4914 } else {
4915 nv_txrx_reset(dev);
4916 }
4917
4918 /* reinit driver view of the rx queue */
4919 set_bufsize(dev);
4920 nv_init_ring(dev);
4921
4922 /* setup hardware for loopback */
4923 writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
4924 writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
4925
4926 /* reinit nic view of the rx queue */
4927 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4928 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4929 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4930 base + NvRegRingSizes);
4931 pci_push(base);
4932
4933 /* restart rx engine */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004934 nv_start_rxtx(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004935
4936 /* setup packet for tx */
4937 pkt_len = ETH_DATA_LEN;
4938 tx_skb = dev_alloc_skb(pkt_len);
Jesper Juhl46798c82006-09-25 16:39:24 -07004939 if (!tx_skb) {
4940 printk(KERN_ERR "dev_alloc_skb() failed during loopback test"
4941 " of %s\n", dev->name);
4942 ret = 0;
4943 goto out;
4944 }
Arnaldo Carvalho de Melo8b5be262007-03-20 12:08:20 -03004945 test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
4946 skb_tailroom(tx_skb),
4947 PCI_DMA_FROMDEVICE);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004948 pkt_data = skb_put(tx_skb, pkt_len);
4949 for (i = 0; i < pkt_len; i++)
4950 pkt_data[i] = (u8)(i & 0xff);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004951
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004952 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07004953 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
4954 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004955 } else {
Al Viro5bb7ea22007-12-09 16:06:41 +00004956 np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));
4957 np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07004958 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004959 }
4960 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4961 pci_push(get_hwbase(dev));
4962
4963 msleep(500);
4964
4965 /* check for rx of the packet */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004966 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07004967 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004968 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
4969
4970 } else {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07004971 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004972 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
4973 }
4974
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07004975 if (flags & NV_RX_AVAIL) {
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004976 ret = 0;
4977 } else if (np->desc_ver == DESC_VER_1) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07004978 if (flags & NV_RX_ERROR)
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004979 ret = 0;
4980 } else {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07004981 if (flags & NV_RX2_ERROR) {
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004982 ret = 0;
4983 }
4984 }
4985
4986 if (ret) {
4987 if (len != pkt_len) {
4988 ret = 0;
4989 dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
4990 dev->name, len, pkt_len);
4991 } else {
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05004992 rx_skb = np->rx_skb[0].skb;
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004993 for (i = 0; i < pkt_len; i++) {
4994 if (rx_skb->data[i] != (u8)(i & 0xff)) {
4995 ret = 0;
4996 dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
4997 dev->name, i);
4998 break;
4999 }
5000 }
5001 }
5002 } else {
5003 dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
5004 }
5005
5006 pci_unmap_page(np->pci_dev, test_dma_addr,
Arnaldo Carvalho de Melo4305b542007-04-19 20:43:29 -07005007 (skb_end_pointer(tx_skb) - tx_skb->data),
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005008 PCI_DMA_TODEVICE);
5009 dev_kfree_skb_any(tx_skb);
Jesper Juhl46798c82006-09-25 16:39:24 -07005010 out:
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005011 /* stop engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005012 nv_stop_rxtx(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005013 nv_txrx_reset(dev);
5014 /* drain rx queue */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005015 nv_drain_rxtx(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005016
5017 if (netif_running(dev)) {
5018 writel(misc1_flags, base + NvRegMisc1);
5019 writel(filter_flags, base + NvRegPacketFilterFlags);
5020 nv_enable_irq(dev);
5021 }
5022
5023 return ret;
5024}
5025
5026static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
5027{
5028 struct fe_priv *np = netdev_priv(dev);
5029 u8 __iomem *base = get_hwbase(dev);
5030 int result;
Jeff Garzikb9f2c042007-10-03 18:07:32 -07005031 memset(buffer, 0, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(u64));
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005032
5033 if (!nv_link_test(dev)) {
5034 test->flags |= ETH_TEST_FL_FAILED;
5035 buffer[0] = 1;
5036 }
5037
5038 if (test->flags & ETH_TEST_FL_OFFLINE) {
5039 if (netif_running(dev)) {
5040 netif_stop_queue(dev);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07005041#ifdef CONFIG_FORCEDETH_NAPI
5042 napi_disable(&np->napi);
5043#endif
Herbert Xu58dfd9c2006-06-21 10:53:54 +10005044 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07005045 netif_addr_lock(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005046 spin_lock_irq(&np->lock);
5047 nv_disable_hw_interrupts(dev, np->irqmask);
5048 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
5049 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5050 } else {
5051 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
5052 }
5053 /* stop engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005054 nv_stop_rxtx(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005055 nv_txrx_reset(dev);
5056 /* drain rx queue */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005057 nv_drain_rxtx(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005058 spin_unlock_irq(&np->lock);
David S. Millere308a5d2008-07-15 00:13:44 -07005059 netif_addr_unlock(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10005060 netif_tx_unlock_bh(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005061 }
5062
5063 if (!nv_register_test(dev)) {
5064 test->flags |= ETH_TEST_FL_FAILED;
5065 buffer[1] = 1;
5066 }
5067
5068 result = nv_interrupt_test(dev);
5069 if (result != 1) {
5070 test->flags |= ETH_TEST_FL_FAILED;
5071 buffer[2] = 1;
5072 }
5073 if (result == 0) {
5074 /* bail out */
5075 return;
5076 }
5077
5078 if (!nv_loopback_test(dev)) {
5079 test->flags |= ETH_TEST_FL_FAILED;
5080 buffer[3] = 1;
5081 }
5082
5083 if (netif_running(dev)) {
5084 /* reinit driver view of the rx queue */
5085 set_bufsize(dev);
5086 if (nv_init_ring(dev)) {
5087 if (!np->in_shutdown)
5088 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5089 }
5090 /* reinit nic view of the rx queue */
5091 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5092 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5093 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5094 base + NvRegRingSizes);
5095 pci_push(base);
5096 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5097 pci_push(base);
5098 /* restart rx engine */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005099 nv_start_rxtx(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005100 netif_start_queue(dev);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07005101#ifdef CONFIG_FORCEDETH_NAPI
5102 napi_enable(&np->napi);
5103#endif
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005104 nv_enable_hw_interrupts(dev, np->irqmask);
5105 }
5106 }
5107}
5108
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005109static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
5110{
5111 switch (stringset) {
5112 case ETH_SS_STATS:
Jeff Garzikb9f2c042007-10-03 18:07:32 -07005113 memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005114 break;
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005115 case ETH_SS_TEST:
Jeff Garzikb9f2c042007-10-03 18:07:32 -07005116 memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005117 break;
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005118 }
5119}
5120
Jeff Garzik7282d492006-09-13 14:30:00 -04005121static const struct ethtool_ops ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07005122 .get_drvinfo = nv_get_drvinfo,
5123 .get_link = ethtool_op_get_link,
5124 .get_wol = nv_get_wol,
5125 .set_wol = nv_set_wol,
5126 .get_settings = nv_get_settings,
5127 .set_settings = nv_set_settings,
Manfred Sprauldc8216c2005-07-31 18:26:05 +02005128 .get_regs_len = nv_get_regs_len,
5129 .get_regs = nv_get_regs,
5130 .nway_reset = nv_nway_reset,
Ayaz Abdulla6a788142006-06-10 22:47:26 -04005131 .set_tso = nv_set_tso,
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005132 .get_ringparam = nv_get_ringparam,
5133 .set_ringparam = nv_set_ringparam,
Ayaz Abdullab6d07732006-06-10 22:47:42 -04005134 .get_pauseparam = nv_get_pauseparam,
5135 .set_pauseparam = nv_set_pauseparam,
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04005136 .get_rx_csum = nv_get_rx_csum,
5137 .set_rx_csum = nv_set_rx_csum,
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04005138 .set_tx_csum = nv_set_tx_csum,
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04005139 .set_sg = nv_set_sg,
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005140 .get_strings = nv_get_strings,
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005141 .get_ethtool_stats = nv_get_ethtool_stats,
Jeff Garzikb9f2c042007-10-03 18:07:32 -07005142 .get_sset_count = nv_get_sset_count,
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005143 .self_test = nv_self_test,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005144};
5145
Ayaz Abdullaee407b02006-02-04 13:13:17 -05005146static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
5147{
5148 struct fe_priv *np = get_nvpriv(dev);
5149
5150 spin_lock_irq(&np->lock);
5151
5152 /* save vlan group */
5153 np->vlangrp = grp;
5154
5155 if (grp) {
5156 /* enable vlan on MAC */
5157 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
5158 } else {
5159 /* disable vlan on MAC */
5160 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
5161 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
5162 }
5163
5164 writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5165
5166 spin_unlock_irq(&np->lock);
Stephen Hemminger25805dc2007-06-01 09:44:01 -07005167}
Ayaz Abdullaee407b02006-02-04 13:13:17 -05005168
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005169/* The mgmt unit and driver use a semaphore to access the phy during init */
5170static int nv_mgmt_acquire_sema(struct net_device *dev)
5171{
5172 u8 __iomem *base = get_hwbase(dev);
5173 int i;
5174 u32 tx_ctrl, mgmt_sema;
5175
5176 for (i = 0; i < 10; i++) {
5177 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
5178 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
5179 break;
5180 msleep(500);
5181 }
5182
5183 if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
5184 return 0;
5185
5186 for (i = 0; i < 2; i++) {
5187 tx_ctrl = readl(base + NvRegTransmitterControl);
5188 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
5189 writel(tx_ctrl, base + NvRegTransmitterControl);
5190
5191 /* verify that semaphore was acquired */
5192 tx_ctrl = readl(base + NvRegTransmitterControl);
5193 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
5194 ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE))
5195 return 1;
5196 else
5197 udelay(50);
5198 }
5199
5200 return 0;
5201}
5202
Linus Torvalds1da177e2005-04-16 15:20:36 -07005203static int nv_open(struct net_device *dev)
5204{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04005205 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005206 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05005207 int ret = 1;
5208 int oom, i;
Ayaz Abdullaa4336862008-04-18 13:50:43 -07005209 u32 low;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005210
5211 dprintk(KERN_DEBUG "nv_open: begin\n");
5212
Ayaz Abdullaf1489652006-07-31 12:04:45 -04005213 /* erase previous misconfiguration */
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005214 if (np->driver_data & DEV_HAS_POWER_CNTRL)
5215 nv_mac_reset(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005216 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5217 writel(0, base + NvRegMulticastAddrB);
Ayaz Abdullabb9a4fd2008-01-13 16:03:04 -05005218 writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5219 writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005220 writel(0, base + NvRegPacketFilterFlags);
5221
5222 writel(0, base + NvRegTransmitterControl);
5223 writel(0, base + NvRegReceiverControl);
5224
5225 writel(0, base + NvRegAdapterControl);
5226
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04005227 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
5228 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
5229
Ayaz Abdullaf1489652006-07-31 12:04:45 -04005230 /* initialize descriptor rings */
Manfred Sprauld81c0982005-07-31 18:20:30 +02005231 set_bufsize(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005232 oom = nv_init_ring(dev);
5233
5234 writel(0, base + NvRegLinkSpeed);
Ayaz Abdulla5070d342006-07-31 12:05:01 -04005235 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005236 nv_txrx_reset(dev);
5237 writel(0, base + NvRegUnknownSetupReg6);
5238
5239 np->in_shutdown = 0;
5240
Ayaz Abdullaf1489652006-07-31 12:04:45 -04005241 /* give hw rings */
Ayaz Abdulla0832b252006-02-04 13:13:26 -05005242 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005243 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
Linus Torvalds1da177e2005-04-16 15:20:36 -07005244 base + NvRegRingSizes);
5245
Linus Torvalds1da177e2005-04-16 15:20:36 -07005246 writel(np->linkspeed, base + NvRegLinkSpeed);
Ayaz Abdulla95d161c2006-07-06 16:46:25 -04005247 if (np->desc_ver == DESC_VER_1)
5248 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
5249 else
5250 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005251 writel(np->txrxctl_bits, base + NvRegTxRxControl);
Ayaz Abdullaee407b02006-02-04 13:13:17 -05005252 writel(np->vlanctl_bits, base + NvRegVlanControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005253 pci_push(base);
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005254 writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005255 reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
5256 NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
5257 KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
5258
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005259 writel(0, base + NvRegMIIMask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005260 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
Ayaz Abdullaeb798422008-02-04 15:14:04 -05005261 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005262
Linus Torvalds1da177e2005-04-16 15:20:36 -07005263 writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
5264 writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
5265 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
Manfred Sprauld81c0982005-07-31 18:20:30 +02005266 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005267
5268 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
Ayaz Abdullaa4336862008-04-18 13:50:43 -07005269
5270 get_random_bytes(&low, sizeof(low));
5271 low &= NVREG_SLOTTIME_MASK;
5272 if (np->desc_ver == DESC_VER_1) {
5273 writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime);
5274 } else {
5275 if (!(np->driver_data & DEV_HAS_GEAR_MODE)) {
5276 /* setup legacy backoff */
5277 writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime);
5278 } else {
5279 writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime);
5280 nv_gear_backoff_reseed(dev);
5281 }
5282 }
Ayaz Abdulla9744e212006-07-06 16:45:58 -04005283 writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
5284 writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
Ayaz Abdullaa971c322005-11-11 08:30:38 -05005285 if (poll_interval == -1) {
5286 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
5287 writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
5288 else
5289 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
5290 }
5291 else
5292 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005293 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5294 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
5295 base + NvRegAdapterControl);
5296 writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005297 writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
Ayaz Abdullac42d9df2006-06-10 22:47:52 -04005298 if (np->wolenabled)
5299 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005300
5301 i = readl(base + NvRegPowerState);
5302 if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
5303 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
5304
5305 pci_push(base);
5306 udelay(10);
5307 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
5308
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005309 nv_disable_hw_interrupts(dev, np->irqmask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005310 pci_push(base);
Ayaz Abdullaeb798422008-02-04 15:14:04 -05005311 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005312 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5313 pci_push(base);
5314
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005315 if (nv_request_irq(dev, 0)) {
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005316 goto out_drain;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05005317 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005318
5319 /* ask for interrupts */
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005320 nv_enable_hw_interrupts(dev, np->irqmask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005321
5322 spin_lock_irq(&np->lock);
5323 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5324 writel(0, base + NvRegMulticastAddrB);
Ayaz Abdullabb9a4fd2008-01-13 16:03:04 -05005325 writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5326 writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005327 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5328 /* One manual link speed update: Interrupts are enabled, future link
5329 * speed changes cause interrupts and are handled by nv_link_irq().
5330 */
5331 {
5332 u32 miistat;
5333 miistat = readl(base + NvRegMIIStatus);
Ayaz Abdullaeb798422008-02-04 15:14:04 -05005334 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005335 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
5336 }
Manfred Spraul1b1b3c92005-08-06 23:47:55 +02005337 /* set linkspeed to invalid value, thus force nv_update_linkspeed
5338 * to init hw */
5339 np->linkspeed = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005340 ret = nv_update_linkspeed(dev);
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005341 nv_start_rxtx(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005342 netif_start_queue(dev);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07005343#ifdef CONFIG_FORCEDETH_NAPI
5344 napi_enable(&np->napi);
5345#endif
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07005346
Linus Torvalds1da177e2005-04-16 15:20:36 -07005347 if (ret) {
5348 netif_carrier_on(dev);
5349 } else {
Ed Swierkf7ab6972007-09-28 22:42:13 -07005350 printk(KERN_INFO "%s: no link during initialization.\n", dev->name);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005351 netif_carrier_off(dev);
5352 }
5353 if (oom)
5354 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005355
5356 /* start statistics timer */
Ayaz Abdulla9c662432008-08-06 12:11:42 -04005357 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
Daniel Drakebfebbb82008-03-18 11:07:18 +00005358 mod_timer(&np->stats_poll,
5359 round_jiffies(jiffies + STATS_INTERVAL));
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005360
Linus Torvalds1da177e2005-04-16 15:20:36 -07005361 spin_unlock_irq(&np->lock);
5362
5363 return 0;
5364out_drain:
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005365 nv_drain_rxtx(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005366 return ret;
5367}
5368
5369static int nv_close(struct net_device *dev)
5370{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04005371 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005372 u8 __iomem *base;
5373
5374 spin_lock_irq(&np->lock);
5375 np->in_shutdown = 1;
5376 spin_unlock_irq(&np->lock);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07005377#ifdef CONFIG_FORCEDETH_NAPI
5378 napi_disable(&np->napi);
5379#endif
Manfred Spraula7475902007-10-17 21:52:33 +02005380 synchronize_irq(np->pci_dev->irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005381
5382 del_timer_sync(&np->oom_kick);
5383 del_timer_sync(&np->nic_poll);
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005384 del_timer_sync(&np->stats_poll);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005385
5386 netif_stop_queue(dev);
5387 spin_lock_irq(&np->lock);
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005388 nv_stop_rxtx(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005389 nv_txrx_reset(dev);
5390
5391 /* disable interrupts on the nic or we will lock up */
5392 base = get_hwbase(dev);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005393 nv_disable_hw_interrupts(dev, np->irqmask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005394 pci_push(base);
5395 dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
5396
5397 spin_unlock_irq(&np->lock);
5398
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005399 nv_free_irq(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005400
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005401 nv_drain_rxtx(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005402
Tim Mann2cc49a52007-06-14 13:16:38 -07005403 if (np->wolenabled) {
5404 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005405 nv_start_rx(dev);
Tim Mann2cc49a52007-06-14 13:16:38 -07005406 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005407
5408 /* FIXME: power down nic */
5409
5410 return 0;
5411}
5412
5413static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
5414{
5415 struct net_device *dev;
5416 struct fe_priv *np;
5417 unsigned long addr;
5418 u8 __iomem *base;
5419 int err, i;
Ayaz Abdulla5070d342006-07-31 12:05:01 -04005420 u32 powerstate, txreg;
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005421 u32 phystate_orig = 0, phystate;
5422 int phyinitialized = 0;
Joe Perches0795af52007-10-03 17:59:30 -07005423 DECLARE_MAC_BUF(mac);
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005424 static int printed_version;
5425
5426 if (!printed_version++)
5427 printk(KERN_INFO "%s: Reverse Engineered nForce ethernet"
5428 " driver. Version %s.\n", DRV_NAME, FORCEDETH_VERSION);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005429
5430 dev = alloc_etherdev(sizeof(struct fe_priv));
5431 err = -ENOMEM;
5432 if (!dev)
5433 goto out;
5434
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04005435 np = netdev_priv(dev);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07005436 np->dev = dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005437 np->pci_dev = pci_dev;
5438 spin_lock_init(&np->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005439 SET_NETDEV_DEV(dev, &pci_dev->dev);
5440
5441 init_timer(&np->oom_kick);
5442 np->oom_kick.data = (unsigned long) dev;
5443 np->oom_kick.function = &nv_do_rx_refill; /* timer handler */
5444 init_timer(&np->nic_poll);
5445 np->nic_poll.data = (unsigned long) dev;
5446 np->nic_poll.function = &nv_do_nic_poll; /* timer handler */
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005447 init_timer(&np->stats_poll);
5448 np->stats_poll.data = (unsigned long) dev;
5449 np->stats_poll.function = &nv_do_stats_poll; /* timer handler */
Linus Torvalds1da177e2005-04-16 15:20:36 -07005450
5451 err = pci_enable_device(pci_dev);
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005452 if (err)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005453 goto out_free;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005454
5455 pci_set_master(pci_dev);
5456
5457 err = pci_request_regions(pci_dev, DRV_NAME);
5458 if (err < 0)
5459 goto out_disable;
5460
Ayaz Abdulla9c662432008-08-06 12:11:42 -04005461 if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
Ayaz Abdulla57fff692007-01-23 12:27:00 -05005462 np->register_size = NV_PCI_REGSZ_VER3;
5463 else if (id->driver_data & DEV_HAS_STATISTICS_V1)
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005464 np->register_size = NV_PCI_REGSZ_VER2;
5465 else
5466 np->register_size = NV_PCI_REGSZ_VER1;
5467
Linus Torvalds1da177e2005-04-16 15:20:36 -07005468 err = -EINVAL;
5469 addr = 0;
5470 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5471 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
5472 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
5473 pci_resource_len(pci_dev, i),
5474 pci_resource_flags(pci_dev, i));
5475 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005476 pci_resource_len(pci_dev, i) >= np->register_size) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07005477 addr = pci_resource_start(pci_dev, i);
5478 break;
5479 }
5480 }
5481 if (i == DEVICE_COUNT_RESOURCE) {
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005482 dev_printk(KERN_INFO, &pci_dev->dev,
5483 "Couldn't find register window\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07005484 goto out_relreg;
5485 }
5486
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005487 /* copy of driver data */
5488 np->driver_data = id->driver_data;
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04005489 /* copy of device id */
5490 np->device_id = id->device;
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005491
Linus Torvalds1da177e2005-04-16 15:20:36 -07005492 /* handle different descriptor versions */
Manfred Spraulee733622005-07-31 18:32:26 +02005493 if (id->driver_data & DEV_HAS_HIGH_DMA) {
5494 /* packet format 3: supports 40-bit addressing */
5495 np->desc_ver = DESC_VER_3;
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005496 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -04005497 if (dma_64bit) {
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005498 if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK))
5499 dev_printk(KERN_INFO, &pci_dev->dev,
5500 "64-bit DMA failed, using 32-bit addressing\n");
5501 else
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -04005502 dev->features |= NETIF_F_HIGHDMA;
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -04005503 if (pci_set_consistent_dma_mask(pci_dev, DMA_39BIT_MASK)) {
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005504 dev_printk(KERN_INFO, &pci_dev->dev,
5505 "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -04005506 }
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005507 }
Manfred Spraulee733622005-07-31 18:32:26 +02005508 } else if (id->driver_data & DEV_HAS_LARGEDESC) {
5509 /* packet format 2: supports jumbo frames */
Linus Torvalds1da177e2005-04-16 15:20:36 -07005510 np->desc_ver = DESC_VER_2;
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005511 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
Manfred Spraulee733622005-07-31 18:32:26 +02005512 } else {
5513 /* original packet format */
5514 np->desc_ver = DESC_VER_1;
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005515 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
Manfred Sprauld81c0982005-07-31 18:20:30 +02005516 }
Manfred Spraulee733622005-07-31 18:32:26 +02005517
5518 np->pkt_limit = NV_PKTLIMIT_1;
5519 if (id->driver_data & DEV_HAS_LARGEDESC)
5520 np->pkt_limit = NV_PKTLIMIT_2;
5521
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005522 if (id->driver_data & DEV_HAS_CHECKSUM) {
Ayaz Abdullaf2ad2d92006-08-24 17:35:41 -04005523 np->rx_csum = 1;
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005524 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
Ayaz Abdullaedcfe5f2008-08-20 16:34:37 -07005525 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
Ayaz Abdullafa454592006-01-05 22:45:45 -08005526 dev->features |= NETIF_F_TSO;
Ayaz Abdulla21828162007-01-23 12:27:21 -05005527 }
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005528
Ayaz Abdullaee407b02006-02-04 13:13:17 -05005529 np->vlanctl_bits = 0;
5530 if (id->driver_data & DEV_HAS_VLAN) {
5531 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
5532 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
5533 dev->vlan_rx_register = nv_vlan_rx_register;
Ayaz Abdullaee407b02006-02-04 13:13:17 -05005534 }
5535
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05005536 np->msi_flags = 0;
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -04005537 if ((id->driver_data & DEV_HAS_MSI) && msi) {
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05005538 np->msi_flags |= NV_MSI_CAPABLE;
5539 }
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -04005540 if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05005541 np->msi_flags |= NV_MSI_X_CAPABLE;
5542 }
5543
Ayaz Abdullab6d07732006-06-10 22:47:42 -04005544 np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -05005545 if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) ||
5546 (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) ||
5547 (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) {
Ayaz Abdullab6d07732006-06-10 22:47:42 -04005548 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04005549 }
Jeff Garzikf3b197a2006-05-26 21:39:03 -04005550
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04005551
Linus Torvalds1da177e2005-04-16 15:20:36 -07005552 err = -ENOMEM;
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005553 np->base = ioremap(addr, np->register_size);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005554 if (!np->base)
5555 goto out_relreg;
5556 dev->base_addr = (unsigned long)np->base;
Manfred Spraulee733622005-07-31 18:32:26 +02005557
Linus Torvalds1da177e2005-04-16 15:20:36 -07005558 dev->irq = pci_dev->irq;
Manfred Spraulee733622005-07-31 18:32:26 +02005559
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005560 np->rx_ring_size = RX_RING_DEFAULT;
5561 np->tx_ring_size = TX_RING_DEFAULT;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005562
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005563 if (!nv_optimized(np)) {
Manfred Spraulee733622005-07-31 18:32:26 +02005564 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005565 sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
Manfred Spraulee733622005-07-31 18:32:26 +02005566 &np->ring_addr);
5567 if (!np->rx_ring.orig)
5568 goto out_unmap;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005569 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
Manfred Spraulee733622005-07-31 18:32:26 +02005570 } else {
5571 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005572 sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
Manfred Spraulee733622005-07-31 18:32:26 +02005573 &np->ring_addr);
5574 if (!np->rx_ring.ex)
5575 goto out_unmap;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005576 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
Manfred Spraulee733622005-07-31 18:32:26 +02005577 }
Yoann Padioleaudd00cc42007-07-19 01:49:03 -07005578 np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5579 np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05005580 if (!np->rx_skb || !np->tx_skb)
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005581 goto out_freering;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005582
5583 dev->open = nv_open;
5584 dev->stop = nv_close;
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005585
5586 if (!nv_optimized(np))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05005587 dev->hard_start_xmit = nv_start_xmit;
5588 else
5589 dev->hard_start_xmit = nv_start_xmit_optimized;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005590 dev->get_stats = nv_get_stats;
5591 dev->change_mtu = nv_change_mtu;
Manfred Spraul72b31782005-07-31 18:33:34 +02005592 dev->set_mac_address = nv_set_mac_address;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005593 dev->set_multicast_list = nv_set_multicast;
Michal Schmidt2918c352005-05-12 19:42:06 -04005594#ifdef CONFIG_NET_POLL_CONTROLLER
5595 dev->poll_controller = nv_poll_controller;
5596#endif
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07005597#ifdef CONFIG_FORCEDETH_NAPI
Stephen Hemmingerbea33482007-10-03 16:41:36 -07005598 netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07005599#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07005600 SET_ETHTOOL_OPS(dev, &ops);
5601 dev->tx_timeout = nv_tx_timeout;
5602 dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
5603
5604 pci_set_drvdata(pci_dev, dev);
5605
5606 /* read the mac address */
5607 base = get_hwbase(dev);
5608 np->orig_mac[0] = readl(base + NvRegMacAddrA);
5609 np->orig_mac[1] = readl(base + NvRegMacAddrB);
5610
Ayaz Abdulla5070d342006-07-31 12:05:01 -04005611 /* check the workaround bit for correct mac address order */
5612 txreg = readl(base + NvRegTransmitPoll);
Ayaz Abdullaa376e792008-04-10 21:30:35 -07005613 if (id->driver_data & DEV_HAS_CORRECT_MACADDR) {
Ayaz Abdulla5070d342006-07-31 12:05:01 -04005614 /* mac address is already in correct order */
5615 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
5616 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
5617 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5618 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5619 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
5620 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
Ayaz Abdullaa376e792008-04-10 21:30:35 -07005621 } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
5622 /* mac address is already in correct order */
5623 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
5624 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
5625 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5626 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5627 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
5628 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
5629 /*
5630 * Set orig mac address back to the reversed version.
5631 * This flag will be cleared during low power transition.
5632 * Therefore, we should always put back the reversed address.
5633 */
5634 np->orig_mac[0] = (dev->dev_addr[5] << 0) + (dev->dev_addr[4] << 8) +
5635 (dev->dev_addr[3] << 16) + (dev->dev_addr[2] << 24);
5636 np->orig_mac[1] = (dev->dev_addr[1] << 0) + (dev->dev_addr[0] << 8);
Ayaz Abdulla5070d342006-07-31 12:05:01 -04005637 } else {
5638 /* need to reverse mac address to correct order */
5639 dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
5640 dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
5641 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
5642 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
5643 dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
5644 dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
Ayaz Abdulla5070d342006-07-31 12:05:01 -04005645 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
Yinghai Luf55c21f2008-09-13 13:10:31 -07005646 printk(KERN_DEBUG "nv_probe: set workaround bit for reversed mac addr\n");
Ayaz Abdulla5070d342006-07-31 12:05:01 -04005647 }
John W. Linvillec704b852005-09-12 10:48:56 -04005648 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005649
John W. Linvillec704b852005-09-12 10:48:56 -04005650 if (!is_valid_ether_addr(dev->perm_addr)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07005651 /*
5652 * Bad mac address. At least one bios sets the mac address
5653 * to 01:23:45:67:89:ab
5654 */
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005655 dev_printk(KERN_ERR, &pci_dev->dev,
5656 "Invalid Mac address detected: %s\n",
5657 print_mac(mac, dev->dev_addr));
5658 dev_printk(KERN_ERR, &pci_dev->dev,
5659 "Please complain to your hardware vendor. Switching to a random MAC.\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07005660 dev->dev_addr[0] = 0x00;
5661 dev->dev_addr[1] = 0x00;
5662 dev->dev_addr[2] = 0x6c;
5663 get_random_bytes(&dev->dev_addr[3], 3);
5664 }
5665
Joe Perches0795af52007-10-03 17:59:30 -07005666 dprintk(KERN_DEBUG "%s: MAC Address %s\n",
5667 pci_name(pci_dev), print_mac(mac, dev->dev_addr));
Linus Torvalds1da177e2005-04-16 15:20:36 -07005668
Ayaz Abdullaf1489652006-07-31 12:04:45 -04005669 /* set mac address */
5670 nv_copy_mac_to_hw(dev);
5671
Tobias Diedrich9a60a822008-06-01 00:54:42 +02005672 /* Workaround current PCI init glitch: wakeup bits aren't
5673 * being set from PCI PM capability.
5674 */
5675 device_init_wakeup(&pci_dev->dev, 1);
5676
Linus Torvalds1da177e2005-04-16 15:20:36 -07005677 /* disable WOL */
5678 writel(0, base + NvRegWakeUpFlags);
5679 np->wolenabled = 0;
5680
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005681 if (id->driver_data & DEV_HAS_POWER_CNTRL) {
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005682
5683 /* take phy and nic out of low power mode */
5684 powerstate = readl(base + NvRegPowerState2);
5685 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
5686 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 ||
5687 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) &&
Auke Kok44c10132007-06-08 15:46:36 -07005688 pci_dev->revision >= 0xA3)
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005689 powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
5690 writel(powerstate, base + NvRegPowerState2);
5691 }
5692
Linus Torvalds1da177e2005-04-16 15:20:36 -07005693 if (np->desc_ver == DESC_VER_1) {
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04005694 np->tx_flags = NV_TX_VALID;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005695 } else {
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04005696 np->tx_flags = NV_TX2_VALID;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005697 }
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05005698 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) {
Ayaz Abdullaa971c322005-11-11 08:30:38 -05005699 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05005700 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5701 np->msi_flags |= 0x0003;
5702 } else {
Ayaz Abdullaa971c322005-11-11 08:30:38 -05005703 np->irqmask = NVREG_IRQMASK_CPU;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05005704 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5705 np->msi_flags |= 0x0001;
5706 }
Ayaz Abdullaa971c322005-11-11 08:30:38 -05005707
Linus Torvalds1da177e2005-04-16 15:20:36 -07005708 if (id->driver_data & DEV_NEED_TIMERIRQ)
5709 np->irqmask |= NVREG_IRQ_TIMER;
5710 if (id->driver_data & DEV_NEED_LINKTIMER) {
5711 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
5712 np->need_linktimer = 1;
5713 np->link_timeout = jiffies + LINK_TIMEOUT;
5714 } else {
5715 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
5716 np->need_linktimer = 0;
5717 }
5718
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05005719 /* Limit the number of tx's outstanding for hw bug */
5720 if (id->driver_data & DEV_NEED_TX_LIMIT) {
5721 np->tx_limit = 1;
5722 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_32 ||
5723 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_33 ||
5724 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_34 ||
5725 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_35 ||
5726 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_36 ||
5727 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_37 ||
5728 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_38 ||
5729 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_39) &&
5730 pci_dev->revision >= 0xA2)
5731 np->tx_limit = 0;
5732 }
5733
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005734 /* clear phy state and temporarily halt phy interrupts */
5735 writel(0, base + NvRegMIIMask);
5736 phystate = readl(base + NvRegAdapterControl);
5737 if (phystate & NVREG_ADAPTCTL_RUNNING) {
5738 phystate_orig = 1;
5739 phystate &= ~NVREG_ADAPTCTL_RUNNING;
5740 writel(phystate, base + NvRegAdapterControl);
5741 }
Ayaz Abdullaeb798422008-02-04 15:14:04 -05005742 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005743
5744 if (id->driver_data & DEV_HAS_MGMT_UNIT) {
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005745 /* management unit running on the mac? */
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05005746 if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) {
5747 np->mac_in_use = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST;
5748 dprintk(KERN_INFO "%s: mgmt unit is running. mac in use %x.\n", pci_name(pci_dev), np->mac_in_use);
Ayaz Abdulla9e555932007-11-21 15:02:58 -08005749 if (nv_mgmt_acquire_sema(dev)) {
5750 /* management unit setup the phy already? */
5751 if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
5752 NVREG_XMITCTL_SYNC_PHY_INIT) {
5753 /* phy is inited by mgmt unit */
5754 phyinitialized = 1;
5755 dprintk(KERN_INFO "%s: Phy already initialized by mgmt unit.\n", pci_name(pci_dev));
5756 } else {
5757 /* we need to init the phy */
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005758 }
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005759 }
5760 }
5761 }
5762
Linus Torvalds1da177e2005-04-16 15:20:36 -07005763 /* find a suitable phy */
Ayaz Abdulla7a33e452005-11-11 08:31:11 -05005764 for (i = 1; i <= 32; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07005765 int id1, id2;
Ayaz Abdulla7a33e452005-11-11 08:31:11 -05005766 int phyaddr = i & 0x1F;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005767
5768 spin_lock_irq(&np->lock);
Ayaz Abdulla7a33e452005-11-11 08:31:11 -05005769 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005770 spin_unlock_irq(&np->lock);
5771 if (id1 < 0 || id1 == 0xffff)
5772 continue;
5773 spin_lock_irq(&np->lock);
Ayaz Abdulla7a33e452005-11-11 08:31:11 -05005774 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005775 spin_unlock_irq(&np->lock);
5776 if (id2 < 0 || id2 == 0xffff)
5777 continue;
5778
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04005779 np->phy_model = id2 & PHYID2_MODEL_MASK;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005780 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
5781 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
5782 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
Ayaz Abdulla7a33e452005-11-11 08:31:11 -05005783 pci_name(pci_dev), id1, id2, phyaddr);
5784 np->phyaddr = phyaddr;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005785 np->phy_oui = id1 | id2;
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04005786
5787 /* Realtek hardcoded phy id1 to all zero's on certain phys */
5788 if (np->phy_oui == PHY_OUI_REALTEK2)
5789 np->phy_oui = PHY_OUI_REALTEK;
5790 /* Setup phy revision for Realtek */
5791 if (np->phy_oui == PHY_OUI_REALTEK && np->phy_model == PHY_MODEL_REALTEK_8211)
5792 np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK;
5793
Linus Torvalds1da177e2005-04-16 15:20:36 -07005794 break;
5795 }
Ayaz Abdulla7a33e452005-11-11 08:31:11 -05005796 if (i == 33) {
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005797 dev_printk(KERN_INFO, &pci_dev->dev,
5798 "open: Could not find a valid PHY.\n");
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005799 goto out_error;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005800 }
Jeff Garzikf3b197a2006-05-26 21:39:03 -04005801
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005802 if (!phyinitialized) {
5803 /* reset it */
5804 phy_init(dev);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05005805 } else {
5806 /* see if it is a gigabit phy */
5807 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5808 if (mii_status & PHY_GIGABIT) {
5809 np->gigabit = PHY_GIGABIT;
5810 }
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005811 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005812
5813 /* set default link speed settings */
5814 np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
5815 np->duplex = 0;
5816 np->autoneg = 1;
5817
5818 err = register_netdev(dev);
5819 if (err) {
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005820 dev_printk(KERN_INFO, &pci_dev->dev,
5821 "unable to register netdev: %d\n", err);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005822 goto out_error;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005823 }
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005824
5825 dev_printk(KERN_INFO, &pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, "
5826 "addr %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
5827 dev->name,
5828 np->phy_oui,
5829 np->phyaddr,
5830 dev->dev_addr[0],
5831 dev->dev_addr[1],
5832 dev->dev_addr[2],
5833 dev->dev_addr[3],
5834 dev->dev_addr[4],
5835 dev->dev_addr[5]);
5836
5837 dev_printk(KERN_INFO, &pci_dev->dev, "%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
5838 dev->features & NETIF_F_HIGHDMA ? "highdma " : "",
Ayaz Abdullaedcfe5f2008-08-20 16:34:37 -07005839 dev->features & (NETIF_F_IP_CSUM | NETIF_F_SG) ?
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005840 "csum " : "",
5841 dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ?
5842 "vlan " : "",
5843 id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "",
5844 id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "",
5845 id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "",
5846 np->gigabit == PHY_GIGABIT ? "gbit " : "",
5847 np->need_linktimer ? "lnktim " : "",
5848 np->msi_flags & NV_MSI_CAPABLE ? "msi " : "",
5849 np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "",
5850 np->desc_ver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005851
5852 return 0;
5853
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005854out_error:
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005855 if (phystate_orig)
5856 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005857 pci_set_drvdata(pci_dev, NULL);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005858out_freering:
5859 free_rings(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005860out_unmap:
5861 iounmap(get_hwbase(dev));
5862out_relreg:
5863 pci_release_regions(pci_dev);
5864out_disable:
5865 pci_disable_device(pci_dev);
5866out_free:
5867 free_netdev(dev);
5868out:
5869 return err;
5870}
5871
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04005872static void nv_restore_phy(struct net_device *dev)
5873{
5874 struct fe_priv *np = netdev_priv(dev);
5875 u16 phy_reserved, mii_control;
5876
5877 if (np->phy_oui == PHY_OUI_REALTEK &&
5878 np->phy_model == PHY_MODEL_REALTEK_8201 &&
5879 phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
5880 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3);
5881 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
5882 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
5883 phy_reserved |= PHY_REALTEK_INIT8;
5884 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved);
5885 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1);
5886
5887 /* restart auto negotiation */
5888 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
5889 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
5890 mii_rw(dev, np->phyaddr, MII_BMCR, mii_control);
5891 }
5892}
5893
Yinghai Luf55c21f2008-09-13 13:10:31 -07005894static void nv_restore_mac_addr(struct pci_dev *pci_dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005895{
5896 struct net_device *dev = pci_get_drvdata(pci_dev);
Ayaz Abdullaf1489652006-07-31 12:04:45 -04005897 struct fe_priv *np = netdev_priv(dev);
5898 u8 __iomem *base = get_hwbase(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005899
Ayaz Abdullaf1489652006-07-31 12:04:45 -04005900 /* special op: write back the misordered MAC address - otherwise
5901 * the next nv_probe would see a wrong address.
5902 */
5903 writel(np->orig_mac[0], base + NvRegMacAddrA);
5904 writel(np->orig_mac[1], base + NvRegMacAddrB);
Björn Steinbrink2e3884b2008-01-07 23:22:53 -08005905 writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV,
5906 base + NvRegTransmitPoll);
Yinghai Luf55c21f2008-09-13 13:10:31 -07005907}
5908
5909static void __devexit nv_remove(struct pci_dev *pci_dev)
5910{
5911 struct net_device *dev = pci_get_drvdata(pci_dev);
5912
5913 unregister_netdev(dev);
5914
5915 nv_restore_mac_addr(pci_dev);
Ayaz Abdullaf1489652006-07-31 12:04:45 -04005916
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04005917 /* restore any phy related changes */
5918 nv_restore_phy(dev);
5919
Linus Torvalds1da177e2005-04-16 15:20:36 -07005920 /* free all structures */
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005921 free_rings(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005922 iounmap(get_hwbase(dev));
5923 pci_release_regions(pci_dev);
5924 pci_disable_device(pci_dev);
5925 free_netdev(dev);
5926 pci_set_drvdata(pci_dev, NULL);
5927}
5928
Francois Romieua1893172006-10-10 14:33:27 -07005929#ifdef CONFIG_PM
5930static int nv_suspend(struct pci_dev *pdev, pm_message_t state)
5931{
5932 struct net_device *dev = pci_get_drvdata(pdev);
5933 struct fe_priv *np = netdev_priv(dev);
Tobias Diedrich1a1ca862008-05-18 15:03:44 +02005934 u8 __iomem *base = get_hwbase(dev);
5935 int i;
Francois Romieua1893172006-10-10 14:33:27 -07005936
Tobias Diedrich25d90812008-05-18 15:04:29 +02005937 if (netif_running(dev)) {
5938 // Gross.
5939 nv_close(dev);
5940 }
Francois Romieua1893172006-10-10 14:33:27 -07005941 netif_device_detach(dev);
5942
Tobias Diedrich1a1ca862008-05-18 15:03:44 +02005943 /* save non-pci configuration space */
5944 for (i = 0;i <= np->register_size/sizeof(u32); i++)
5945 np->saved_config_space[i] = readl(base + i*sizeof(u32));
5946
Francois Romieua1893172006-10-10 14:33:27 -07005947 pci_save_state(pdev);
5948 pci_enable_wake(pdev, pci_choose_state(pdev, state), np->wolenabled);
Tobias Diedrich25d90812008-05-18 15:04:29 +02005949 pci_disable_device(pdev);
Francois Romieua1893172006-10-10 14:33:27 -07005950 pci_set_power_state(pdev, pci_choose_state(pdev, state));
Francois Romieua1893172006-10-10 14:33:27 -07005951 return 0;
5952}
5953
5954static int nv_resume(struct pci_dev *pdev)
5955{
5956 struct net_device *dev = pci_get_drvdata(pdev);
Tobias Diedrich1a1ca862008-05-18 15:03:44 +02005957 struct fe_priv *np = netdev_priv(dev);
Ayaz Abdullaa376e792008-04-10 21:30:35 -07005958 u8 __iomem *base = get_hwbase(dev);
Tobias Diedrich1a1ca862008-05-18 15:03:44 +02005959 int i, rc = 0;
Francois Romieua1893172006-10-10 14:33:27 -07005960
Francois Romieua1893172006-10-10 14:33:27 -07005961 pci_set_power_state(pdev, PCI_D0);
5962 pci_restore_state(pdev);
Tobias Diedrich25d90812008-05-18 15:04:29 +02005963 /* ack any pending wake events, disable PME */
Francois Romieua1893172006-10-10 14:33:27 -07005964 pci_enable_wake(pdev, PCI_D0, 0);
5965
Tobias Diedrich1a1ca862008-05-18 15:03:44 +02005966 /* restore non-pci configuration space */
5967 for (i = 0;i <= np->register_size/sizeof(u32); i++)
5968 writel(np->saved_config_space[i], base+i*sizeof(u32));
Ayaz Abdullaa376e792008-04-10 21:30:35 -07005969
Tobias Diedrich25d90812008-05-18 15:04:29 +02005970 netif_device_attach(dev);
5971 if (netif_running(dev)) {
5972 rc = nv_open(dev);
5973 nv_set_multicast(dev);
5974 }
Francois Romieua1893172006-10-10 14:33:27 -07005975 return rc;
5976}
Tobias Diedrichf735a2a2008-05-18 15:02:37 +02005977
5978static void nv_shutdown(struct pci_dev *pdev)
5979{
5980 struct net_device *dev = pci_get_drvdata(pdev);
5981 struct fe_priv *np = netdev_priv(dev);
5982
5983 if (netif_running(dev))
5984 nv_close(dev);
5985
Yinghai Luf55c21f2008-09-13 13:10:31 -07005986 nv_restore_mac_addr(pdev);
5987
Tobias Diedrichf735a2a2008-05-18 15:02:37 +02005988 pci_disable_device(pdev);
Rafael J. Wysocki3cb55992008-09-05 14:00:19 -07005989 if (system_state == SYSTEM_POWER_OFF) {
5990 if (pci_enable_wake(pdev, PCI_D3cold, np->wolenabled))
5991 pci_enable_wake(pdev, PCI_D3hot, np->wolenabled);
5992 pci_set_power_state(pdev, PCI_D3hot);
5993 }
Tobias Diedrichf735a2a2008-05-18 15:02:37 +02005994}
Francois Romieua1893172006-10-10 14:33:27 -07005995#else
5996#define nv_suspend NULL
Tobias Diedrichf735a2a2008-05-18 15:02:37 +02005997#define nv_shutdown NULL
Francois Romieua1893172006-10-10 14:33:27 -07005998#define nv_resume NULL
5999#endif /* CONFIG_PM */
6000
Linus Torvalds1da177e2005-04-16 15:20:36 -07006001static struct pci_device_id pci_tbl[] = {
6002 { /* nForce Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02006003 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
Manfred Spraulc2dba062005-07-31 18:29:47 +02006004 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006005 },
6006 { /* nForce2 Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02006007 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
Manfred Spraulc2dba062005-07-31 18:29:47 +02006008 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006009 },
6010 { /* nForce3 Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02006011 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
Manfred Spraulc2dba062005-07-31 18:29:47 +02006012 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006013 },
6014 { /* nForce3 Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02006015 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04006016 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006017 },
6018 { /* nForce3 Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02006019 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04006020 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006021 },
6022 { /* nForce3 Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02006023 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04006024 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006025 },
6026 { /* nForce3 Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02006027 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04006028 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006029 },
6030 { /* CK804 Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02006031 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05006032 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006033 },
6034 { /* CK804 Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02006035 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05006036 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006037 },
6038 { /* MCP04 Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02006039 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05006040 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006041 },
6042 { /* MCP04 Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02006043 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05006044 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
Manfred Sprauldc8216c2005-07-31 18:26:05 +02006045 },
6046 { /* MCP51 Ethernet Controller */
6047 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
Ayaz Abdulla57fff692007-01-23 12:27:00 -05006048 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006049 },
Manfred Spraul9992d4a2005-06-05 17:36:11 +02006050 { /* MCP51 Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02006051 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
Ayaz Abdulla57fff692007-01-23 12:27:00 -05006052 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1,
Manfred Spraul9992d4a2005-06-05 17:36:11 +02006053 },
Manfred Spraulf49d16e2005-06-26 11:36:52 +02006054 { /* MCP55 Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02006055 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05006056 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT,
Manfred Spraulf49d16e2005-06-26 11:36:52 +02006057 },
6058 { /* MCP55 Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02006059 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05006060 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT,
Manfred Spraulf49d16e2005-06-26 11:36:52 +02006061 },
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04006062 { /* MCP61 Ethernet Controller */
6063 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_16),
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -05006064 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04006065 },
6066 { /* MCP61 Ethernet Controller */
6067 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_17),
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -05006068 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04006069 },
6070 { /* MCP61 Ethernet Controller */
6071 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_18),
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -05006072 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04006073 },
6074 { /* MCP61 Ethernet Controller */
6075 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_19),
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -05006076 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04006077 },
6078 { /* MCP65 Ethernet Controller */
6079 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20),
Ayaz Abdullaa4336862008-04-18 13:50:43 -07006080 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04006081 },
6082 { /* MCP65 Ethernet Controller */
6083 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21),
Ayaz Abdullaa4336862008-04-18 13:50:43 -07006084 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04006085 },
6086 { /* MCP65 Ethernet Controller */
6087 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22),
Ayaz Abdullaa4336862008-04-18 13:50:43 -07006088 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04006089 },
6090 { /* MCP65 Ethernet Controller */
6091 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23),
Ayaz Abdullaa4336862008-04-18 13:50:43 -07006092 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04006093 },
Ayaz Abdullaf4344842006-11-06 00:43:40 -08006094 { /* MCP67 Ethernet Controller */
6095 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_24),
Ayaz Abdullaa4336862008-04-18 13:50:43 -07006096 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE,
Ayaz Abdullaf4344842006-11-06 00:43:40 -08006097 },
6098 { /* MCP67 Ethernet Controller */
6099 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_25),
Ayaz Abdullaa4336862008-04-18 13:50:43 -07006100 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE,
Ayaz Abdullaf4344842006-11-06 00:43:40 -08006101 },
6102 { /* MCP67 Ethernet Controller */
6103 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_26),
Ayaz Abdullaa4336862008-04-18 13:50:43 -07006104 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE,
Ayaz Abdullaf4344842006-11-06 00:43:40 -08006105 },
6106 { /* MCP67 Ethernet Controller */
6107 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_27),
Ayaz Abdullaa4336862008-04-18 13:50:43 -07006108 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE,
Ayaz Abdullaf4344842006-11-06 00:43:40 -08006109 },
Ayaz Abdulla13986612007-07-22 20:43:26 -04006110 { /* MCP73 Ethernet Controller */
6111 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_28),
Ayaz Abdullaa4336862008-04-18 13:50:43 -07006112 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE,
Ayaz Abdulla13986612007-07-22 20:43:26 -04006113 },
6114 { /* MCP73 Ethernet Controller */
6115 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_29),
Ayaz Abdullaa4336862008-04-18 13:50:43 -07006116 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE,
Ayaz Abdulla13986612007-07-22 20:43:26 -04006117 },
6118 { /* MCP73 Ethernet Controller */
6119 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_30),
Ayaz Abdullaa4336862008-04-18 13:50:43 -07006120 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE,
Ayaz Abdulla13986612007-07-22 20:43:26 -04006121 },
6122 { /* MCP73 Ethernet Controller */
6123 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_31),
Ayaz Abdullaa4336862008-04-18 13:50:43 -07006124 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE,
Ayaz Abdulla13986612007-07-22 20:43:26 -04006125 },
Ayaz Abdulla96fd4cd2007-10-25 03:36:42 -04006126 { /* MCP77 Ethernet Controller */
6127 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_32),
Ayaz Abdulla9c662432008-08-06 12:11:42 -04006128 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
Ayaz Abdulla96fd4cd2007-10-25 03:36:42 -04006129 },
6130 { /* MCP77 Ethernet Controller */
6131 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_33),
Ayaz Abdulla9c662432008-08-06 12:11:42 -04006132 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
Ayaz Abdulla96fd4cd2007-10-25 03:36:42 -04006133 },
6134 { /* MCP77 Ethernet Controller */
6135 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_34),
Ayaz Abdulla9c662432008-08-06 12:11:42 -04006136 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
Ayaz Abdulla96fd4cd2007-10-25 03:36:42 -04006137 },
6138 { /* MCP77 Ethernet Controller */
6139 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_35),
Ayaz Abdulla9c662432008-08-06 12:11:42 -04006140 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
Ayaz Abdulla96fd4cd2007-10-25 03:36:42 -04006141 },
Ayaz Abdulla490dde82007-11-23 20:54:01 -05006142 { /* MCP79 Ethernet Controller */
6143 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_36),
Ayaz Abdulla06941932008-08-06 12:12:18 -04006144 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
Ayaz Abdulla490dde82007-11-23 20:54:01 -05006145 },
6146 { /* MCP79 Ethernet Controller */
6147 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_37),
Ayaz Abdulla06941932008-08-06 12:12:18 -04006148 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
Ayaz Abdulla490dde82007-11-23 20:54:01 -05006149 },
6150 { /* MCP79 Ethernet Controller */
6151 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_38),
Ayaz Abdulla06941932008-08-06 12:12:18 -04006152 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
Ayaz Abdulla490dde82007-11-23 20:54:01 -05006153 },
6154 { /* MCP79 Ethernet Controller */
6155 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_39),
Ayaz Abdulla06941932008-08-06 12:12:18 -04006156 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
Ayaz Abdulla490dde82007-11-23 20:54:01 -05006157 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07006158 {0,},
6159};
6160
6161static struct pci_driver driver = {
Jeff Garzik3f88ce42007-10-16 04:09:09 -04006162 .name = DRV_NAME,
6163 .id_table = pci_tbl,
6164 .probe = nv_probe,
6165 .remove = __devexit_p(nv_remove),
6166 .suspend = nv_suspend,
6167 .resume = nv_resume,
Tobias Diedrichf735a2a2008-05-18 15:02:37 +02006168 .shutdown = nv_shutdown,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006169};
6170
Linus Torvalds1da177e2005-04-16 15:20:36 -07006171static int __init init_nic(void)
6172{
Jeff Garzik29917622006-08-19 17:48:59 -04006173 return pci_register_driver(&driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006174}
6175
6176static void __exit exit_nic(void)
6177{
6178 pci_unregister_driver(&driver);
6179}
6180
6181module_param(max_interrupt_work, int, 0);
6182MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
Ayaz Abdullaa971c322005-11-11 08:30:38 -05006183module_param(optimization_mode, int, 0);
6184MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer.");
6185module_param(poll_interval, int, 0);
6186MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -04006187module_param(msi, int, 0);
6188MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
6189module_param(msix, int, 0);
6190MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
6191module_param(dma_64bit, int, 0);
6192MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04006193module_param(phy_cross, int, 0);
6194MODULE_PARM_DESC(phy_cross, "Phy crossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0.");
Linus Torvalds1da177e2005-04-16 15:20:36 -07006195
6196MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
6197MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
6198MODULE_LICENSE("GPL");
6199
6200MODULE_DEVICE_TABLE(pci, pci_tbl);
6201
6202module_init(init_nic);
6203module_exit(exit_nic);