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Rafał Miłecki8369ae32011-05-09 18:56:46 +02001/*
2 * Broadcom specific AMBA
3 * ChipCommon core driver
4 *
5 * Copyright 2005, Broadcom Corporation
Michael Büscheb032b92011-07-04 20:50:05 +02006 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
Hauke Mehrtens56fd5f02012-12-05 18:45:59 +01007 * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
Rafał Miłecki8369ae32011-05-09 18:56:46 +02008 *
9 * Licensed under the GNU/GPL. See COPYING for details.
10 */
11
12#include "bcma_private.h"
Paul Gortmaker44a8e372011-07-27 21:21:04 -040013#include <linux/export.h>
Rafał Miłecki8369ae32011-05-09 18:56:46 +020014#include <linux/bcma/bcma.h>
15
16static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset,
17 u32 mask, u32 value)
18{
19 value &= mask;
20 value |= bcma_cc_read32(cc, offset) & ~mask;
21 bcma_cc_write32(cc, offset, value);
22
23 return value;
24}
25
Hauke Mehrtens56fd5f02012-12-05 18:45:59 +010026static u32 bcma_chipco_alp_clock(struct bcma_drv_cc *cc)
27{
28 if (cc->capabilities & BCMA_CC_CAP_PMU)
29 return bcma_pmu_alp_clock(cc);
30
31 return 20000000;
32}
33
Hauke Mehrtensf6354c82012-12-05 18:46:00 +010034static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc)
35{
36 struct bcma_bus *bus = cc->core->bus;
37 u32 nb;
38
39 if (cc->capabilities & BCMA_CC_CAP_PMU) {
40 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
41 nb = 32;
42 else if (cc->core->id.rev < 26)
43 nb = 16;
44 else
45 nb = (cc->core->id.rev >= 37) ? 32 : 24;
46 } else {
47 nb = 28;
48 }
49 if (nb == 32)
50 return 0xffffffff;
51 else
52 return (1 << nb) - 1;
53}
54
55
Hauke Mehrtens49655bb2012-09-29 20:29:49 +020056void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
57{
58 if (cc->early_setup_done)
59 return;
60
61 if (cc->core->id.rev >= 11)
62 cc->status = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
63 cc->capabilities = bcma_cc_read32(cc, BCMA_CC_CAP);
64 if (cc->core->id.rev >= 35)
65 cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT);
66
67 if (cc->capabilities & BCMA_CC_CAP_PMU)
68 bcma_pmu_early_init(cc);
69
70 cc->early_setup_done = true;
71}
72
Rafał Miłecki8369ae32011-05-09 18:56:46 +020073void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
74{
Rafał Miłecki18dfa492011-07-14 21:49:19 +020075 u32 leddc_on = 10;
76 u32 leddc_off = 90;
77
Hauke Mehrtens517f43e2011-07-23 01:20:07 +020078 if (cc->setup_done)
79 return;
80
Hauke Mehrtens49655bb2012-09-29 20:29:49 +020081 bcma_core_chipcommon_early_init(cc);
Rafał Miłecki8369ae32011-05-09 18:56:46 +020082
Rafał Miłecki1073e4e2011-05-11 02:08:09 +020083 if (cc->core->id.rev >= 20) {
84 bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0);
85 bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0);
86 }
Rafał Miłecki8369ae32011-05-09 18:56:46 +020087
88 if (cc->capabilities & BCMA_CC_CAP_PMU)
89 bcma_pmu_init(cc);
90 if (cc->capabilities & BCMA_CC_CAP_PCTL)
Rafał Miłecki3d9d8af2012-07-05 22:07:32 +020091 bcma_err(cc->core->bus, "Power control not implemented!\n");
Rafał Miłecki18dfa492011-07-14 21:49:19 +020092
93 if (cc->core->id.rev >= 16) {
94 if (cc->core->bus->sprom.leddc_on_time &&
95 cc->core->bus->sprom.leddc_off_time) {
96 leddc_on = cc->core->bus->sprom.leddc_on_time;
97 leddc_off = cc->core->bus->sprom.leddc_off_time;
98 }
99 bcma_cc_write32(cc, BCMA_CC_GPIOTIMER,
100 ((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) |
101 (leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT)));
102 }
Hauke Mehrtens517f43e2011-07-23 01:20:07 +0200103
104 cc->setup_done = true;
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200105}
106
107/* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
108void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
109{
Hauke Mehrtensf6354c82012-12-05 18:46:00 +0100110 u32 maxt;
111 enum bcma_clkmode clkmode;
112
113 maxt = bcma_chipco_watchdog_get_max_timer(cc);
114 if (cc->capabilities & BCMA_CC_CAP_PMU) {
115 if (ticks == 1)
116 ticks = 2;
117 else if (ticks > maxt)
118 ticks = maxt;
119 bcma_cc_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks);
120 } else {
121 clkmode = ticks ? BCMA_CLKMODE_FAST : BCMA_CLKMODE_DYNAMIC;
122 bcma_core_set_clockmode(cc->core, clkmode);
123 if (ticks > maxt)
124 ticks = maxt;
125 /* instant NMI */
126 bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
127 }
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200128}
129
130void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value)
131{
132 bcma_cc_write32_masked(cc, BCMA_CC_IRQMASK, mask, value);
133}
134
135u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask)
136{
137 return bcma_cc_read32(cc, BCMA_CC_IRQSTAT) & mask;
138}
139
140u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask)
141{
142 return bcma_cc_read32(cc, BCMA_CC_GPIOIN) & mask;
143}
144
145u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value)
146{
147 return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
148}
149
150u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value)
151{
152 return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
153}
154
155u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value)
156{
157 return bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);
158}
159EXPORT_SYMBOL_GPL(bcma_chipco_gpio_control);
160
161u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value)
162{
163 return bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
164}
165
166u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value)
167{
168 return bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
169}
Hauke Mehrtense3afe0e2011-07-23 01:20:10 +0200170
171#ifdef CONFIG_BCMA_DRIVER_MIPS
172void bcma_chipco_serial_init(struct bcma_drv_cc *cc)
173{
174 unsigned int irq;
175 u32 baud_base;
176 u32 i;
177 unsigned int ccrev = cc->core->id.rev;
178 struct bcma_serial_port *ports = cc->serial_ports;
179
180 if (ccrev >= 11 && ccrev != 15) {
Hauke Mehrtens56fd5f02012-12-05 18:45:59 +0100181 baud_base = bcma_chipco_alp_clock(cc);
Hauke Mehrtense3afe0e2011-07-23 01:20:10 +0200182 if (ccrev >= 21) {
183 /* Turn off UART clock before switching clocksource. */
184 bcma_cc_write32(cc, BCMA_CC_CORECTL,
185 bcma_cc_read32(cc, BCMA_CC_CORECTL)
186 & ~BCMA_CC_CORECTL_UARTCLKEN);
187 }
188 /* Set the override bit so we don't divide it */
189 bcma_cc_write32(cc, BCMA_CC_CORECTL,
190 bcma_cc_read32(cc, BCMA_CC_CORECTL)
191 | BCMA_CC_CORECTL_UARTCLK0);
192 if (ccrev >= 21) {
193 /* Re-enable the UART clock. */
194 bcma_cc_write32(cc, BCMA_CC_CORECTL,
195 bcma_cc_read32(cc, BCMA_CC_CORECTL)
196 | BCMA_CC_CORECTL_UARTCLKEN);
197 }
198 } else {
Rafał Miłecki9a89c3a2012-07-09 19:34:59 +0200199 bcma_err(cc->core->bus, "serial not supported on this device ccrev: 0x%x\n", ccrev);
Hauke Mehrtense3afe0e2011-07-23 01:20:10 +0200200 return;
201 }
202
203 irq = bcma_core_mips_irq(cc->core);
204
205 /* Determine the registers of the UARTs */
206 cc->nr_serial_ports = (cc->capabilities & BCMA_CC_CAP_NRUART);
207 for (i = 0; i < cc->nr_serial_ports; i++) {
208 ports[i].regs = cc->core->io_addr + BCMA_CC_UART0_DATA +
209 (i * 256);
210 ports[i].irq = irq;
211 ports[i].baud_base = baud_base;
212 ports[i].reg_shift = 0;
213 }
214}
215#endif /* CONFIG_BCMA_DRIVER_MIPS */