blob: 9d2bc270b35b7d535fe8459dbd1292248447d885 [file] [log] [blame]
Peter De Schrijveradd29e62011-10-12 14:53:05 +03001/dts-v1/;
2
Peter De Schrijveradd29e62011-10-12 14:53:05 +03003/include/ "tegra20.dtsi"
4
5/ {
6 model = "NVIDIA Tegra2 Ventana evaluation board";
7 compatible = "nvidia,ventana", "nvidia,tegra20";
8
Peter De Schrijveradd29e62011-10-12 14:53:05 +03009 memory {
Stephen Warren95decf82012-05-11 16:11:38 -060010 reg = <0x00000000 0x40000000>;
Peter De Schrijveradd29e62011-10-12 14:53:05 +030011 };
12
Stephen Warrenecc295b2012-03-15 16:27:36 -060013 pinmux@70000000 {
14 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>;
16
17 state_default: pinmux {
18 ata {
19 nvidia,pins = "ata";
20 nvidia,function = "ide";
21 };
22 atb {
23 nvidia,pins = "atb", "gma", "gme";
24 nvidia,function = "sdio4";
25 };
26 atc {
27 nvidia,pins = "atc";
28 nvidia,function = "nand";
29 };
30 atd {
31 nvidia,pins = "atd", "ate", "gmb", "spia",
32 "spib", "spic";
33 nvidia,function = "gmi";
34 };
35 cdev1 {
36 nvidia,pins = "cdev1";
37 nvidia,function = "plla_out";
38 };
39 cdev2 {
40 nvidia,pins = "cdev2";
41 nvidia,function = "pllp_out4";
42 };
43 crtp {
44 nvidia,pins = "crtp", "lm1";
45 nvidia,function = "crt";
46 };
47 csus {
48 nvidia,pins = "csus";
49 nvidia,function = "vi_sensor_clk";
50 };
51 dap1 {
52 nvidia,pins = "dap1";
53 nvidia,function = "dap1";
54 };
55 dap2 {
56 nvidia,pins = "dap2";
57 nvidia,function = "dap2";
58 };
59 dap3 {
60 nvidia,pins = "dap3";
61 nvidia,function = "dap3";
62 };
63 dap4 {
64 nvidia,pins = "dap4";
65 nvidia,function = "dap4";
66 };
67 ddc {
68 nvidia,pins = "ddc", "owc", "spdi", "spdo",
69 "uac";
70 nvidia,function = "rsvd2";
71 };
72 dta {
73 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
74 nvidia,function = "vi";
75 };
76 dtf {
77 nvidia,pins = "dtf";
78 nvidia,function = "i2c3";
79 };
80 gmc {
81 nvidia,pins = "gmc";
82 nvidia,function = "uartd";
83 };
84 gmd {
85 nvidia,pins = "gmd";
86 nvidia,function = "sflash";
87 };
88 gpu {
89 nvidia,pins = "gpu";
90 nvidia,function = "pwm";
91 };
92 gpu7 {
93 nvidia,pins = "gpu7";
94 nvidia,function = "rtck";
95 };
96 gpv {
97 nvidia,pins = "gpv", "slxa", "slxk";
98 nvidia,function = "pcie";
99 };
100 hdint {
101 nvidia,pins = "hdint", "pta";
102 nvidia,function = "hdmi";
103 };
104 i2cp {
105 nvidia,pins = "i2cp";
106 nvidia,function = "i2cp";
107 };
108 irrx {
109 nvidia,pins = "irrx", "irtx";
110 nvidia,function = "uartb";
111 };
112 kbca {
113 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
114 "kbce", "kbcf";
115 nvidia,function = "kbc";
116 };
117 lcsn {
118 nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
119 "lsdi", "lvp0";
120 nvidia,function = "rsvd4";
121 };
122 ld0 {
123 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
124 "ld5", "ld6", "ld7", "ld8", "ld9",
125 "ld10", "ld11", "ld12", "ld13", "ld14",
126 "ld15", "ld16", "ld17", "ldi", "lhp0",
127 "lhp1", "lhp2", "lhs", "lpp", "lpw0",
128 "lpw2", "lsc0", "lsc1", "lsck", "lsda",
129 "lspi", "lvp1", "lvs";
130 nvidia,function = "displaya";
131 };
132 pmc {
133 nvidia,pins = "pmc";
134 nvidia,function = "pwr_on";
135 };
136 rm {
137 nvidia,pins = "rm";
138 nvidia,function = "i2c1";
139 };
140 sdb {
141 nvidia,pins = "sdb", "sdc", "sdd", "slxc";
142 nvidia,function = "sdio3";
143 };
144 sdio1 {
145 nvidia,pins = "sdio1";
146 nvidia,function = "sdio1";
147 };
148 slxd {
149 nvidia,pins = "slxd";
150 nvidia,function = "spdif";
151 };
152 spid {
153 nvidia,pins = "spid", "spie", "spif";
154 nvidia,function = "spi1";
155 };
156 spig {
157 nvidia,pins = "spig", "spih";
158 nvidia,function = "spi2_alt";
159 };
160 uaa {
161 nvidia,pins = "uaa", "uab", "uda";
162 nvidia,function = "ulpi";
163 };
164 uad {
165 nvidia,pins = "uad";
166 nvidia,function = "irda";
167 };
168 uca {
169 nvidia,pins = "uca", "ucb";
170 nvidia,function = "uartc";
171 };
172 conf_ata {
173 nvidia,pins = "ata", "atb", "atc", "atd",
174 "cdev1", "cdev2", "dap1", "dap2",
175 "dap4", "ddc", "dtf", "gma", "gmc",
176 "gme", "gpu", "gpu7", "i2cp", "irrx",
177 "irtx", "pta", "rm", "sdc", "sdd",
178 "slxc", "slxd", "slxk", "spdi", "spdo",
179 "uac", "uad", "uca", "ucb", "uda";
180 nvidia,pull = <0>;
181 nvidia,tristate = <0>;
182 };
183 conf_ate {
184 nvidia,pins = "ate", "csus", "dap3", "gmd",
185 "gpv", "owc", "spia", "spib", "spic",
186 "spid", "spie", "spig";
187 nvidia,pull = <0>;
188 nvidia,tristate = <1>;
189 };
190 conf_ck32 {
191 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
192 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
193 nvidia,pull = <0>;
194 };
195 conf_crtp {
196 nvidia,pins = "crtp", "gmb", "slxa", "spih";
197 nvidia,pull = <2>;
198 nvidia,tristate = <1>;
199 };
200 conf_dta {
201 nvidia,pins = "dta", "dtb", "dtc", "dtd";
202 nvidia,pull = <1>;
203 nvidia,tristate = <0>;
204 };
205 conf_dte {
206 nvidia,pins = "dte", "spif";
207 nvidia,pull = <1>;
208 nvidia,tristate = <1>;
209 };
210 conf_hdint {
211 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
212 "lpw1", "lsck", "lsda", "lsdi", "lvp0";
213 nvidia,tristate = <1>;
214 };
215 conf_kbca {
216 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
217 "kbce", "kbcf", "sdio1", "uaa", "uab";
218 nvidia,pull = <2>;
219 nvidia,tristate = <0>;
220 };
221 conf_lc {
222 nvidia,pins = "lc", "ls";
223 nvidia,pull = <2>;
224 };
225 conf_ld0 {
226 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
227 "ld5", "ld6", "ld7", "ld8", "ld9",
228 "ld10", "ld11", "ld12", "ld13", "ld14",
229 "ld15", "ld16", "ld17", "ldi", "lhp0",
230 "lhp1", "lhp2", "lhs", "lm0", "lpp",
231 "lpw0", "lpw2", "lsc0", "lsc1", "lspi",
232 "lvp1", "lvs", "pmc", "sdb";
233 nvidia,tristate = <0>;
234 };
235 conf_ld17_0 {
236 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
237 "ld23_22";
238 nvidia,pull = <1>;
239 };
240 };
241 };
242
Stephen Warren88950f3b2011-11-21 14:44:09 -0700243 i2c@7000c000 {
244 clock-frequency = <400000>;
Stephen Warren797acf72012-01-11 16:09:57 -0700245
246 wm8903: wm8903@1a {
247 compatible = "wlf,wm8903";
248 reg = <0x1a>;
249 interrupt-parent = <&gpio>;
Stephen Warren95decf82012-05-11 16:11:38 -0600250 interrupts = <187 0x04>;
Stephen Warren797acf72012-01-11 16:09:57 -0700251
252 gpio-controller;
253 #gpio-cells = <2>;
254
255 micdet-cfg = <0>;
256 micdet-delay = <100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600257 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
Stephen Warren797acf72012-01-11 16:09:57 -0700258 };
Laxman Dewanganb46b0b52012-04-23 17:41:36 +0530259
260 /* ALS and proximity sensor */
261 isl29018@44 {
262 compatible = "isil,isl29018";
263 reg = <0x44>;
264 interrupt-parent = <&gpio>;
265 interrupts = <202 0x04>; /*gpio PZ2 */
266 };
Stephen Warren88950f3b2011-11-21 14:44:09 -0700267 };
268
269 i2c@7000c400 {
270 clock-frequency = <400000>;
271 };
272
273 i2c@7000c500 {
274 clock-frequency = <400000>;
275 };
276
277 i2c@7000d000 {
278 clock-frequency = <400000>;
279 };
280
Stephen Warren797acf72012-01-11 16:09:57 -0700281 i2s@70002a00 {
282 status = "disable";
283 };
284
285 sound {
286 compatible = "nvidia,tegra-audio-wm8903-ventana",
287 "nvidia,tegra-audio-wm8903";
288 nvidia,model = "NVIDIA Tegra Ventana";
289
290 nvidia,audio-routing =
291 "Headphone Jack", "HPOUTR",
292 "Headphone Jack", "HPOUTL",
293 "Int Spk", "ROP",
294 "Int Spk", "RON",
295 "Int Spk", "LOP",
296 "Int Spk", "LON",
297 "Mic Jack", "MICBIAS",
298 "IN1L", "Mic Jack";
299
300 nvidia,i2s-controller = <&tegra_i2s1>;
301 nvidia,audio-codec = <&wm8903>;
302
303 nvidia,spkr-en-gpios = <&wm8903 2 0>;
304 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
305 nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */
306 nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
307 };
308
Stephen Warren31c1ec92011-11-21 14:44:10 -0700309 serial@70006000 {
310 status = "disable";
311 };
312
313 serial@70006040 {
314 status = "disable";
315 };
316
317 serial@70006200 {
318 status = "disable";
319 };
320
Peter De Schrijveradd29e62011-10-12 14:53:05 +0300321 serial@70006300 {
Stephen Warren95decf82012-05-11 16:11:38 -0600322 clock-frequency = <216000000>;
Peter De Schrijveradd29e62011-10-12 14:53:05 +0300323 };
324
Stephen Warren31c1ec92011-11-21 14:44:10 -0700325 serial@70006400 {
326 status = "disable";
327 };
328
Stephen Warren1292c122011-11-21 14:44:11 -0700329 sdhci@c8000000 {
330 status = "disable";
331 };
332
333 sdhci@c8000200 {
334 status = "disable";
335 };
336
Peter De Schrijveradd29e62011-10-12 14:53:05 +0300337 sdhci@c8000400 {
338 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
339 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
Stephen Warrenc406eeb2011-10-19 06:53:57 +0000340 power-gpios = <&gpio 70 0>; /* gpio PI6 */
Peter De Schrijveradd29e62011-10-12 14:53:05 +0300341 };
342
343 sdhci@c8000600 {
Peter De Schrijveradd29e62011-10-12 14:53:05 +0300344 support-8bit;
345 };
Stephen Warrenaa607eb2012-04-12 15:46:49 -0600346
347 usb@c5004000 {
348 nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
349 };
Peter De Schrijveradd29e62011-10-12 14:53:05 +0300350};