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gerrit-public.fairphone.software / kernel / msm-4.19 / f9fa1bb9d7a3c9537d6abd4ad47c58fe27862625 / . / arch / arm / mach-omap2 / prm-regbits-44xx.h
blob: 6d2776f6fc08021ad89ce64021477850c9958eec [file] [log] [blame]
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1/*
2 * OMAP44xx Power Management register bits
3 *
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]6 *
7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 *
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 */
21
22#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H
23#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H
24
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]25
26/*
27 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
28 * PRM_LDO_SRAM_MPU_SETUP
29 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]30#define OMAP4430_ABBOFF_ACT_EXPORT_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]31#define OMAP4430_ABBOFF_ACT_EXPORT_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]32
33/*
34 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
35 * PRM_LDO_SRAM_MPU_SETUP
36 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]37#define OMAP4430_ABBOFF_SLEEP_EXPORT_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]38#define OMAP4430_ABBOFF_SLEEP_EXPORT_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]39
40/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]41#define OMAP4430_ABB_IVA_DONE_EN_SHIFT 31
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]42#define OMAP4430_ABB_IVA_DONE_EN_MASK (1 << 31)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]43
44/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]45#define OMAP4430_ABB_IVA_DONE_ST_SHIFT 31
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]46#define OMAP4430_ABB_IVA_DONE_ST_MASK (1 << 31)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]47
48/* Used by PRM_IRQENABLE_MPU_2 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]49#define OMAP4430_ABB_MPU_DONE_EN_SHIFT 7
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]50#define OMAP4430_ABB_MPU_DONE_EN_MASK (1 << 7)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]51
52/* Used by PRM_IRQSTATUS_MPU_2 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]53#define OMAP4430_ABB_MPU_DONE_ST_SHIFT 7
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]54#define OMAP4430_ABB_MPU_DONE_ST_MASK (1 << 7)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]55
56/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]57#define OMAP4430_ACTIVE_FBB_SEL_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]58#define OMAP4430_ACTIVE_FBB_SEL_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]59
60/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]61#define OMAP4430_ACTIVE_RBB_SEL_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]62#define OMAP4430_ACTIVE_RBB_SEL_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]63
64/* Used by PM_ABE_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]65#define OMAP4430_AESSMEM_ONSTATE_SHIFT 16
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]66#define OMAP4430_AESSMEM_ONSTATE_MASK (0x3 << 16)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]67
68/* Used by PM_ABE_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]69#define OMAP4430_AESSMEM_RETSTATE_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]70#define OMAP4430_AESSMEM_RETSTATE_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]71
72/* Used by PM_ABE_PWRSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]73#define OMAP4430_AESSMEM_STATEST_SHIFT 4
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]74#define OMAP4430_AESSMEM_STATEST_MASK (0x3 << 4)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]75
76/*
77 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
78 * PRM_LDO_SRAM_MPU_SETUP
79 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]80#define OMAP4430_AIPOFF_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]81#define OMAP4430_AIPOFF_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]82
83/* Used by PRM_VOLTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]84#define OMAP4430_AUTO_CTRL_VDD_CORE_L_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]85#define OMAP4430_AUTO_CTRL_VDD_CORE_L_MASK (0x3 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]86
87/* Used by PRM_VOLTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]88#define OMAP4430_AUTO_CTRL_VDD_IVA_L_SHIFT 4
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]89#define OMAP4430_AUTO_CTRL_VDD_IVA_L_MASK (0x3 << 4)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]90
91/* Used by PRM_VOLTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]92#define OMAP4430_AUTO_CTRL_VDD_MPU_L_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]93#define OMAP4430_AUTO_CTRL_VDD_MPU_L_MASK (0x3 << 2)
94
95/* Used by PRM_VC_ERRST */
96#define OMAP4430_BYPS_RA_ERR_SHIFT 25
97#define OMAP4430_BYPS_RA_ERR_MASK (1 << 25)
98
99/* Used by PRM_VC_ERRST */
100#define OMAP4430_BYPS_SA_ERR_SHIFT 24
101#define OMAP4430_BYPS_SA_ERR_MASK (1 << 24)
102
103/* Used by PRM_VC_ERRST */
104#define OMAP4430_BYPS_TIMEOUT_ERR_SHIFT 26
105#define OMAP4430_BYPS_TIMEOUT_ERR_MASK (1 << 26)
106
107/* Used by PRM_RSTST */
108#define OMAP4430_C2C_RST_SHIFT 10
109#define OMAP4430_C2C_RST_MASK (1 << 10)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]110
111/* Used by PM_CAM_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]112#define OMAP4430_CAM_MEM_ONSTATE_SHIFT 16
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]113#define OMAP4430_CAM_MEM_ONSTATE_MASK (0x3 << 16)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]114
115/* Used by PM_CAM_PWRSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]116#define OMAP4430_CAM_MEM_STATEST_SHIFT 4
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]117#define OMAP4430_CAM_MEM_STATEST_MASK (0x3 << 4)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]118
119/* Used by PRM_CLKREQCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]120#define OMAP4430_CLKREQ_COND_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]121#define OMAP4430_CLKREQ_COND_MASK (0x7 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]122
123/* Used by PRM_VC_VAL_SMPS_RA_CMD */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]124#define OMAP4430_CMDRA_VDD_CORE_L_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]125#define OMAP4430_CMDRA_VDD_CORE_L_MASK (0xff << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]126
127/* Used by PRM_VC_VAL_SMPS_RA_CMD */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]128#define OMAP4430_CMDRA_VDD_IVA_L_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]129#define OMAP4430_CMDRA_VDD_IVA_L_MASK (0xff << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]130
131/* Used by PRM_VC_VAL_SMPS_RA_CMD */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]132#define OMAP4430_CMDRA_VDD_MPU_L_SHIFT 16
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]133#define OMAP4430_CMDRA_VDD_MPU_L_MASK (0xff << 16)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]134
135/* Used by PRM_VC_CFG_CHANNEL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]136#define OMAP4430_CMD_VDD_CORE_L_SHIFT 4
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]137#define OMAP4430_CMD_VDD_CORE_L_MASK (1 << 4)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]138
139/* Used by PRM_VC_CFG_CHANNEL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]140#define OMAP4430_CMD_VDD_IVA_L_SHIFT 12
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]141#define OMAP4430_CMD_VDD_IVA_L_MASK (1 << 12)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]142
143/* Used by PRM_VC_CFG_CHANNEL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]144#define OMAP4430_CMD_VDD_MPU_L_SHIFT 17
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]145#define OMAP4430_CMD_VDD_MPU_L_MASK (1 << 17)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]146
147/* Used by PM_CORE_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]148#define OMAP4430_CORE_OCMRAM_ONSTATE_SHIFT 18
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]149#define OMAP4430_CORE_OCMRAM_ONSTATE_MASK (0x3 << 18)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]150
151/* Used by PM_CORE_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]152#define OMAP4430_CORE_OCMRAM_RETSTATE_SHIFT 9
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]153#define OMAP4430_CORE_OCMRAM_RETSTATE_MASK (1 << 9)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]154
155/* Used by PM_CORE_PWRSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]156#define OMAP4430_CORE_OCMRAM_STATEST_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]157#define OMAP4430_CORE_OCMRAM_STATEST_MASK (0x3 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]158
159/* Used by PM_CORE_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]160#define OMAP4430_CORE_OTHER_BANK_ONSTATE_SHIFT 16
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]161#define OMAP4430_CORE_OTHER_BANK_ONSTATE_MASK (0x3 << 16)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]162
163/* Used by PM_CORE_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]164#define OMAP4430_CORE_OTHER_BANK_RETSTATE_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]165#define OMAP4430_CORE_OTHER_BANK_RETSTATE_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]166
167/* Used by PM_CORE_PWRSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]168#define OMAP4430_CORE_OTHER_BANK_STATEST_SHIFT 4
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]169#define OMAP4430_CORE_OTHER_BANK_STATEST_MASK (0x3 << 4)
170
171/* Used by REVISION_PRM */
172#define OMAP4430_CUSTOM_SHIFT 6
173#define OMAP4430_CUSTOM_MASK (0x3 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]174
175/* Used by PRM_VC_VAL_BYPASS */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]176#define OMAP4430_DATA_SHIFT 16
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]177#define OMAP4430_DATA_MASK (0xff << 16)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]178
179/* Used by PRM_DEVICE_OFF_CTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]180#define OMAP4430_DEVICE_OFF_ENABLE_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]181#define OMAP4430_DEVICE_OFF_ENABLE_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]182
183/* Used by PRM_VC_CFG_I2C_MODE */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]184#define OMAP4430_DFILTEREN_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]185#define OMAP4430_DFILTEREN_MASK (1 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]186
187/*
188 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
189 * PRM_LDO_SRAM_MPU_SETUP, PRM_SRAM_WKUP_SETUP
190 */
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]191#define OMAP4430_DISABLE_RTA_EXPORT_SHIFT 0
192#define OMAP4430_DISABLE_RTA_EXPORT_MASK (1 << 0)
193
194/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */
195#define OMAP4430_DPLL_ABE_RECAL_EN_SHIFT 4
196#define OMAP4430_DPLL_ABE_RECAL_EN_MASK (1 << 4)
197
198/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */
199#define OMAP4430_DPLL_ABE_RECAL_ST_SHIFT 4
200#define OMAP4430_DPLL_ABE_RECAL_ST_MASK (1 << 4)
201
202/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
203#define OMAP4430_DPLL_CORE_RECAL_EN_SHIFT 0
204#define OMAP4430_DPLL_CORE_RECAL_EN_MASK (1 << 0)
205
206/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
207#define OMAP4430_DPLL_CORE_RECAL_ST_SHIFT 0
208#define OMAP4430_DPLL_CORE_RECAL_ST_MASK (1 << 0)
209
210/* Used by PRM_IRQENABLE_MPU */
211#define OMAP4430_DPLL_DDRPHY_RECAL_EN_SHIFT 6
212#define OMAP4430_DPLL_DDRPHY_RECAL_EN_MASK (1 << 6)
213
214/* Used by PRM_IRQSTATUS_MPU */
215#define OMAP4430_DPLL_DDRPHY_RECAL_ST_SHIFT 6
216#define OMAP4430_DPLL_DDRPHY_RECAL_ST_MASK (1 << 6)
217
218/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */
219#define OMAP4430_DPLL_IVA_RECAL_EN_SHIFT 2
220#define OMAP4430_DPLL_IVA_RECAL_EN_MASK (1 << 2)
221
222/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */
223#define OMAP4430_DPLL_IVA_RECAL_ST_SHIFT 2
224#define OMAP4430_DPLL_IVA_RECAL_ST_MASK (1 << 2)
225
226/* Used by PRM_IRQENABLE_MPU */
227#define OMAP4430_DPLL_MPU_RECAL_EN_SHIFT 1
228#define OMAP4430_DPLL_MPU_RECAL_EN_MASK (1 << 1)
229
230/* Used by PRM_IRQSTATUS_MPU */
231#define OMAP4430_DPLL_MPU_RECAL_ST_SHIFT 1
232#define OMAP4430_DPLL_MPU_RECAL_ST_MASK (1 << 1)
233
234/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
235#define OMAP4430_DPLL_PER_RECAL_EN_SHIFT 3
236#define OMAP4430_DPLL_PER_RECAL_EN_MASK (1 << 3)
237
238/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
239#define OMAP4430_DPLL_PER_RECAL_ST_SHIFT 3
240#define OMAP4430_DPLL_PER_RECAL_ST_MASK (1 << 3)
241
242/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
243#define OMAP4430_DPLL_UNIPRO_RECAL_EN_SHIFT 7
244#define OMAP4430_DPLL_UNIPRO_RECAL_EN_MASK (1 << 7)
245
246/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
247#define OMAP4430_DPLL_UNIPRO_RECAL_ST_SHIFT 7
248#define OMAP4430_DPLL_UNIPRO_RECAL_ST_MASK (1 << 7)
249
250/* Used by PM_DSS_PWRSTCTRL */
251#define OMAP4430_DSS_MEM_ONSTATE_SHIFT 16
252#define OMAP4430_DSS_MEM_ONSTATE_MASK (0x3 << 16)
253
254/* Used by PM_DSS_PWRSTCTRL */
255#define OMAP4430_DSS_MEM_RETSTATE_SHIFT 8
256#define OMAP4430_DSS_MEM_RETSTATE_MASK (1 << 8)
257
258/* Used by PM_DSS_PWRSTST */
259#define OMAP4430_DSS_MEM_STATEST_SHIFT 4
260#define OMAP4430_DSS_MEM_STATEST_MASK (0x3 << 4)
261
262/* Used by PM_CORE_PWRSTCTRL */
263#define OMAP4430_DUCATI_L2RAM_ONSTATE_SHIFT 20
264#define OMAP4430_DUCATI_L2RAM_ONSTATE_MASK (0x3 << 20)
265
266/* Used by PM_CORE_PWRSTCTRL */
267#define OMAP4430_DUCATI_L2RAM_RETSTATE_SHIFT 10
268#define OMAP4430_DUCATI_L2RAM_RETSTATE_MASK (1 << 10)
269
270/* Used by PM_CORE_PWRSTST */
271#define OMAP4430_DUCATI_L2RAM_STATEST_SHIFT 8
272#define OMAP4430_DUCATI_L2RAM_STATEST_MASK (0x3 << 8)
273
274/* Used by PM_CORE_PWRSTCTRL */
275#define OMAP4430_DUCATI_UNICACHE_ONSTATE_SHIFT 22
276#define OMAP4430_DUCATI_UNICACHE_ONSTATE_MASK (0x3 << 22)
277
278/* Used by PM_CORE_PWRSTCTRL */
279#define OMAP4430_DUCATI_UNICACHE_RETSTATE_SHIFT 11
280#define OMAP4430_DUCATI_UNICACHE_RETSTATE_MASK (1 << 11)
281
282/* Used by PM_CORE_PWRSTST */
283#define OMAP4430_DUCATI_UNICACHE_STATEST_SHIFT 10
284#define OMAP4430_DUCATI_UNICACHE_STATEST_MASK (0x3 << 10)
285
286/* Used by RM_MPU_RSTST */
287#define OMAP4430_EMULATION_RST_SHIFT 0
288#define OMAP4430_EMULATION_RST_MASK (1 << 0)
289
290/* Used by RM_DUCATI_RSTST */
291#define OMAP4430_EMULATION_RST1ST_SHIFT 3
292#define OMAP4430_EMULATION_RST1ST_MASK (1 << 3)
293
294/* Used by RM_DUCATI_RSTST */
295#define OMAP4430_EMULATION_RST2ST_SHIFT 4
296#define OMAP4430_EMULATION_RST2ST_MASK (1 << 4)
297
298/* Used by RM_IVAHD_RSTST */
299#define OMAP4430_EMULATION_SEQ1_RST1ST_SHIFT 3
300#define OMAP4430_EMULATION_SEQ1_RST1ST_MASK (1 << 3)
301
302/* Used by RM_IVAHD_RSTST */
303#define OMAP4430_EMULATION_SEQ2_RST2ST_SHIFT 4
304#define OMAP4430_EMULATION_SEQ2_RST2ST_MASK (1 << 4)
305
306/* Used by PM_EMU_PWRSTCTRL */
307#define OMAP4430_EMU_BANK_ONSTATE_SHIFT 16
308#define OMAP4430_EMU_BANK_ONSTATE_MASK (0x3 << 16)
309
310/* Used by PM_EMU_PWRSTST */
311#define OMAP4430_EMU_BANK_STATEST_SHIFT 4
312#define OMAP4430_EMU_BANK_STATEST_MASK (0x3 << 4)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]313
314/*
315 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
316 * PRM_LDO_SRAM_MPU_SETUP
317 */
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]318#define OMAP4430_ENFUNC1_EXPORT_SHIFT 3
319#define OMAP4430_ENFUNC1_EXPORT_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]320
321/*
322 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
323 * PRM_LDO_SRAM_MPU_SETUP
324 */
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]325#define OMAP4430_ENFUNC3_EXPORT_SHIFT 5
326#define OMAP4430_ENFUNC3_EXPORT_MASK (1 << 5)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]327
328/*
329 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
330 * PRM_LDO_SRAM_MPU_SETUP
331 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]332#define OMAP4430_ENFUNC4_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]333#define OMAP4430_ENFUNC4_MASK (1 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]334
335/*
336 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
337 * PRM_LDO_SRAM_MPU_SETUP
338 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]339#define OMAP4430_ENFUNC5_SHIFT 7
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]340#define OMAP4430_ENFUNC5_MASK (1 << 7)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]341
342/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]343#define OMAP4430_ERRORGAIN_SHIFT 16
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]344#define OMAP4430_ERRORGAIN_MASK (0xff << 16)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]345
346/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]347#define OMAP4430_ERROROFFSET_SHIFT 24
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]348#define OMAP4430_ERROROFFSET_MASK (0xff << 24)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]349
350/* Used by PRM_RSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]351#define OMAP4430_EXTERNAL_WARM_RST_SHIFT 5
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]352#define OMAP4430_EXTERNAL_WARM_RST_MASK (1 << 5)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]353
354/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]355#define OMAP4430_FORCEUPDATE_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]356#define OMAP4430_FORCEUPDATE_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]357
358/* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]359#define OMAP4430_FORCEUPDATEWAIT_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]360#define OMAP4430_FORCEUPDATEWAIT_MASK (0xffffff << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]361
362/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_TESLA */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]363#define OMAP4430_FORCEWKUP_EN_SHIFT 10
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]364#define OMAP4430_FORCEWKUP_EN_MASK (1 << 10)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]365
366/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_TESLA */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]367#define OMAP4430_FORCEWKUP_ST_SHIFT 10
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]368#define OMAP4430_FORCEWKUP_ST_MASK (1 << 10)
369
370/* Used by REVISION_PRM */
371#define OMAP4430_FUNC_SHIFT 16
372#define OMAP4430_FUNC_MASK (0xfff << 16)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]373
374/* Used by PM_GFX_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]375#define OMAP4430_GFX_MEM_ONSTATE_SHIFT 16
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]376#define OMAP4430_GFX_MEM_ONSTATE_MASK (0x3 << 16)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]377
378/* Used by PM_GFX_PWRSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]379#define OMAP4430_GFX_MEM_STATEST_SHIFT 4
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]380#define OMAP4430_GFX_MEM_STATEST_MASK (0x3 << 4)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]381
382/* Used by PRM_RSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]383#define OMAP4430_GLOBAL_COLD_RST_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]384#define OMAP4430_GLOBAL_COLD_RST_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]385
386/* Used by PRM_RSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]387#define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]388#define OMAP4430_GLOBAL_WARM_SW_RST_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]389
390/* Used by PRM_IO_PMCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]391#define OMAP4430_GLOBAL_WUEN_SHIFT 16
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]392#define OMAP4430_GLOBAL_WUEN_MASK (1 << 16)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]393
394/* Used by PRM_VC_CFG_I2C_MODE */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]395#define OMAP4430_HSMCODE_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]396#define OMAP4430_HSMCODE_MASK (0x7 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]397
398/* Used by PRM_VC_CFG_I2C_MODE */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]399#define OMAP4430_HSMODEEN_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]400#define OMAP4430_HSMODEEN_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]401
402/* Used by PRM_VC_CFG_I2C_CLK */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]403#define OMAP4430_HSSCLH_SHIFT 16
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]404#define OMAP4430_HSSCLH_MASK (0xff << 16)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]405
406/* Used by PRM_VC_CFG_I2C_CLK */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]407#define OMAP4430_HSSCLL_SHIFT 24
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]408#define OMAP4430_HSSCLL_MASK (0xff << 24)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]409
410/* Used by PM_IVAHD_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]411#define OMAP4430_HWA_MEM_ONSTATE_SHIFT 16
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]412#define OMAP4430_HWA_MEM_ONSTATE_MASK (0x3 << 16)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]413
414/* Used by PM_IVAHD_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]415#define OMAP4430_HWA_MEM_RETSTATE_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]416#define OMAP4430_HWA_MEM_RETSTATE_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]417
418/* Used by PM_IVAHD_PWRSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]419#define OMAP4430_HWA_MEM_STATEST_SHIFT 4
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]420#define OMAP4430_HWA_MEM_STATEST_MASK (0x3 << 4)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]421
422/* Used by RM_MPU_RSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]423#define OMAP4430_ICECRUSHER_MPU_RST_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]424#define OMAP4430_ICECRUSHER_MPU_RST_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]425
426/* Used by RM_DUCATI_RSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]427#define OMAP4430_ICECRUSHER_RST1ST_SHIFT 5
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]428#define OMAP4430_ICECRUSHER_RST1ST_MASK (1 << 5)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]429
430/* Used by RM_DUCATI_RSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]431#define OMAP4430_ICECRUSHER_RST2ST_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]432#define OMAP4430_ICECRUSHER_RST2ST_MASK (1 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]433
434/* Used by RM_IVAHD_RSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]435#define OMAP4430_ICECRUSHER_SEQ1_RST1ST_SHIFT 5
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]436#define OMAP4430_ICECRUSHER_SEQ1_RST1ST_MASK (1 << 5)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]437
438/* Used by RM_IVAHD_RSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]439#define OMAP4430_ICECRUSHER_SEQ2_RST2ST_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]440#define OMAP4430_ICECRUSHER_SEQ2_RST2ST_MASK (1 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]441
442/* Used by PRM_RSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]443#define OMAP4430_ICEPICK_RST_SHIFT 9
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]444#define OMAP4430_ICEPICK_RST_MASK (1 << 9)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]445
446/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]447#define OMAP4430_INITVDD_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]448#define OMAP4430_INITVDD_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]449
450/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]451#define OMAP4430_INITVOLTAGE_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]452#define OMAP4430_INITVOLTAGE_MASK (0xff << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]453
454/*
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]455 * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST,
456 * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST,
457 * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]458 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]459#define OMAP4430_INTRANSITION_SHIFT 20
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]460#define OMAP4430_INTRANSITION_MASK (1 << 20)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]461
462/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]463#define OMAP4430_IO_EN_SHIFT 9
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]464#define OMAP4430_IO_EN_MASK (1 << 9)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]465
466/* Used by PRM_IO_PMCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]467#define OMAP4430_IO_ON_STATUS_SHIFT 5
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]468#define OMAP4430_IO_ON_STATUS_MASK (1 << 5)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]469
470/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]471#define OMAP4430_IO_ST_SHIFT 9
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]472#define OMAP4430_IO_ST_MASK (1 << 9)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]473
474/* Used by PRM_IO_PMCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]475#define OMAP4430_ISOCLK_OVERRIDE_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]476#define OMAP4430_ISOCLK_OVERRIDE_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]477
478/* Used by PRM_IO_PMCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]479#define OMAP4430_ISOCLK_STATUS_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]480#define OMAP4430_ISOCLK_STATUS_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]481
482/* Used by PRM_IO_PMCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]483#define OMAP4430_ISOOVR_EXTEND_SHIFT 4
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]484#define OMAP4430_ISOOVR_EXTEND_MASK (1 << 4)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]485
486/* Used by PRM_IO_COUNT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]487#define OMAP4430_ISO_2_ON_TIME_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]488#define OMAP4430_ISO_2_ON_TIME_MASK (0xff << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]489
490/* Used by PM_L3INIT_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]491#define OMAP4430_L3INIT_BANK1_ONSTATE_SHIFT 16
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]492#define OMAP4430_L3INIT_BANK1_ONSTATE_MASK (0x3 << 16)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]493
494/* Used by PM_L3INIT_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]495#define OMAP4430_L3INIT_BANK1_RETSTATE_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]496#define OMAP4430_L3INIT_BANK1_RETSTATE_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]497
498/* Used by PM_L3INIT_PWRSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]499#define OMAP4430_L3INIT_BANK1_STATEST_SHIFT 4
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]500#define OMAP4430_L3INIT_BANK1_STATEST_MASK (0x3 << 4)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]501
502/*
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]503 * Used by PM_ABE_PWRSTST, PM_CORE_PWRSTST, PM_IVAHD_PWRSTST,
504 * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST
505 */
506#define OMAP4430_LASTPOWERSTATEENTERED_SHIFT 24
507#define OMAP4430_LASTPOWERSTATEENTERED_MASK (0x3 << 24)
508
509/*
510 * Used by PM_ABE_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL,
511 * PM_IVAHD_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL,
512 * PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]513 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]514#define OMAP4430_LOGICRETSTATE_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]515#define OMAP4430_LOGICRETSTATE_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]516
517/*
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]518 * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST,
519 * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST,
520 * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]521 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]522#define OMAP4430_LOGICSTATEST_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]523#define OMAP4430_LOGICSTATEST_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]524
525/*
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]526 * Used by RM_ABE_AESS_CONTEXT, RM_ABE_DMIC_CONTEXT, RM_ABE_MCASP_CONTEXT,
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]527 * RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, RM_ABE_MCBSP3_CONTEXT,
528 * RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT, RM_ABE_TIMER5_CONTEXT,
529 * RM_ABE_TIMER6_CONTEXT, RM_ABE_TIMER7_CONTEXT, RM_ABE_TIMER8_CONTEXT,
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]530 * RM_ABE_WDT3_CONTEXT, RM_ALWON_MDMINTC_CONTEXT, RM_ALWON_SR_CORE_CONTEXT,
531 * RM_ALWON_SR_IVA_CONTEXT, RM_ALWON_SR_MPU_CONTEXT, RM_CAM_FDIF_CONTEXT,
532 * RM_CAM_ISS_CONTEXT, RM_CEFUSE_CEFUSE_CONTEXT, RM_D2D_SAD2D_CONTEXT,
533 * RM_D2D_SAD2D_FW_CONTEXT, RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT,
534 * RM_DUCATI_DUCATI_CONTEXT, RM_EMU_DEBUGSS_CONTEXT, RM_GFX_GFX_CONTEXT,
535 * RM_IVAHD_IVAHD_CONTEXT, RM_IVAHD_SL2_CONTEXT, RM_L3INIT_CCPTX_CONTEXT,
536 * RM_L3INIT_EMAC_CONTEXT, RM_L3INIT_P1500_CONTEXT, RM_L3INIT_PCIESS_CONTEXT,
537 * RM_L3INIT_SATA_CONTEXT, RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT,
538 * RM_L3INIT_USBPHYOCP2SCP_CONTEXT, RM_L3INIT_XHPI_CONTEXT,
539 * RM_L3INSTR_L3_3_CONTEXT, RM_L3INSTR_L3_INSTR_CONTEXT,
540 * RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_L3_2_CONTEXT,
541 * RM_L3_2_OCMC_RAM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_SAR_ROM_CONTEXT,
542 * RM_L4PER_ADC_CONTEXT, RM_L4PER_DMTIMER10_CONTEXT,
543 * RM_L4PER_DMTIMER11_CONTEXT, RM_L4PER_DMTIMER2_CONTEXT,
544 * RM_L4PER_DMTIMER3_CONTEXT, RM_L4PER_DMTIMER4_CONTEXT,
545 * RM_L4PER_DMTIMER9_CONTEXT, RM_L4PER_ELM_CONTEXT, RM_L4PER_HDQ1W_CONTEXT,
546 * RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT, RM_L4PER_I2C2_CONTEXT,
547 * RM_L4PER_I2C3_CONTEXT, RM_L4PER_I2C4_CONTEXT, RM_L4PER_I2C5_CONTEXT,
548 * RM_L4PER_L4_PER_CONTEXT, RM_L4PER_MCASP2_CONTEXT, RM_L4PER_MCASP3_CONTEXT,
549 * RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MCSPI1_CONTEXT, RM_L4PER_MCSPI2_CONTEXT,
550 * RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT, RM_L4PER_MGATE_CONTEXT,
551 * RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT, RM_L4PER_MMCSD5_CONTEXT,
552 * RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT,
553 * RM_L4SEC_PKAEIP29_CONTEXT, RM_MEMIF_DLL_CONTEXT, RM_MEMIF_DLL_H_CONTEXT,
554 * RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, RM_MEMIF_EMIF_2_CONTEXT,
555 * RM_MEMIF_EMIF_FW_CONTEXT, RM_MPU_MPU_CONTEXT, RM_TESLA_TESLA_CONTEXT,
556 * RM_WKUP_GPIO1_CONTEXT, RM_WKUP_KEYBOARD_CONTEXT, RM_WKUP_L4WKUP_CONTEXT,
557 * RM_WKUP_RTC_CONTEXT, RM_WKUP_SARRAM_CONTEXT, RM_WKUP_SYNCTIMER_CONTEXT,
558 * RM_WKUP_TIMER12_CONTEXT, RM_WKUP_TIMER1_CONTEXT, RM_WKUP_USIM_CONTEXT,
559 * RM_WKUP_WDT1_CONTEXT, RM_WKUP_WDT2_CONTEXT
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]560 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]561#define OMAP4430_LOSTCONTEXT_DFF_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]562#define OMAP4430_LOSTCONTEXT_DFF_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]563
564/*
565 * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_D2D_SAD2D_CONTEXT,
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]566 * RM_D2D_SAD2D_FW_CONTEXT, RM_DSS_DSS_CONTEXT, RM_DUCATI_DUCATI_CONTEXT,
567 * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT,
568 * RM_L3INIT_MMC6_CONTEXT, RM_L3INIT_USB_HOST_CONTEXT,
569 * RM_L3INIT_USB_HOST_FS_CONTEXT, RM_L3INIT_USB_OTG_CONTEXT,
570 * RM_L3INIT_USB_TLL_CONTEXT, RM_L3INSTR_L3_3_CONTEXT,
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]571 * RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_GPMC_CONTEXT,
572 * RM_L3_2_L3_2_CONTEXT, RM_L4CFG_HW_SEM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT,
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]573 * RM_L4CFG_MAILBOX_CONTEXT, RM_L4PER_GPIO2_CONTEXT, RM_L4PER_GPIO3_CONTEXT,
574 * RM_L4PER_GPIO4_CONTEXT, RM_L4PER_GPIO5_CONTEXT, RM_L4PER_GPIO6_CONTEXT,
575 * RM_L4PER_I2C1_CONTEXT, RM_L4PER_L4_PER_CONTEXT, RM_L4PER_UART1_CONTEXT,
576 * RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT,
577 * RM_L4SEC_AES1_CONTEXT, RM_L4SEC_AES2_CONTEXT, RM_L4SEC_CRYPTODMA_CONTEXT,
578 * RM_L4SEC_DES3DES_CONTEXT, RM_L4SEC_RNG_CONTEXT, RM_L4SEC_SHA2MD51_CONTEXT,
579 * RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, RM_MEMIF_EMIF_2_CONTEXT,
580 * RM_MEMIF_EMIF_FW_CONTEXT, RM_MEMIF_EMIF_H1_CONTEXT,
581 * RM_MEMIF_EMIF_H2_CONTEXT, RM_SDMA_SDMA_CONTEXT, RM_TESLA_TESLA_CONTEXT
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]582 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]583#define OMAP4430_LOSTCONTEXT_RFF_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]584#define OMAP4430_LOSTCONTEXT_RFF_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]585
586/* Used by RM_ABE_AESS_CONTEXT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]587#define OMAP4430_LOSTMEM_AESSMEM_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]588#define OMAP4430_LOSTMEM_AESSMEM_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]589
590/* Used by RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]591#define OMAP4430_LOSTMEM_CAM_MEM_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]592#define OMAP4430_LOSTMEM_CAM_MEM_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]593
594/* Used by RM_L3INSTR_OCP_WP1_CONTEXT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]595#define OMAP4430_LOSTMEM_CORE_NRET_BANK_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]596#define OMAP4430_LOSTMEM_CORE_NRET_BANK_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]597
598/* Renamed from LOSTMEM_CORE_NRET_BANK Used by RM_MEMIF_DMM_CONTEXT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]599#define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_SHIFT 9
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]600#define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_MASK (1 << 9)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]601
602/* Used by RM_L3_2_OCMC_RAM_CONTEXT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]603#define OMAP4430_LOSTMEM_CORE_OCMRAM_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]604#define OMAP4430_LOSTMEM_CORE_OCMRAM_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]605
606/*
607 * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_MEMIF_DMM_CONTEXT,
608 * RM_SDMA_SDMA_CONTEXT
609 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]610#define OMAP4430_LOSTMEM_CORE_OTHER_BANK_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]611#define OMAP4430_LOSTMEM_CORE_OTHER_BANK_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]612
613/* Used by RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]614#define OMAP4430_LOSTMEM_DSS_MEM_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]615#define OMAP4430_LOSTMEM_DSS_MEM_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]616
617/* Used by RM_DUCATI_DUCATI_CONTEXT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]618#define OMAP4430_LOSTMEM_DUCATI_L2RAM_SHIFT 9
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]619#define OMAP4430_LOSTMEM_DUCATI_L2RAM_MASK (1 << 9)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]620
621/* Used by RM_DUCATI_DUCATI_CONTEXT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]622#define OMAP4430_LOSTMEM_DUCATI_UNICACHE_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]623#define OMAP4430_LOSTMEM_DUCATI_UNICACHE_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]624
625/* Used by RM_EMU_DEBUGSS_CONTEXT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]626#define OMAP4430_LOSTMEM_EMU_BANK_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]627#define OMAP4430_LOSTMEM_EMU_BANK_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]628
629/* Used by RM_GFX_GFX_CONTEXT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]630#define OMAP4430_LOSTMEM_GFX_MEM_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]631#define OMAP4430_LOSTMEM_GFX_MEM_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]632
633/* Used by RM_IVAHD_IVAHD_CONTEXT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]634#define OMAP4430_LOSTMEM_HWA_MEM_SHIFT 10
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]635#define OMAP4430_LOSTMEM_HWA_MEM_MASK (1 << 10)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]636
637/*
638 * Used by RM_L3INIT_CCPTX_CONTEXT, RM_L3INIT_EMAC_CONTEXT,
639 * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT,
640 * RM_L3INIT_MMC6_CONTEXT, RM_L3INIT_PCIESS_CONTEXT, RM_L3INIT_SATA_CONTEXT,
641 * RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT,
642 * RM_L3INIT_USB_OTG_CONTEXT, RM_L3INIT_XHPI_CONTEXT
643 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]644#define OMAP4430_LOSTMEM_L3INIT_BANK1_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]645#define OMAP4430_LOSTMEM_L3INIT_BANK1_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]646
647/* Used by RM_MPU_MPU_CONTEXT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]648#define OMAP4430_LOSTMEM_MPU_L1_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]649#define OMAP4430_LOSTMEM_MPU_L1_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]650
651/* Used by RM_MPU_MPU_CONTEXT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]652#define OMAP4430_LOSTMEM_MPU_L2_SHIFT 9
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]653#define OMAP4430_LOSTMEM_MPU_L2_MASK (1 << 9)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]654
655/* Used by RM_MPU_MPU_CONTEXT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]656#define OMAP4430_LOSTMEM_MPU_RAM_SHIFT 10
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]657#define OMAP4430_LOSTMEM_MPU_RAM_MASK (1 << 10)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]658
659/*
660 * Used by RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT,
661 * RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT,
662 * RM_L4PER_MMCSD5_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT
663 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]664#define OMAP4430_LOSTMEM_NONRETAINED_BANK_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]665#define OMAP4430_LOSTMEM_NONRETAINED_BANK_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]666
667/*
668 * Used by RM_ABE_DMIC_CONTEXT, RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT,
669 * RM_ABE_MCBSP3_CONTEXT, RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT
670 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]671#define OMAP4430_LOSTMEM_PERIHPMEM_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]672#define OMAP4430_LOSTMEM_PERIHPMEM_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]673
674/*
675 * Used by RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_UART1_CONTEXT,
676 * RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT,
677 * RM_L4SEC_CRYPTODMA_CONTEXT
678 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]679#define OMAP4430_LOSTMEM_RETAINED_BANK_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]680#define OMAP4430_LOSTMEM_RETAINED_BANK_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]681
682/* Used by RM_IVAHD_SL2_CONTEXT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]683#define OMAP4430_LOSTMEM_SL2_MEM_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]684#define OMAP4430_LOSTMEM_SL2_MEM_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]685
686/* Used by RM_IVAHD_IVAHD_CONTEXT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]687#define OMAP4430_LOSTMEM_TCM1_MEM_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]688#define OMAP4430_LOSTMEM_TCM1_MEM_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]689
690/* Used by RM_IVAHD_IVAHD_CONTEXT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]691#define OMAP4430_LOSTMEM_TCM2_MEM_SHIFT 9
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]692#define OMAP4430_LOSTMEM_TCM2_MEM_MASK (1 << 9)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]693
694/* Used by RM_TESLA_TESLA_CONTEXT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]695#define OMAP4430_LOSTMEM_TESLA_EDMA_SHIFT 10
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]696#define OMAP4430_LOSTMEM_TESLA_EDMA_MASK (1 << 10)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]697
698/* Used by RM_TESLA_TESLA_CONTEXT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]699#define OMAP4430_LOSTMEM_TESLA_L1_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]700#define OMAP4430_LOSTMEM_TESLA_L1_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]701
702/* Used by RM_TESLA_TESLA_CONTEXT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]703#define OMAP4430_LOSTMEM_TESLA_L2_SHIFT 9
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]704#define OMAP4430_LOSTMEM_TESLA_L2_MASK (1 << 9)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]705
706/* Used by RM_WKUP_SARRAM_CONTEXT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]707#define OMAP4430_LOSTMEM_WKUP_BANK_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]708#define OMAP4430_LOSTMEM_WKUP_BANK_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]709
710/*
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]711 * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL,
712 * PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_IVAHD_PWRSTCTRL,
713 * PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]714 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]715#define OMAP4430_LOWPOWERSTATECHANGE_SHIFT 4
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]716#define OMAP4430_LOWPOWERSTATECHANGE_MASK (1 << 4)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]717
718/* Used by PRM_MODEM_IF_CTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]719#define OMAP4430_MODEM_READY_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]720#define OMAP4430_MODEM_READY_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]721
722/* Used by PRM_MODEM_IF_CTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]723#define OMAP4430_MODEM_SHUTDOWN_IRQ_SHIFT 9
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]724#define OMAP4430_MODEM_SHUTDOWN_IRQ_MASK (1 << 9)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]725
726/* Used by PRM_MODEM_IF_CTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]727#define OMAP4430_MODEM_SLEEP_ST_SHIFT 16
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]728#define OMAP4430_MODEM_SLEEP_ST_MASK (1 << 16)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]729
730/* Used by PRM_MODEM_IF_CTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]731#define OMAP4430_MODEM_WAKE_IRQ_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]732#define OMAP4430_MODEM_WAKE_IRQ_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]733
734/* Used by PM_MPU_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]735#define OMAP4430_MPU_L1_ONSTATE_SHIFT 16
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]736#define OMAP4430_MPU_L1_ONSTATE_MASK (0x3 << 16)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]737
738/* Used by PM_MPU_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]739#define OMAP4430_MPU_L1_RETSTATE_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]740#define OMAP4430_MPU_L1_RETSTATE_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]741
742/* Used by PM_MPU_PWRSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]743#define OMAP4430_MPU_L1_STATEST_SHIFT 4
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]744#define OMAP4430_MPU_L1_STATEST_MASK (0x3 << 4)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]745
746/* Used by PM_MPU_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]747#define OMAP4430_MPU_L2_ONSTATE_SHIFT 18
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]748#define OMAP4430_MPU_L2_ONSTATE_MASK (0x3 << 18)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]749
750/* Used by PM_MPU_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]751#define OMAP4430_MPU_L2_RETSTATE_SHIFT 9
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]752#define OMAP4430_MPU_L2_RETSTATE_MASK (1 << 9)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]753
754/* Used by PM_MPU_PWRSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]755#define OMAP4430_MPU_L2_STATEST_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]756#define OMAP4430_MPU_L2_STATEST_MASK (0x3 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]757
758/* Used by PM_MPU_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]759#define OMAP4430_MPU_RAM_ONSTATE_SHIFT 20
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]760#define OMAP4430_MPU_RAM_ONSTATE_MASK (0x3 << 20)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]761
762/* Used by PM_MPU_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]763#define OMAP4430_MPU_RAM_RETSTATE_SHIFT 10
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]764#define OMAP4430_MPU_RAM_RETSTATE_MASK (1 << 10)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]765
766/* Used by PM_MPU_PWRSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]767#define OMAP4430_MPU_RAM_STATEST_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]768#define OMAP4430_MPU_RAM_STATEST_MASK (0x3 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]769
770/* Used by PRM_RSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]771#define OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]772#define OMAP4430_MPU_SECURITY_VIOL_RST_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]773
774/* Used by PRM_RSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]775#define OMAP4430_MPU_WDT_RST_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]776#define OMAP4430_MPU_WDT_RST_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]777
778/* Used by PM_L4PER_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]779#define OMAP4430_NONRETAINED_BANK_ONSTATE_SHIFT 18
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]780#define OMAP4430_NONRETAINED_BANK_ONSTATE_MASK (0x3 << 18)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]781
782/* Used by PM_L4PER_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]783#define OMAP4430_NONRETAINED_BANK_RETSTATE_SHIFT 9
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]784#define OMAP4430_NONRETAINED_BANK_RETSTATE_MASK (1 << 9)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]785
786/* Used by PM_L4PER_PWRSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]787#define OMAP4430_NONRETAINED_BANK_STATEST_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]788#define OMAP4430_NONRETAINED_BANK_STATEST_MASK (0x3 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]789
790/* Used by PM_CORE_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]791#define OMAP4430_OCP_NRET_BANK_ONSTATE_SHIFT 24
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]792#define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK (0x3 << 24)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]793
794/* Used by PM_CORE_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]795#define OMAP4430_OCP_NRET_BANK_RETSTATE_SHIFT 12
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]796#define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK (1 << 12)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]797
798/* Used by PM_CORE_PWRSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]799#define OMAP4430_OCP_NRET_BANK_STATEST_SHIFT 12
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]800#define OMAP4430_OCP_NRET_BANK_STATEST_MASK (0x3 << 12)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]801
802/*
803 * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
804 * PRM_VC_VAL_CMD_VDD_MPU_L
805 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]806#define OMAP4430_OFF_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]807#define OMAP4430_OFF_MASK (0xff << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]808
809/*
810 * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
811 * PRM_VC_VAL_CMD_VDD_MPU_L
812 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]813#define OMAP4430_ON_SHIFT 24
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]814#define OMAP4430_ON_MASK (0xff << 24)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]815
816/*
817 * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
818 * PRM_VC_VAL_CMD_VDD_MPU_L
819 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]820#define OMAP4430_ONLP_SHIFT 16
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]821#define OMAP4430_ONLP_MASK (0xff << 16)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]822
823/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]824#define OMAP4430_OPP_CHANGE_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]825#define OMAP4430_OPP_CHANGE_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]826
827/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]828#define OMAP4430_OPP_SEL_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]829#define OMAP4430_OPP_SEL_MASK (0x3 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]830
831/* Used by PRM_SRAM_COUNT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]832#define OMAP4430_PCHARGECNT_VALUE_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]833#define OMAP4430_PCHARGECNT_VALUE_MASK (0x3f << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]834
835/* Used by PRM_PSCON_COUNT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]836#define OMAP4430_PCHARGE_TIME_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]837#define OMAP4430_PCHARGE_TIME_MASK (0xff << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]838
839/* Used by PM_ABE_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]840#define OMAP4430_PERIPHMEM_ONSTATE_SHIFT 20
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]841#define OMAP4430_PERIPHMEM_ONSTATE_MASK (0x3 << 20)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]842
843/* Used by PM_ABE_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]844#define OMAP4430_PERIPHMEM_RETSTATE_SHIFT 10
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]845#define OMAP4430_PERIPHMEM_RETSTATE_MASK (1 << 10)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]846
847/* Used by PM_ABE_PWRSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]848#define OMAP4430_PERIPHMEM_STATEST_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]849#define OMAP4430_PERIPHMEM_STATEST_MASK (0x3 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]850
851/* Used by PRM_PHASE1_CNDP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]852#define OMAP4430_PHASE1_CNDP_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]853#define OMAP4430_PHASE1_CNDP_MASK (0xffffffff << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]854
855/* Used by PRM_PHASE2A_CNDP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]856#define OMAP4430_PHASE2A_CNDP_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]857#define OMAP4430_PHASE2A_CNDP_MASK (0xffffffff << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]858
859/* Used by PRM_PHASE2B_CNDP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]860#define OMAP4430_PHASE2B_CNDP_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]861#define OMAP4430_PHASE2B_CNDP_MASK (0xffffffff << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]862
863/* Used by PRM_PSCON_COUNT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]864#define OMAP4430_PONOUT_2_PGOODIN_TIME_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]865#define OMAP4430_PONOUT_2_PGOODIN_TIME_MASK (0xff << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]866
867/*
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]868 * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL,
869 * PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_EMU_PWRSTCTRL, PM_GFX_PWRSTCTRL,
870 * PM_IVAHD_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL,
871 * PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]872 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]873#define OMAP4430_POWERSTATE_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]874#define OMAP4430_POWERSTATE_MASK (0x3 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]875
876/*
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]877 * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST,
878 * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST,
879 * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]880 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]881#define OMAP4430_POWERSTATEST_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]882#define OMAP4430_POWERSTATEST_MASK (0x3 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]883
884/* Used by PRM_PWRREQCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]885#define OMAP4430_PWRREQ_COND_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]886#define OMAP4430_PWRREQ_COND_MASK (0x3 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]887
888/* Used by PRM_VC_CFG_CHANNEL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]889#define OMAP4430_RACEN_VDD_CORE_L_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]890#define OMAP4430_RACEN_VDD_CORE_L_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]891
892/* Used by PRM_VC_CFG_CHANNEL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]893#define OMAP4430_RACEN_VDD_IVA_L_SHIFT 11
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]894#define OMAP4430_RACEN_VDD_IVA_L_MASK (1 << 11)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]895
896/* Used by PRM_VC_CFG_CHANNEL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]897#define OMAP4430_RACEN_VDD_MPU_L_SHIFT 20
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]898#define OMAP4430_RACEN_VDD_MPU_L_MASK (1 << 20)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]899
900/* Used by PRM_VC_CFG_CHANNEL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]901#define OMAP4430_RAC_VDD_CORE_L_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]902#define OMAP4430_RAC_VDD_CORE_L_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]903
904/* Used by PRM_VC_CFG_CHANNEL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]905#define OMAP4430_RAC_VDD_IVA_L_SHIFT 10
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]906#define OMAP4430_RAC_VDD_IVA_L_MASK (1 << 10)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]907
908/* Used by PRM_VC_CFG_CHANNEL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]909#define OMAP4430_RAC_VDD_MPU_L_SHIFT 19
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]910#define OMAP4430_RAC_VDD_MPU_L_MASK (1 << 19)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]911
912/*
913 * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
914 * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
915 * PRM_VOLTSETUP_MPU_RET_SLEEP
916 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]917#define OMAP4430_RAMP_DOWN_COUNT_SHIFT 16
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]918#define OMAP4430_RAMP_DOWN_COUNT_MASK (0x3f << 16)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]919
920/*
921 * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
922 * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
923 * PRM_VOLTSETUP_MPU_RET_SLEEP
924 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]925#define OMAP4430_RAMP_DOWN_PRESCAL_SHIFT 24
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]926#define OMAP4430_RAMP_DOWN_PRESCAL_MASK (0x3 << 24)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]927
928/*
929 * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
930 * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
931 * PRM_VOLTSETUP_MPU_RET_SLEEP
932 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]933#define OMAP4430_RAMP_UP_COUNT_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]934#define OMAP4430_RAMP_UP_COUNT_MASK (0x3f << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]935
936/*
937 * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
938 * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
939 * PRM_VOLTSETUP_MPU_RET_SLEEP
940 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]941#define OMAP4430_RAMP_UP_PRESCAL_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]942#define OMAP4430_RAMP_UP_PRESCAL_MASK (0x3 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]943
944/* Used by PRM_VC_CFG_CHANNEL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]945#define OMAP4430_RAV_VDD_CORE_L_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]946#define OMAP4430_RAV_VDD_CORE_L_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]947
948/* Used by PRM_VC_CFG_CHANNEL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]949#define OMAP4430_RAV_VDD_IVA_L_SHIFT 9
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]950#define OMAP4430_RAV_VDD_IVA_L_MASK (1 << 9)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]951
952/* Used by PRM_VC_CFG_CHANNEL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]953#define OMAP4430_RAV_VDD_MPU_L_SHIFT 18
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]954#define OMAP4430_RAV_VDD_MPU_L_MASK (1 << 18)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]955
956/* Used by PRM_VC_VAL_BYPASS */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]957#define OMAP4430_REGADDR_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]958#define OMAP4430_REGADDR_MASK (0xff << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]959
960/*
961 * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
962 * PRM_VC_VAL_CMD_VDD_MPU_L
963 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]964#define OMAP4430_RET_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]965#define OMAP4430_RET_MASK (0xff << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]966
967/* Used by PM_L4PER_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]968#define OMAP4430_RETAINED_BANK_ONSTATE_SHIFT 16
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]969#define OMAP4430_RETAINED_BANK_ONSTATE_MASK (0x3 << 16)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]970
971/* Used by PM_L4PER_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]972#define OMAP4430_RETAINED_BANK_RETSTATE_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]973#define OMAP4430_RETAINED_BANK_RETSTATE_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]974
975/* Used by PM_L4PER_PWRSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]976#define OMAP4430_RETAINED_BANK_STATEST_SHIFT 4
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]977#define OMAP4430_RETAINED_BANK_STATEST_MASK (0x3 << 4)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]978
979/*
980 * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL,
981 * PRM_LDO_SRAM_MPU_CTRL
982 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]983#define OMAP4430_RETMODE_ENABLE_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]984#define OMAP4430_RETMODE_ENABLE_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]985
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]986/* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL, RM_TESLA_RSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]987#define OMAP4430_RST1_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]988#define OMAP4430_RST1_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]989
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]990/* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST, RM_TESLA_RSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]991#define OMAP4430_RST1ST_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]992#define OMAP4430_RST1ST_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]993
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]994/* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL, RM_TESLA_RSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]995#define OMAP4430_RST2_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]996#define OMAP4430_RST2_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]997
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]998/* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST, RM_TESLA_RSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]999#define OMAP4430_RST2ST_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1000#define OMAP4430_RST2ST_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1001
1002/* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1003#define OMAP4430_RST3_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1004#define OMAP4430_RST3_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1005
1006/* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1007#define OMAP4430_RST3ST_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1008#define OMAP4430_RST3ST_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1009
1010/* Used by PRM_RSTTIME */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1011#define OMAP4430_RSTTIME1_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1012#define OMAP4430_RSTTIME1_MASK (0x3ff << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1013
1014/* Used by PRM_RSTTIME */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1015#define OMAP4430_RSTTIME2_SHIFT 10
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1016#define OMAP4430_RSTTIME2_MASK (0x1f << 10)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1017
1018/* Used by PRM_RSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1019#define OMAP4430_RST_GLOBAL_COLD_SW_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1020#define OMAP4430_RST_GLOBAL_COLD_SW_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1021
1022/* Used by PRM_RSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1023#define OMAP4430_RST_GLOBAL_WARM_SW_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1024#define OMAP4430_RST_GLOBAL_WARM_SW_MASK (1 << 0)
1025
1026/* Used by REVISION_PRM */
1027#define OMAP4430_R_RTL_SHIFT 11
1028#define OMAP4430_R_RTL_MASK (0x1f << 11)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1029
1030/* Used by PRM_VC_CFG_CHANNEL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1031#define OMAP4430_SA_VDD_CORE_L_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1032#define OMAP4430_SA_VDD_CORE_L_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1033
1034/* Renamed from SA_VDD_CORE_L Used by PRM_VC_SMPS_SA */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1035#define OMAP4430_SA_VDD_CORE_L_0_6_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1036#define OMAP4430_SA_VDD_CORE_L_0_6_MASK (0x7f << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1037
1038/* Used by PRM_VC_CFG_CHANNEL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1039#define OMAP4430_SA_VDD_IVA_L_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1040#define OMAP4430_SA_VDD_IVA_L_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1041
1042/* Renamed from SA_VDD_IVA_L Used by PRM_VC_SMPS_SA */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1043#define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1044#define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK (0x7f << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1045
1046/* Used by PRM_VC_CFG_CHANNEL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1047#define OMAP4430_SA_VDD_MPU_L_SHIFT 16
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1048#define OMAP4430_SA_VDD_MPU_L_MASK (1 << 16)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1049
1050/* Renamed from SA_VDD_MPU_L Used by PRM_VC_SMPS_SA */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1051#define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT 16
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1052#define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK (0x7f << 16)
1053
1054/* Used by REVISION_PRM */
1055#define OMAP4430_SCHEME_SHIFT 30
1056#define OMAP4430_SCHEME_MASK (0x3 << 30)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1057
1058/* Used by PRM_VC_CFG_I2C_CLK */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1059#define OMAP4430_SCLH_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1060#define OMAP4430_SCLH_MASK (0xff << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1061
1062/* Used by PRM_VC_CFG_I2C_CLK */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1063#define OMAP4430_SCLL_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1064#define OMAP4430_SCLL_MASK (0xff << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1065
1066/* Used by PRM_RSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1067#define OMAP4430_SECURE_WDT_RST_SHIFT 4
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1068#define OMAP4430_SECURE_WDT_RST_MASK (1 << 4)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1069
1070/* Used by PM_IVAHD_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1071#define OMAP4430_SL2_MEM_ONSTATE_SHIFT 18
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1072#define OMAP4430_SL2_MEM_ONSTATE_MASK (0x3 << 18)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1073
1074/* Used by PM_IVAHD_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1075#define OMAP4430_SL2_MEM_RETSTATE_SHIFT 9
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1076#define OMAP4430_SL2_MEM_RETSTATE_MASK (1 << 9)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1077
1078/* Used by PM_IVAHD_PWRSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1079#define OMAP4430_SL2_MEM_STATEST_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1080#define OMAP4430_SL2_MEM_STATEST_MASK (0x3 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1081
1082/* Used by PRM_VC_VAL_BYPASS */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1083#define OMAP4430_SLAVEADDR_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1084#define OMAP4430_SLAVEADDR_MASK (0x7f << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1085
1086/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1087#define OMAP4430_SLEEP_RBB_SEL_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1088#define OMAP4430_SLEEP_RBB_SEL_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1089
1090/* Used by PRM_SRAM_COUNT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1091#define OMAP4430_SLPCNT_VALUE_SHIFT 16
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1092#define OMAP4430_SLPCNT_VALUE_MASK (0xff << 16)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1093
1094/* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1095#define OMAP4430_SMPSWAITTIMEMAX_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1096#define OMAP4430_SMPSWAITTIMEMAX_MASK (0xffff << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1097
1098/* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1099#define OMAP4430_SMPSWAITTIMEMIN_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1100#define OMAP4430_SMPSWAITTIMEMIN_MASK (0xffff << 8)
1101
1102/* Used by PRM_VC_ERRST */
1103#define OMAP4430_SMPS_RA_ERR_CORE_SHIFT 1
1104#define OMAP4430_SMPS_RA_ERR_CORE_MASK (1 << 1)
1105
1106/* Used by PRM_VC_ERRST */
1107#define OMAP4430_SMPS_RA_ERR_IVA_SHIFT 9
1108#define OMAP4430_SMPS_RA_ERR_IVA_MASK (1 << 9)
1109
1110/* Used by PRM_VC_ERRST */
1111#define OMAP4430_SMPS_RA_ERR_MPU_SHIFT 17
1112#define OMAP4430_SMPS_RA_ERR_MPU_MASK (1 << 17)
1113
1114/* Used by PRM_VC_ERRST */
1115#define OMAP4430_SMPS_SA_ERR_CORE_SHIFT 0
1116#define OMAP4430_SMPS_SA_ERR_CORE_MASK (1 << 0)
1117
1118/* Used by PRM_VC_ERRST */
1119#define OMAP4430_SMPS_SA_ERR_IVA_SHIFT 8
1120#define OMAP4430_SMPS_SA_ERR_IVA_MASK (1 << 8)
1121
1122/* Used by PRM_VC_ERRST */
1123#define OMAP4430_SMPS_SA_ERR_MPU_SHIFT 16
1124#define OMAP4430_SMPS_SA_ERR_MPU_MASK (1 << 16)
1125
1126/* Used by PRM_VC_ERRST */
1127#define OMAP4430_SMPS_TIMEOUT_ERR_CORE_SHIFT 2
1128#define OMAP4430_SMPS_TIMEOUT_ERR_CORE_MASK (1 << 2)
1129
1130/* Used by PRM_VC_ERRST */
1131#define OMAP4430_SMPS_TIMEOUT_ERR_IVA_SHIFT 10
1132#define OMAP4430_SMPS_TIMEOUT_ERR_IVA_MASK (1 << 10)
1133
1134/* Used by PRM_VC_ERRST */
1135#define OMAP4430_SMPS_TIMEOUT_ERR_MPU_SHIFT 18
1136#define OMAP4430_SMPS_TIMEOUT_ERR_MPU_MASK (1 << 18)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1137
1138/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1139#define OMAP4430_SR2EN_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1140#define OMAP4430_SR2EN_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1141
1142/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1143#define OMAP4430_SR2_IN_TRANSITION_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1144#define OMAP4430_SR2_IN_TRANSITION_MASK (1 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1145
1146/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1147#define OMAP4430_SR2_STATUS_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1148#define OMAP4430_SR2_STATUS_MASK (0x3 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1149
1150/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1151#define OMAP4430_SR2_WTCNT_VALUE_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1152#define OMAP4430_SR2_WTCNT_VALUE_MASK (0xff << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1153
1154/*
1155 * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL,
1156 * PRM_LDO_SRAM_MPU_CTRL
1157 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1158#define OMAP4430_SRAMLDO_STATUS_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1159#define OMAP4430_SRAMLDO_STATUS_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1160
1161/*
1162 * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL,
1163 * PRM_LDO_SRAM_MPU_CTRL
1164 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1165#define OMAP4430_SRAM_IN_TRANSITION_SHIFT 9
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1166#define OMAP4430_SRAM_IN_TRANSITION_MASK (1 << 9)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1167
1168/* Used by PRM_VC_CFG_I2C_MODE */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1169#define OMAP4430_SRMODEEN_SHIFT 4
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1170#define OMAP4430_SRMODEEN_MASK (1 << 4)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1171
1172/* Used by PRM_VOLTSETUP_WARMRESET */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1173#define OMAP4430_STABLE_COUNT_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1174#define OMAP4430_STABLE_COUNT_MASK (0x3f << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1175
1176/* Used by PRM_VOLTSETUP_WARMRESET */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1177#define OMAP4430_STABLE_PRESCAL_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1178#define OMAP4430_STABLE_PRESCAL_MASK (0x3 << 8)
1179
1180/* Used by PRM_LDO_BANDGAP_SETUP */
1181#define OMAP4430_STARTUP_COUNT_SHIFT 0
1182#define OMAP4430_STARTUP_COUNT_MASK (0xff << 0)
1183
1184/* Renamed from STARTUP_COUNT Used by PRM_SRAM_COUNT */
1185#define OMAP4430_STARTUP_COUNT_24_31_SHIFT 24
1186#define OMAP4430_STARTUP_COUNT_24_31_MASK (0xff << 24)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1187
1188/* Used by PM_IVAHD_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1189#define OMAP4430_TCM1_MEM_ONSTATE_SHIFT 20
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1190#define OMAP4430_TCM1_MEM_ONSTATE_MASK (0x3 << 20)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1191
1192/* Used by PM_IVAHD_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1193#define OMAP4430_TCM1_MEM_RETSTATE_SHIFT 10
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1194#define OMAP4430_TCM1_MEM_RETSTATE_MASK (1 << 10)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1195
1196/* Used by PM_IVAHD_PWRSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1197#define OMAP4430_TCM1_MEM_STATEST_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1198#define OMAP4430_TCM1_MEM_STATEST_MASK (0x3 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1199
1200/* Used by PM_IVAHD_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1201#define OMAP4430_TCM2_MEM_ONSTATE_SHIFT 22
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1202#define OMAP4430_TCM2_MEM_ONSTATE_MASK (0x3 << 22)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1203
1204/* Used by PM_IVAHD_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1205#define OMAP4430_TCM2_MEM_RETSTATE_SHIFT 11
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1206#define OMAP4430_TCM2_MEM_RETSTATE_MASK (1 << 11)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1207
1208/* Used by PM_IVAHD_PWRSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1209#define OMAP4430_TCM2_MEM_STATEST_SHIFT 10
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1210#define OMAP4430_TCM2_MEM_STATEST_MASK (0x3 << 10)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1211
1212/* Used by RM_TESLA_RSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1213#define OMAP4430_TESLASS_EMU_RSTST_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1214#define OMAP4430_TESLASS_EMU_RSTST_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1215
1216/* Used by RM_TESLA_RSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1217#define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1218#define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1219
1220/* Used by PM_TESLA_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1221#define OMAP4430_TESLA_EDMA_ONSTATE_SHIFT 20
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1222#define OMAP4430_TESLA_EDMA_ONSTATE_MASK (0x3 << 20)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1223
1224/* Used by PM_TESLA_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1225#define OMAP4430_TESLA_EDMA_RETSTATE_SHIFT 10
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1226#define OMAP4430_TESLA_EDMA_RETSTATE_MASK (1 << 10)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1227
1228/* Used by PM_TESLA_PWRSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1229#define OMAP4430_TESLA_EDMA_STATEST_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1230#define OMAP4430_TESLA_EDMA_STATEST_MASK (0x3 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1231
1232/* Used by PM_TESLA_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1233#define OMAP4430_TESLA_L1_ONSTATE_SHIFT 16
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1234#define OMAP4430_TESLA_L1_ONSTATE_MASK (0x3 << 16)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1235
1236/* Used by PM_TESLA_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1237#define OMAP4430_TESLA_L1_RETSTATE_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1238#define OMAP4430_TESLA_L1_RETSTATE_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1239
1240/* Used by PM_TESLA_PWRSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1241#define OMAP4430_TESLA_L1_STATEST_SHIFT 4
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1242#define OMAP4430_TESLA_L1_STATEST_MASK (0x3 << 4)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1243
1244/* Used by PM_TESLA_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1245#define OMAP4430_TESLA_L2_ONSTATE_SHIFT 18
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1246#define OMAP4430_TESLA_L2_ONSTATE_MASK (0x3 << 18)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1247
1248/* Used by PM_TESLA_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1249#define OMAP4430_TESLA_L2_RETSTATE_SHIFT 9
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1250#define OMAP4430_TESLA_L2_RETSTATE_MASK (1 << 9)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1251
1252/* Used by PM_TESLA_PWRSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1253#define OMAP4430_TESLA_L2_STATEST_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1254#define OMAP4430_TESLA_L2_STATEST_MASK (0x3 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1255
1256/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1257#define OMAP4430_TIMEOUT_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1258#define OMAP4430_TIMEOUT_MASK (0xffff << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1259
1260/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1261#define OMAP4430_TIMEOUTEN_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1262#define OMAP4430_TIMEOUTEN_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1263
1264/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1265#define OMAP4430_TRANSITION_EN_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1266#define OMAP4430_TRANSITION_EN_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1267
1268/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1269#define OMAP4430_TRANSITION_ST_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1270#define OMAP4430_TRANSITION_ST_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1271
1272/* Used by PRM_VC_VAL_BYPASS */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1273#define OMAP4430_VALID_SHIFT 24
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1274#define OMAP4430_VALID_MASK (1 << 24)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1275
1276/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1277#define OMAP4430_VC_BYPASSACK_EN_SHIFT 14
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1278#define OMAP4430_VC_BYPASSACK_EN_MASK (1 << 14)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1279
1280/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1281#define OMAP4430_VC_BYPASSACK_ST_SHIFT 14
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1282#define OMAP4430_VC_BYPASSACK_ST_MASK (1 << 14)
1283
1284/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
1285#define OMAP4430_VC_CORE_VPACK_EN_SHIFT 22
1286#define OMAP4430_VC_CORE_VPACK_EN_MASK (1 << 22)
1287
1288/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
1289#define OMAP4430_VC_CORE_VPACK_ST_SHIFT 22
1290#define OMAP4430_VC_CORE_VPACK_ST_MASK (1 << 22)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1291
1292/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1293#define OMAP4430_VC_IVA_VPACK_EN_SHIFT 30
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1294#define OMAP4430_VC_IVA_VPACK_EN_MASK (1 << 30)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1295
1296/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1297#define OMAP4430_VC_IVA_VPACK_ST_SHIFT 30
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1298#define OMAP4430_VC_IVA_VPACK_ST_MASK (1 << 30)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1299
1300/* Used by PRM_IRQENABLE_MPU_2 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1301#define OMAP4430_VC_MPU_VPACK_EN_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1302#define OMAP4430_VC_MPU_VPACK_EN_MASK (1 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1303
1304/* Used by PRM_IRQSTATUS_MPU_2 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1305#define OMAP4430_VC_MPU_VPACK_ST_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1306#define OMAP4430_VC_MPU_VPACK_ST_MASK (1 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1307
1308/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1309#define OMAP4430_VC_RAERR_EN_SHIFT 12
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1310#define OMAP4430_VC_RAERR_EN_MASK (1 << 12)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1311
1312/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1313#define OMAP4430_VC_RAERR_ST_SHIFT 12
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1314#define OMAP4430_VC_RAERR_ST_MASK (1 << 12)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1315
1316/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1317#define OMAP4430_VC_SAERR_EN_SHIFT 11
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1318#define OMAP4430_VC_SAERR_EN_MASK (1 << 11)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1319
1320/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1321#define OMAP4430_VC_SAERR_ST_SHIFT 11
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1322#define OMAP4430_VC_SAERR_ST_MASK (1 << 11)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1323
1324/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1325#define OMAP4430_VC_TOERR_EN_SHIFT 13
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1326#define OMAP4430_VC_TOERR_EN_MASK (1 << 13)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1327
1328/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1329#define OMAP4430_VC_TOERR_ST_SHIFT 13
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1330#define OMAP4430_VC_TOERR_ST_MASK (1 << 13)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1331
1332/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1333#define OMAP4430_VDDMAX_SHIFT 24
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1334#define OMAP4430_VDDMAX_MASK (0xff << 24)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1335
1336/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1337#define OMAP4430_VDDMIN_SHIFT 16
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1338#define OMAP4430_VDDMIN_MASK (0xff << 16)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1339
1340/* Used by PRM_VOLTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1341#define OMAP4430_VDD_CORE_I2C_DISABLE_SHIFT 12
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1342#define OMAP4430_VDD_CORE_I2C_DISABLE_MASK (1 << 12)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1343
1344/* Used by PRM_RSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1345#define OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1346#define OMAP4430_VDD_CORE_VOLT_MGR_RST_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1347
1348/* Used by PRM_VOLTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1349#define OMAP4430_VDD_IVA_I2C_DISABLE_SHIFT 14
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1350#define OMAP4430_VDD_IVA_I2C_DISABLE_MASK (1 << 14)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1351
1352/* Used by PRM_VOLTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1353#define OMAP4430_VDD_IVA_PRESENCE_SHIFT 9
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1354#define OMAP4430_VDD_IVA_PRESENCE_MASK (1 << 9)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1355
1356/* Used by PRM_RSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1357#define OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT 7
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1358#define OMAP4430_VDD_IVA_VOLT_MGR_RST_MASK (1 << 7)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1359
1360/* Used by PRM_VOLTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1361#define OMAP4430_VDD_MPU_I2C_DISABLE_SHIFT 13
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1362#define OMAP4430_VDD_MPU_I2C_DISABLE_MASK (1 << 13)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1363
1364/* Used by PRM_VOLTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1365#define OMAP4430_VDD_MPU_PRESENCE_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1366#define OMAP4430_VDD_MPU_PRESENCE_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1367
1368/* Used by PRM_RSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1369#define OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1370#define OMAP4430_VDD_MPU_VOLT_MGR_RST_MASK (1 << 6)
1371
1372/* Used by PRM_VC_ERRST */
1373#define OMAP4430_VFSM_RA_ERR_CORE_SHIFT 4
1374#define OMAP4430_VFSM_RA_ERR_CORE_MASK (1 << 4)
1375
1376/* Used by PRM_VC_ERRST */
1377#define OMAP4430_VFSM_RA_ERR_IVA_SHIFT 12
1378#define OMAP4430_VFSM_RA_ERR_IVA_MASK (1 << 12)
1379
1380/* Used by PRM_VC_ERRST */
1381#define OMAP4430_VFSM_RA_ERR_MPU_SHIFT 20
1382#define OMAP4430_VFSM_RA_ERR_MPU_MASK (1 << 20)
1383
1384/* Used by PRM_VC_ERRST */
1385#define OMAP4430_VFSM_SA_ERR_CORE_SHIFT 3
1386#define OMAP4430_VFSM_SA_ERR_CORE_MASK (1 << 3)
1387
1388/* Used by PRM_VC_ERRST */
1389#define OMAP4430_VFSM_SA_ERR_IVA_SHIFT 11
1390#define OMAP4430_VFSM_SA_ERR_IVA_MASK (1 << 11)
1391
1392/* Used by PRM_VC_ERRST */
1393#define OMAP4430_VFSM_SA_ERR_MPU_SHIFT 19
1394#define OMAP4430_VFSM_SA_ERR_MPU_MASK (1 << 19)
1395
1396/* Used by PRM_VC_ERRST */
1397#define OMAP4430_VFSM_TIMEOUT_ERR_CORE_SHIFT 5
1398#define OMAP4430_VFSM_TIMEOUT_ERR_CORE_MASK (1 << 5)
1399
1400/* Used by PRM_VC_ERRST */
1401#define OMAP4430_VFSM_TIMEOUT_ERR_IVA_SHIFT 13
1402#define OMAP4430_VFSM_TIMEOUT_ERR_IVA_MASK (1 << 13)
1403
1404/* Used by PRM_VC_ERRST */
1405#define OMAP4430_VFSM_TIMEOUT_ERR_MPU_SHIFT 21
1406#define OMAP4430_VFSM_TIMEOUT_ERR_MPU_MASK (1 << 21)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1407
1408/* Used by PRM_VC_VAL_SMPS_RA_VOL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1409#define OMAP4430_VOLRA_VDD_CORE_L_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1410#define OMAP4430_VOLRA_VDD_CORE_L_MASK (0xff << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1411
1412/* Used by PRM_VC_VAL_SMPS_RA_VOL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1413#define OMAP4430_VOLRA_VDD_IVA_L_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1414#define OMAP4430_VOLRA_VDD_IVA_L_MASK (0xff << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1415
1416/* Used by PRM_VC_VAL_SMPS_RA_VOL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1417#define OMAP4430_VOLRA_VDD_MPU_L_SHIFT 16
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1418#define OMAP4430_VOLRA_VDD_MPU_L_MASK (0xff << 16)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1419
1420/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1421#define OMAP4430_VPENABLE_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1422#define OMAP4430_VPENABLE_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1423
1424/* Used by PRM_VP_CORE_STATUS, PRM_VP_IVA_STATUS, PRM_VP_MPU_STATUS */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1425#define OMAP4430_VPINIDLE_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1426#define OMAP4430_VPINIDLE_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1427
1428/* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1429#define OMAP4430_VPVOLTAGE_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1430#define OMAP4430_VPVOLTAGE_MASK (0xff << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1431
1432/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1433#define OMAP4430_VP_CORE_EQVALUE_EN_SHIFT 20
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1434#define OMAP4430_VP_CORE_EQVALUE_EN_MASK (1 << 20)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1435
1436/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1437#define OMAP4430_VP_CORE_EQVALUE_ST_SHIFT 20
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1438#define OMAP4430_VP_CORE_EQVALUE_ST_MASK (1 << 20)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1439
1440/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1441#define OMAP4430_VP_CORE_MAXVDD_EN_SHIFT 18
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1442#define OMAP4430_VP_CORE_MAXVDD_EN_MASK (1 << 18)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1443
1444/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1445#define OMAP4430_VP_CORE_MAXVDD_ST_SHIFT 18
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1446#define OMAP4430_VP_CORE_MAXVDD_ST_MASK (1 << 18)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1447
1448/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1449#define OMAP4430_VP_CORE_MINVDD_EN_SHIFT 17
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1450#define OMAP4430_VP_CORE_MINVDD_EN_MASK (1 << 17)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1451
1452/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1453#define OMAP4430_VP_CORE_MINVDD_ST_SHIFT 17
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1454#define OMAP4430_VP_CORE_MINVDD_ST_MASK (1 << 17)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1455
1456/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1457#define OMAP4430_VP_CORE_NOSMPSACK_EN_SHIFT 19
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1458#define OMAP4430_VP_CORE_NOSMPSACK_EN_MASK (1 << 19)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1459
1460/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1461#define OMAP4430_VP_CORE_NOSMPSACK_ST_SHIFT 19
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1462#define OMAP4430_VP_CORE_NOSMPSACK_ST_MASK (1 << 19)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1463
1464/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1465#define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_SHIFT 16
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1466#define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_MASK (1 << 16)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1467
1468/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1469#define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_SHIFT 16
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1470#define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_MASK (1 << 16)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1471
1472/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1473#define OMAP4430_VP_CORE_TRANXDONE_EN_SHIFT 21
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1474#define OMAP4430_VP_CORE_TRANXDONE_EN_MASK (1 << 21)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1475
1476/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1477#define OMAP4430_VP_CORE_TRANXDONE_ST_SHIFT 21
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1478#define OMAP4430_VP_CORE_TRANXDONE_ST_MASK (1 << 21)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1479
1480/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1481#define OMAP4430_VP_IVA_EQVALUE_EN_SHIFT 28
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1482#define OMAP4430_VP_IVA_EQVALUE_EN_MASK (1 << 28)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1483
1484/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1485#define OMAP4430_VP_IVA_EQVALUE_ST_SHIFT 28
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1486#define OMAP4430_VP_IVA_EQVALUE_ST_MASK (1 << 28)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1487
1488/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1489#define OMAP4430_VP_IVA_MAXVDD_EN_SHIFT 26
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1490#define OMAP4430_VP_IVA_MAXVDD_EN_MASK (1 << 26)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1491
1492/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1493#define OMAP4430_VP_IVA_MAXVDD_ST_SHIFT 26
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1494#define OMAP4430_VP_IVA_MAXVDD_ST_MASK (1 << 26)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1495
1496/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1497#define OMAP4430_VP_IVA_MINVDD_EN_SHIFT 25
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1498#define OMAP4430_VP_IVA_MINVDD_EN_MASK (1 << 25)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1499
1500/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1501#define OMAP4430_VP_IVA_MINVDD_ST_SHIFT 25
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1502#define OMAP4430_VP_IVA_MINVDD_ST_MASK (1 << 25)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1503
1504/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1505#define OMAP4430_VP_IVA_NOSMPSACK_EN_SHIFT 27
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1506#define OMAP4430_VP_IVA_NOSMPSACK_EN_MASK (1 << 27)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1507
1508/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1509#define OMAP4430_VP_IVA_NOSMPSACK_ST_SHIFT 27
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1510#define OMAP4430_VP_IVA_NOSMPSACK_ST_MASK (1 << 27)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1511
1512/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1513#define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_SHIFT 24
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1514#define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_MASK (1 << 24)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1515
1516/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1517#define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_SHIFT 24
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1518#define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_MASK (1 << 24)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1519
1520/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1521#define OMAP4430_VP_IVA_TRANXDONE_EN_SHIFT 29
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1522#define OMAP4430_VP_IVA_TRANXDONE_EN_MASK (1 << 29)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1523
1524/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1525#define OMAP4430_VP_IVA_TRANXDONE_ST_SHIFT 29
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1526#define OMAP4430_VP_IVA_TRANXDONE_ST_MASK (1 << 29)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1527
1528/* Used by PRM_IRQENABLE_MPU_2 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1529#define OMAP4430_VP_MPU_EQVALUE_EN_SHIFT 4
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1530#define OMAP4430_VP_MPU_EQVALUE_EN_MASK (1 << 4)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1531
1532/* Used by PRM_IRQSTATUS_MPU_2 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1533#define OMAP4430_VP_MPU_EQVALUE_ST_SHIFT 4
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1534#define OMAP4430_VP_MPU_EQVALUE_ST_MASK (1 << 4)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1535
1536/* Used by PRM_IRQENABLE_MPU_2 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1537#define OMAP4430_VP_MPU_MAXVDD_EN_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1538#define OMAP4430_VP_MPU_MAXVDD_EN_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1539
1540/* Used by PRM_IRQSTATUS_MPU_2 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1541#define OMAP4430_VP_MPU_MAXVDD_ST_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1542#define OMAP4430_VP_MPU_MAXVDD_ST_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1543
1544/* Used by PRM_IRQENABLE_MPU_2 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1545#define OMAP4430_VP_MPU_MINVDD_EN_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1546#define OMAP4430_VP_MPU_MINVDD_EN_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1547
1548/* Used by PRM_IRQSTATUS_MPU_2 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1549#define OMAP4430_VP_MPU_MINVDD_ST_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1550#define OMAP4430_VP_MPU_MINVDD_ST_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1551
1552/* Used by PRM_IRQENABLE_MPU_2 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1553#define OMAP4430_VP_MPU_NOSMPSACK_EN_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1554#define OMAP4430_VP_MPU_NOSMPSACK_EN_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1555
1556/* Used by PRM_IRQSTATUS_MPU_2 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1557#define OMAP4430_VP_MPU_NOSMPSACK_ST_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1558#define OMAP4430_VP_MPU_NOSMPSACK_ST_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1559
1560/* Used by PRM_IRQENABLE_MPU_2 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1561#define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1562#define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1563
1564/* Used by PRM_IRQSTATUS_MPU_2 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1565#define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1566#define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1567
1568/* Used by PRM_IRQENABLE_MPU_2 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1569#define OMAP4430_VP_MPU_TRANXDONE_EN_SHIFT 5
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1570#define OMAP4430_VP_MPU_TRANXDONE_EN_MASK (1 << 5)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1571
1572/* Used by PRM_IRQSTATUS_MPU_2 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1573#define OMAP4430_VP_MPU_TRANXDONE_ST_SHIFT 5
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1574#define OMAP4430_VP_MPU_TRANXDONE_ST_MASK (1 << 5)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1575
1576/* Used by PRM_SRAM_COUNT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1577#define OMAP4430_VSETUPCNT_VALUE_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1578#define OMAP4430_VSETUPCNT_VALUE_MASK (0xff << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1579
1580/* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1581#define OMAP4430_VSTEPMAX_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1582#define OMAP4430_VSTEPMAX_MASK (0xff << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1583
1584/* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1585#define OMAP4430_VSTEPMIN_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1586#define OMAP4430_VSTEPMIN_MASK (0xff << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1587
1588/* Used by PRM_MODEM_IF_CTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1589#define OMAP4430_WAKE_MODEM_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1590#define OMAP4430_WAKE_MODEM_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1591
1592/* Used by PM_DSS_DSS_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1593#define OMAP4430_WKUPDEP_DISPC_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1594#define OMAP4430_WKUPDEP_DISPC_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1595
1596/* Used by PM_DSS_DSS_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1597#define OMAP4430_WKUPDEP_DISPC_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1598#define OMAP4430_WKUPDEP_DISPC_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1599
1600/* Used by PM_DSS_DSS_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1601#define OMAP4430_WKUPDEP_DISPC_SDMA_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1602#define OMAP4430_WKUPDEP_DISPC_SDMA_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1603
1604/* Used by PM_DSS_DSS_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1605#define OMAP4430_WKUPDEP_DISPC_TESLA_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1606#define OMAP4430_WKUPDEP_DISPC_TESLA_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1607
1608/* Used by PM_ABE_DMIC_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1609#define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_SHIFT 7
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1610#define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_MASK (1 << 7)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1611
1612/* Used by PM_ABE_DMIC_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1613#define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1614#define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_MASK (1 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1615
1616/* Used by PM_ABE_DMIC_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1617#define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1618#define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1619
1620/* Used by PM_ABE_DMIC_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1621#define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1622#define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1623
1624/* Used by PM_L4PER_DMTIMER10_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1625#define OMAP4430_WKUPDEP_DMTIMER10_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1626#define OMAP4430_WKUPDEP_DMTIMER10_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1627
1628/* Used by PM_L4PER_DMTIMER11_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1629#define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1630#define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1631
1632/* Used by PM_L4PER_DMTIMER11_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1633#define OMAP4430_WKUPDEP_DMTIMER11_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1634#define OMAP4430_WKUPDEP_DMTIMER11_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1635
1636/* Used by PM_L4PER_DMTIMER2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1637#define OMAP4430_WKUPDEP_DMTIMER2_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1638#define OMAP4430_WKUPDEP_DMTIMER2_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1639
1640/* Used by PM_L4PER_DMTIMER3_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1641#define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1642#define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1643
1644/* Used by PM_L4PER_DMTIMER3_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1645#define OMAP4430_WKUPDEP_DMTIMER3_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1646#define OMAP4430_WKUPDEP_DMTIMER3_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1647
1648/* Used by PM_L4PER_DMTIMER4_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1649#define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1650#define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1651
1652/* Used by PM_L4PER_DMTIMER4_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1653#define OMAP4430_WKUPDEP_DMTIMER4_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1654#define OMAP4430_WKUPDEP_DMTIMER4_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1655
1656/* Used by PM_L4PER_DMTIMER9_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1657#define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1658#define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1659
1660/* Used by PM_L4PER_DMTIMER9_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1661#define OMAP4430_WKUPDEP_DMTIMER9_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1662#define OMAP4430_WKUPDEP_DMTIMER9_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1663
1664/* Used by PM_DSS_DSS_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1665#define OMAP4430_WKUPDEP_DSI1_DUCATI_SHIFT 5
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1666#define OMAP4430_WKUPDEP_DSI1_DUCATI_MASK (1 << 5)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1667
1668/* Used by PM_DSS_DSS_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1669#define OMAP4430_WKUPDEP_DSI1_MPU_SHIFT 4
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1670#define OMAP4430_WKUPDEP_DSI1_MPU_MASK (1 << 4)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1671
1672/* Used by PM_DSS_DSS_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1673#define OMAP4430_WKUPDEP_DSI1_SDMA_SHIFT 7
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1674#define OMAP4430_WKUPDEP_DSI1_SDMA_MASK (1 << 7)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1675
1676/* Used by PM_DSS_DSS_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1677#define OMAP4430_WKUPDEP_DSI1_TESLA_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1678#define OMAP4430_WKUPDEP_DSI1_TESLA_MASK (1 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1679
1680/* Used by PM_DSS_DSS_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1681#define OMAP4430_WKUPDEP_DSI2_DUCATI_SHIFT 9
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1682#define OMAP4430_WKUPDEP_DSI2_DUCATI_MASK (1 << 9)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1683
1684/* Used by PM_DSS_DSS_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1685#define OMAP4430_WKUPDEP_DSI2_MPU_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1686#define OMAP4430_WKUPDEP_DSI2_MPU_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1687
1688/* Used by PM_DSS_DSS_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1689#define OMAP4430_WKUPDEP_DSI2_SDMA_SHIFT 11
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1690#define OMAP4430_WKUPDEP_DSI2_SDMA_MASK (1 << 11)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1691
1692/* Used by PM_DSS_DSS_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1693#define OMAP4430_WKUPDEP_DSI2_TESLA_SHIFT 10
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1694#define OMAP4430_WKUPDEP_DSI2_TESLA_MASK (1 << 10)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1695
1696/* Used by PM_WKUP_GPIO1_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1697#define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1698#define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1699
1700/* Used by PM_WKUP_GPIO1_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1701#define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1702#define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1703
1704/* Used by PM_WKUP_GPIO1_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1705#define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1706#define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_MASK (1 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1707
1708/* Used by PM_L4PER_GPIO2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1709#define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1710#define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1711
1712/* Used by PM_L4PER_GPIO2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1713#define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1714#define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1715
1716/* Used by PM_L4PER_GPIO2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1717#define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1718#define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_MASK (1 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1719
1720/* Used by PM_L4PER_GPIO3_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1721#define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1722#define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1723
1724/* Used by PM_L4PER_GPIO3_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1725#define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1726#define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_MASK (1 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1727
1728/* Used by PM_L4PER_GPIO4_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1729#define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1730#define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1731
1732/* Used by PM_L4PER_GPIO4_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1733#define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1734#define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_MASK (1 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1735
1736/* Used by PM_L4PER_GPIO5_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1737#define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1738#define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1739
1740/* Used by PM_L4PER_GPIO5_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1741#define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1742#define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_MASK (1 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1743
1744/* Used by PM_L4PER_GPIO6_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1745#define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1746#define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1747
1748/* Used by PM_L4PER_GPIO6_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1749#define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1750#define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_MASK (1 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1751
1752/* Used by PM_DSS_DSS_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1753#define OMAP4430_WKUPDEP_HDMIDMA_SDMA_SHIFT 19
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1754#define OMAP4430_WKUPDEP_HDMIDMA_SDMA_MASK (1 << 19)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1755
1756/* Used by PM_DSS_DSS_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1757#define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_SHIFT 13
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1758#define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_MASK (1 << 13)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1759
1760/* Used by PM_DSS_DSS_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1761#define OMAP4430_WKUPDEP_HDMIIRQ_MPU_SHIFT 12
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1762#define OMAP4430_WKUPDEP_HDMIIRQ_MPU_MASK (1 << 12)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1763
1764/* Used by PM_DSS_DSS_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1765#define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_SHIFT 14
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1766#define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_MASK (1 << 14)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1767
1768/* Used by PM_L4PER_HECC1_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1769#define OMAP4430_WKUPDEP_HECC1_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1770#define OMAP4430_WKUPDEP_HECC1_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1771
1772/* Used by PM_L4PER_HECC2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1773#define OMAP4430_WKUPDEP_HECC2_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1774#define OMAP4430_WKUPDEP_HECC2_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1775
1776/* Used by PM_L3INIT_HSI_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1777#define OMAP4430_WKUPDEP_HSI_DSP_TESLA_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1778#define OMAP4430_WKUPDEP_HSI_DSP_TESLA_MASK (1 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1779
1780/* Used by PM_L3INIT_HSI_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1781#define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1782#define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1783
1784/* Used by PM_L3INIT_HSI_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1785#define OMAP4430_WKUPDEP_HSI_MCU_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1786#define OMAP4430_WKUPDEP_HSI_MCU_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1787
1788/* Used by PM_L4PER_I2C1_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1789#define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_SHIFT 7
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1790#define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_MASK (1 << 7)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1791
1792/* Used by PM_L4PER_I2C1_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1793#define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1794#define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1795
1796/* Used by PM_L4PER_I2C1_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1797#define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1798#define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1799
1800/* Used by PM_L4PER_I2C2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1801#define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_SHIFT 7
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1802#define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_MASK (1 << 7)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1803
1804/* Used by PM_L4PER_I2C2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1805#define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1806#define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1807
1808/* Used by PM_L4PER_I2C2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1809#define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1810#define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1811
1812/* Used by PM_L4PER_I2C3_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1813#define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_SHIFT 7
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1814#define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_MASK (1 << 7)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1815
1816/* Used by PM_L4PER_I2C3_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1817#define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1818#define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1819
1820/* Used by PM_L4PER_I2C3_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1821#define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1822#define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1823
1824/* Used by PM_L4PER_I2C4_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1825#define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_SHIFT 7
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1826#define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_MASK (1 << 7)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1827
1828/* Used by PM_L4PER_I2C4_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1829#define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1830#define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1831
1832/* Used by PM_L4PER_I2C4_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1833#define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1834#define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1835
1836/* Used by PM_L4PER_I2C5_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1837#define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_SHIFT 7
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1838#define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_MASK (1 << 7)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1839
1840/* Used by PM_L4PER_I2C5_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1841#define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1842#define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1843
1844/* Used by PM_WKUP_KEYBOARD_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1845#define OMAP4430_WKUPDEP_KEYBOARD_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1846#define OMAP4430_WKUPDEP_KEYBOARD_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1847
1848/* Used by PM_ABE_MCASP_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1849#define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_SHIFT 7
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1850#define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_MASK (1 << 7)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1851
1852/* Used by PM_ABE_MCASP_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1853#define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1854#define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_MASK (1 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1855
1856/* Used by PM_ABE_MCASP_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1857#define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1858#define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1859
1860/* Used by PM_ABE_MCASP_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1861#define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1862#define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1863
1864/* Used by PM_L4PER_MCASP2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1865#define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_SHIFT 7
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1866#define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_MASK (1 << 7)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1867
1868/* Used by PM_L4PER_MCASP2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1869#define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1870#define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_MASK (1 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1871
1872/* Used by PM_L4PER_MCASP2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1873#define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1874#define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1875
1876/* Used by PM_L4PER_MCASP2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1877#define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1878#define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1879
1880/* Used by PM_L4PER_MCASP3_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1881#define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_SHIFT 7
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1882#define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_MASK (1 << 7)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1883
1884/* Used by PM_L4PER_MCASP3_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1885#define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1886#define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_MASK (1 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1887
1888/* Used by PM_L4PER_MCASP3_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1889#define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1890#define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1891
1892/* Used by PM_L4PER_MCASP3_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1893#define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1894#define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1895
1896/* Used by PM_ABE_MCBSP1_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1897#define OMAP4430_WKUPDEP_MCBSP1_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1898#define OMAP4430_WKUPDEP_MCBSP1_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1899
1900/* Used by PM_ABE_MCBSP1_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1901#define OMAP4430_WKUPDEP_MCBSP1_SDMA_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1902#define OMAP4430_WKUPDEP_MCBSP1_SDMA_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1903
1904/* Used by PM_ABE_MCBSP1_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1905#define OMAP4430_WKUPDEP_MCBSP1_TESLA_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1906#define OMAP4430_WKUPDEP_MCBSP1_TESLA_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1907
1908/* Used by PM_ABE_MCBSP2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1909#define OMAP4430_WKUPDEP_MCBSP2_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1910#define OMAP4430_WKUPDEP_MCBSP2_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1911
1912/* Used by PM_ABE_MCBSP2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1913#define OMAP4430_WKUPDEP_MCBSP2_SDMA_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1914#define OMAP4430_WKUPDEP_MCBSP2_SDMA_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1915
1916/* Used by PM_ABE_MCBSP2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1917#define OMAP4430_WKUPDEP_MCBSP2_TESLA_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1918#define OMAP4430_WKUPDEP_MCBSP2_TESLA_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1919
1920/* Used by PM_ABE_MCBSP3_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1921#define OMAP4430_WKUPDEP_MCBSP3_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1922#define OMAP4430_WKUPDEP_MCBSP3_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1923
1924/* Used by PM_ABE_MCBSP3_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1925#define OMAP4430_WKUPDEP_MCBSP3_SDMA_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1926#define OMAP4430_WKUPDEP_MCBSP3_SDMA_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1927
1928/* Used by PM_ABE_MCBSP3_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1929#define OMAP4430_WKUPDEP_MCBSP3_TESLA_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1930#define OMAP4430_WKUPDEP_MCBSP3_TESLA_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1931
1932/* Used by PM_L4PER_MCBSP4_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1933#define OMAP4430_WKUPDEP_MCBSP4_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1934#define OMAP4430_WKUPDEP_MCBSP4_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1935
1936/* Used by PM_L4PER_MCBSP4_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1937#define OMAP4430_WKUPDEP_MCBSP4_SDMA_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1938#define OMAP4430_WKUPDEP_MCBSP4_SDMA_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1939
1940/* Used by PM_L4PER_MCBSP4_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1941#define OMAP4430_WKUPDEP_MCBSP4_TESLA_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1942#define OMAP4430_WKUPDEP_MCBSP4_TESLA_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1943
1944/* Used by PM_L4PER_MCSPI1_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1945#define OMAP4430_WKUPDEP_MCSPI1_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1946#define OMAP4430_WKUPDEP_MCSPI1_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1947
1948/* Used by PM_L4PER_MCSPI1_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1949#define OMAP4430_WKUPDEP_MCSPI1_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1950#define OMAP4430_WKUPDEP_MCSPI1_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1951
1952/* Used by PM_L4PER_MCSPI1_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1953#define OMAP4430_WKUPDEP_MCSPI1_SDMA_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1954#define OMAP4430_WKUPDEP_MCSPI1_SDMA_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1955
1956/* Used by PM_L4PER_MCSPI1_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1957#define OMAP4430_WKUPDEP_MCSPI1_TESLA_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1958#define OMAP4430_WKUPDEP_MCSPI1_TESLA_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1959
1960/* Used by PM_L4PER_MCSPI2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1961#define OMAP4430_WKUPDEP_MCSPI2_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1962#define OMAP4430_WKUPDEP_MCSPI2_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1963
1964/* Used by PM_L4PER_MCSPI2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1965#define OMAP4430_WKUPDEP_MCSPI2_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1966#define OMAP4430_WKUPDEP_MCSPI2_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1967
1968/* Used by PM_L4PER_MCSPI2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1969#define OMAP4430_WKUPDEP_MCSPI2_SDMA_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1970#define OMAP4430_WKUPDEP_MCSPI2_SDMA_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1971
1972/* Used by PM_L4PER_MCSPI3_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1973#define OMAP4430_WKUPDEP_MCSPI3_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1974#define OMAP4430_WKUPDEP_MCSPI3_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1975
1976/* Used by PM_L4PER_MCSPI3_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1977#define OMAP4430_WKUPDEP_MCSPI3_SDMA_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1978#define OMAP4430_WKUPDEP_MCSPI3_SDMA_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1979
1980/* Used by PM_L4PER_MCSPI4_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1981#define OMAP4430_WKUPDEP_MCSPI4_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1982#define OMAP4430_WKUPDEP_MCSPI4_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1983
1984/* Used by PM_L4PER_MCSPI4_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1985#define OMAP4430_WKUPDEP_MCSPI4_SDMA_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1986#define OMAP4430_WKUPDEP_MCSPI4_SDMA_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1987
1988/* Used by PM_L3INIT_MMC1_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1989#define OMAP4430_WKUPDEP_MMC1_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1990#define OMAP4430_WKUPDEP_MMC1_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1991
1992/* Used by PM_L3INIT_MMC1_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1993#define OMAP4430_WKUPDEP_MMC1_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1994#define OMAP4430_WKUPDEP_MMC1_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1995
1996/* Used by PM_L3INIT_MMC1_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]1997#define OMAP4430_WKUPDEP_MMC1_SDMA_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]1998#define OMAP4430_WKUPDEP_MMC1_SDMA_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]1999
2000/* Used by PM_L3INIT_MMC1_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2001#define OMAP4430_WKUPDEP_MMC1_TESLA_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2002#define OMAP4430_WKUPDEP_MMC1_TESLA_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2003
2004/* Used by PM_L3INIT_MMC2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2005#define OMAP4430_WKUPDEP_MMC2_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2006#define OMAP4430_WKUPDEP_MMC2_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2007
2008/* Used by PM_L3INIT_MMC2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2009#define OMAP4430_WKUPDEP_MMC2_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2010#define OMAP4430_WKUPDEP_MMC2_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2011
2012/* Used by PM_L3INIT_MMC2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2013#define OMAP4430_WKUPDEP_MMC2_SDMA_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2014#define OMAP4430_WKUPDEP_MMC2_SDMA_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2015
2016/* Used by PM_L3INIT_MMC2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2017#define OMAP4430_WKUPDEP_MMC2_TESLA_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2018#define OMAP4430_WKUPDEP_MMC2_TESLA_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2019
2020/* Used by PM_L3INIT_MMC6_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2021#define OMAP4430_WKUPDEP_MMC6_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2022#define OMAP4430_WKUPDEP_MMC6_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2023
2024/* Used by PM_L3INIT_MMC6_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2025#define OMAP4430_WKUPDEP_MMC6_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2026#define OMAP4430_WKUPDEP_MMC6_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2027
2028/* Used by PM_L3INIT_MMC6_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2029#define OMAP4430_WKUPDEP_MMC6_TESLA_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2030#define OMAP4430_WKUPDEP_MMC6_TESLA_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2031
2032/* Used by PM_L4PER_MMCSD3_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2033#define OMAP4430_WKUPDEP_MMCSD3_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2034#define OMAP4430_WKUPDEP_MMCSD3_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2035
2036/* Used by PM_L4PER_MMCSD3_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2037#define OMAP4430_WKUPDEP_MMCSD3_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2038#define OMAP4430_WKUPDEP_MMCSD3_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2039
2040/* Used by PM_L4PER_MMCSD3_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2041#define OMAP4430_WKUPDEP_MMCSD3_SDMA_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2042#define OMAP4430_WKUPDEP_MMCSD3_SDMA_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2043
2044/* Used by PM_L4PER_MMCSD4_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2045#define OMAP4430_WKUPDEP_MMCSD4_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2046#define OMAP4430_WKUPDEP_MMCSD4_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2047
2048/* Used by PM_L4PER_MMCSD4_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2049#define OMAP4430_WKUPDEP_MMCSD4_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2050#define OMAP4430_WKUPDEP_MMCSD4_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2051
2052/* Used by PM_L4PER_MMCSD4_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2053#define OMAP4430_WKUPDEP_MMCSD4_SDMA_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2054#define OMAP4430_WKUPDEP_MMCSD4_SDMA_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2055
2056/* Used by PM_L4PER_MMCSD5_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2057#define OMAP4430_WKUPDEP_MMCSD5_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2058#define OMAP4430_WKUPDEP_MMCSD5_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2059
2060/* Used by PM_L4PER_MMCSD5_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2061#define OMAP4430_WKUPDEP_MMCSD5_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2062#define OMAP4430_WKUPDEP_MMCSD5_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2063
2064/* Used by PM_L4PER_MMCSD5_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2065#define OMAP4430_WKUPDEP_MMCSD5_SDMA_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2066#define OMAP4430_WKUPDEP_MMCSD5_SDMA_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2067
2068/* Used by PM_L3INIT_PCIESS_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2069#define OMAP4430_WKUPDEP_PCIESS_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2070#define OMAP4430_WKUPDEP_PCIESS_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2071
2072/* Used by PM_L3INIT_PCIESS_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2073#define OMAP4430_WKUPDEP_PCIESS_TESLA_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2074#define OMAP4430_WKUPDEP_PCIESS_TESLA_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2075
2076/* Used by PM_ABE_PDM_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2077#define OMAP4430_WKUPDEP_PDM_DMA_SDMA_SHIFT 7
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2078#define OMAP4430_WKUPDEP_PDM_DMA_SDMA_MASK (1 << 7)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2079
2080/* Used by PM_ABE_PDM_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2081#define OMAP4430_WKUPDEP_PDM_DMA_TESLA_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2082#define OMAP4430_WKUPDEP_PDM_DMA_TESLA_MASK (1 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2083
2084/* Used by PM_ABE_PDM_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2085#define OMAP4430_WKUPDEP_PDM_IRQ_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2086#define OMAP4430_WKUPDEP_PDM_IRQ_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2087
2088/* Used by PM_ABE_PDM_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2089#define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2090#define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2091
2092/* Used by PM_WKUP_RTC_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2093#define OMAP4430_WKUPDEP_RTC_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2094#define OMAP4430_WKUPDEP_RTC_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2095
2096/* Used by PM_L3INIT_SATA_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2097#define OMAP4430_WKUPDEP_SATA_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2098#define OMAP4430_WKUPDEP_SATA_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2099
2100/* Used by PM_L3INIT_SATA_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2101#define OMAP4430_WKUPDEP_SATA_TESLA_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2102#define OMAP4430_WKUPDEP_SATA_TESLA_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2103
2104/* Used by PM_ABE_SLIMBUS_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2105#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_SHIFT 7
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2106#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK (1 << 7)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2107
2108/* Used by PM_ABE_SLIMBUS_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2109#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2110#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_MASK (1 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2111
2112/* Used by PM_ABE_SLIMBUS_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2113#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2114#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2115
2116/* Used by PM_ABE_SLIMBUS_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2117#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2118#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2119
2120/* Used by PM_L4PER_SLIMBUS2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2121#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_SHIFT 7
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2122#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_MASK (1 << 7)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2123
2124/* Used by PM_L4PER_SLIMBUS2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2125#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2126#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_MASK (1 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2127
2128/* Used by PM_L4PER_SLIMBUS2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2129#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2130#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2131
2132/* Used by PM_L4PER_SLIMBUS2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2133#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2134#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2135
2136/* Used by PM_ALWON_SR_CORE_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2137#define OMAP4430_WKUPDEP_SR_CORE_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2138#define OMAP4430_WKUPDEP_SR_CORE_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2139
2140/* Used by PM_ALWON_SR_CORE_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2141#define OMAP4430_WKUPDEP_SR_CORE_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2142#define OMAP4430_WKUPDEP_SR_CORE_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2143
2144/* Used by PM_ALWON_SR_IVA_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2145#define OMAP4430_WKUPDEP_SR_IVA_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2146#define OMAP4430_WKUPDEP_SR_IVA_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2147
2148/* Used by PM_ALWON_SR_IVA_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2149#define OMAP4430_WKUPDEP_SR_IVA_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2150#define OMAP4430_WKUPDEP_SR_IVA_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2151
2152/* Used by PM_ALWON_SR_MPU_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2153#define OMAP4430_WKUPDEP_SR_MPU_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2154#define OMAP4430_WKUPDEP_SR_MPU_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2155
2156/* Used by PM_WKUP_TIMER12_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2157#define OMAP4430_WKUPDEP_TIMER12_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2158#define OMAP4430_WKUPDEP_TIMER12_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2159
2160/* Used by PM_WKUP_TIMER1_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2161#define OMAP4430_WKUPDEP_TIMER1_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2162#define OMAP4430_WKUPDEP_TIMER1_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2163
2164/* Used by PM_ABE_TIMER5_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2165#define OMAP4430_WKUPDEP_TIMER5_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2166#define OMAP4430_WKUPDEP_TIMER5_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2167
2168/* Used by PM_ABE_TIMER5_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2169#define OMAP4430_WKUPDEP_TIMER5_TESLA_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2170#define OMAP4430_WKUPDEP_TIMER5_TESLA_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2171
2172/* Used by PM_ABE_TIMER6_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2173#define OMAP4430_WKUPDEP_TIMER6_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2174#define OMAP4430_WKUPDEP_TIMER6_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2175
2176/* Used by PM_ABE_TIMER6_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2177#define OMAP4430_WKUPDEP_TIMER6_TESLA_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2178#define OMAP4430_WKUPDEP_TIMER6_TESLA_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2179
2180/* Used by PM_ABE_TIMER7_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2181#define OMAP4430_WKUPDEP_TIMER7_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2182#define OMAP4430_WKUPDEP_TIMER7_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2183
2184/* Used by PM_ABE_TIMER7_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2185#define OMAP4430_WKUPDEP_TIMER7_TESLA_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2186#define OMAP4430_WKUPDEP_TIMER7_TESLA_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2187
2188/* Used by PM_ABE_TIMER8_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2189#define OMAP4430_WKUPDEP_TIMER8_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2190#define OMAP4430_WKUPDEP_TIMER8_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2191
2192/* Used by PM_ABE_TIMER8_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2193#define OMAP4430_WKUPDEP_TIMER8_TESLA_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2194#define OMAP4430_WKUPDEP_TIMER8_TESLA_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2195
2196/* Used by PM_L4PER_UART1_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2197#define OMAP4430_WKUPDEP_UART1_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2198#define OMAP4430_WKUPDEP_UART1_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2199
2200/* Used by PM_L4PER_UART1_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2201#define OMAP4430_WKUPDEP_UART1_SDMA_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2202#define OMAP4430_WKUPDEP_UART1_SDMA_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2203
2204/* Used by PM_L4PER_UART2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2205#define OMAP4430_WKUPDEP_UART2_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2206#define OMAP4430_WKUPDEP_UART2_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2207
2208/* Used by PM_L4PER_UART2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2209#define OMAP4430_WKUPDEP_UART2_SDMA_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2210#define OMAP4430_WKUPDEP_UART2_SDMA_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2211
2212/* Used by PM_L4PER_UART3_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2213#define OMAP4430_WKUPDEP_UART3_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2214#define OMAP4430_WKUPDEP_UART3_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2215
2216/* Used by PM_L4PER_UART3_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2217#define OMAP4430_WKUPDEP_UART3_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2218#define OMAP4430_WKUPDEP_UART3_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2219
2220/* Used by PM_L4PER_UART3_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2221#define OMAP4430_WKUPDEP_UART3_SDMA_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2222#define OMAP4430_WKUPDEP_UART3_SDMA_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2223
2224/* Used by PM_L4PER_UART3_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2225#define OMAP4430_WKUPDEP_UART3_TESLA_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2226#define OMAP4430_WKUPDEP_UART3_TESLA_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2227
2228/* Used by PM_L4PER_UART4_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2229#define OMAP4430_WKUPDEP_UART4_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2230#define OMAP4430_WKUPDEP_UART4_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2231
2232/* Used by PM_L4PER_UART4_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2233#define OMAP4430_WKUPDEP_UART4_SDMA_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2234#define OMAP4430_WKUPDEP_UART4_SDMA_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2235
2236/* Used by PM_L3INIT_UNIPRO1_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2237#define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2238#define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2239
2240/* Used by PM_L3INIT_UNIPRO1_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2241#define OMAP4430_WKUPDEP_UNIPRO1_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2242#define OMAP4430_WKUPDEP_UNIPRO1_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2243
2244/* Used by PM_L3INIT_USB_HOST_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2245#define OMAP4430_WKUPDEP_USB_HOST_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2246#define OMAP4430_WKUPDEP_USB_HOST_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2247
2248/* Used by PM_L3INIT_USB_HOST_FS_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2249#define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2250#define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2251
2252/* Used by PM_L3INIT_USB_HOST_FS_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2253#define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2254#define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2255
2256/* Used by PM_L3INIT_USB_HOST_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2257#define OMAP4430_WKUPDEP_USB_HOST_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2258#define OMAP4430_WKUPDEP_USB_HOST_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2259
2260/* Used by PM_L3INIT_USB_OTG_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2261#define OMAP4430_WKUPDEP_USB_OTG_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2262#define OMAP4430_WKUPDEP_USB_OTG_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2263
2264/* Used by PM_L3INIT_USB_OTG_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2265#define OMAP4430_WKUPDEP_USB_OTG_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2266#define OMAP4430_WKUPDEP_USB_OTG_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2267
2268/* Used by PM_L3INIT_USB_TLL_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2269#define OMAP4430_WKUPDEP_USB_TLL_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2270#define OMAP4430_WKUPDEP_USB_TLL_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2271
2272/* Used by PM_L3INIT_USB_TLL_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2273#define OMAP4430_WKUPDEP_USB_TLL_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2274#define OMAP4430_WKUPDEP_USB_TLL_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2275
2276/* Used by PM_WKUP_USIM_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2277#define OMAP4430_WKUPDEP_USIM_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2278#define OMAP4430_WKUPDEP_USIM_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2279
2280/* Used by PM_WKUP_USIM_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2281#define OMAP4430_WKUPDEP_USIM_SDMA_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2282#define OMAP4430_WKUPDEP_USIM_SDMA_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2283
2284/* Used by PM_WKUP_WDT2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2285#define OMAP4430_WKUPDEP_WDT2_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2286#define OMAP4430_WKUPDEP_WDT2_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2287
2288/* Used by PM_WKUP_WDT2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2289#define OMAP4430_WKUPDEP_WDT2_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2290#define OMAP4430_WKUPDEP_WDT2_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2291
2292/* Used by PM_ABE_WDT3_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2293#define OMAP4430_WKUPDEP_WDT3_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2294#define OMAP4430_WKUPDEP_WDT3_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2295
2296/* Used by PM_L3INIT_HSI_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2297#define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2298#define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2299
2300/* Used by PM_L3INIT_XHPI_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2301#define OMAP4430_WKUPDEP_XHPI_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2302#define OMAP4430_WKUPDEP_XHPI_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2303
2304/* Used by PRM_IO_PMCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2305#define OMAP4430_WUCLK_CTRL_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2306#define OMAP4430_WUCLK_CTRL_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2307
2308/* Used by PRM_IO_PMCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700[diff] [blame]2309#define OMAP4430_WUCLK_STATUS_SHIFT 9
Rajendra Nayak568997c2010-09-27 14:02:55 -0600[diff] [blame]2310#define OMAP4430_WUCLK_STATUS_MASK (1 << 9)
2311
2312/* Used by REVISION_PRM */
2313#define OMAP4430_X_MAJOR_SHIFT 8
2314#define OMAP4430_X_MAJOR_MASK (0x7 << 8)
2315
2316/* Used by REVISION_PRM */
2317#define OMAP4430_Y_MINOR_SHIFT 0
2318#define OMAP4430_Y_MINOR_MASK (0x3f << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700[diff] [blame]2319#endif