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Stephen M. Cameronedd16362009-12-08 14:09:11 -08001/*
2 * Disk Array driver for HP Smart Array SAS controllers
3 * Copyright 2000, 2009 Hewlett-Packard Development Company, L.P.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
12 * NON INFRINGEMENT. See the GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 *
18 * Questions/Comments/Bugfixes to iss_storagedev@hp.com
19 *
20 */
21#ifndef HPSA_H
22#define HPSA_H
23
24#include <scsi/scsicam.h>
25
26#define IO_OK 0
27#define IO_ERROR 1
28
29struct ctlr_info;
30
31struct access_method {
32 void (*submit_command)(struct ctlr_info *h,
33 struct CommandList *c);
34 void (*set_intr_mask)(struct ctlr_info *h, unsigned long val);
35 unsigned long (*fifo_full)(struct ctlr_info *h);
Stephen M. Cameron900c5442010-02-04 08:42:35 -060036 bool (*intr_pending)(struct ctlr_info *h);
Stephen M. Cameronedd16362009-12-08 14:09:11 -080037 unsigned long (*command_completed)(struct ctlr_info *h);
38};
39
40struct hpsa_scsi_dev_t {
41 int devtype;
42 int bus, target, lun; /* as presented to the OS */
43 unsigned char scsi3addr[8]; /* as presented to the HW */
44#define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0"
45 unsigned char device_id[16]; /* from inquiry pg. 0x83 */
46 unsigned char vendor[8]; /* bytes 8-15 of inquiry data */
47 unsigned char model[16]; /* bytes 16-31 of inquiry data */
48 unsigned char revision[4]; /* bytes 32-35 of inquiry data */
49 unsigned char raid_level; /* from inquiry page 0xC1 */
50};
51
52struct ctlr_info {
53 int ctlr;
54 char devname[8];
55 char *product_name;
Stephen M. Cameronedd16362009-12-08 14:09:11 -080056 struct pci_dev *pdev;
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -060057 u32 board_id;
Stephen M. Cameronedd16362009-12-08 14:09:11 -080058 void __iomem *vaddr;
59 unsigned long paddr;
60 int nr_cmds; /* Number of commands allowed on this controller */
61 struct CfgTable __iomem *cfgtable;
Don Brace303932f2010-02-04 08:42:40 -060062 int max_sg_entries;
Stephen M. Cameronedd16362009-12-08 14:09:11 -080063 int interrupts_enabled;
64 int major;
65 int max_commands;
66 int commands_outstanding;
67 int max_outstanding; /* Debug */
68 int usage_count; /* number of opens all all minor devices */
Don Brace303932f2010-02-04 08:42:40 -060069# define PERF_MODE_INT 0
70# define DOORBELL_INT 1
Stephen M. Cameronedd16362009-12-08 14:09:11 -080071# define SIMPLE_MODE_INT 2
72# define MEMQ_MODE_INT 3
73 unsigned int intr[4];
74 unsigned int msix_vector;
75 unsigned int msi_vector;
76 struct access_method access;
77
78 /* queue and queue Info */
79 struct hlist_head reqQ;
80 struct hlist_head cmpQ;
81 unsigned int Qdepth;
82 unsigned int maxQsinceinit;
83 unsigned int maxSG;
84 spinlock_t lock;
Stephen M. Cameron33a2ffc2010-02-25 14:03:27 -060085 int maxsgentries;
86 u8 max_cmd_sg_entries;
87 int chainsize;
88 struct SGDescriptor **cmd_sg_list;
Stephen M. Cameronedd16362009-12-08 14:09:11 -080089
90 /* pointers to command and error info pool */
91 struct CommandList *cmd_pool;
92 dma_addr_t cmd_pool_dhandle;
93 struct ErrorInfo *errinfo_pool;
94 dma_addr_t errinfo_pool_dhandle;
95 unsigned long *cmd_pool_bits;
96 int nr_allocs;
97 int nr_frees;
98 int busy_initializing;
99 int busy_scanning;
Stephen M. Camerona08a8472010-02-04 08:43:16 -0600100 int scan_finished;
101 spinlock_t scan_lock;
102 wait_queue_head_t scan_wait_queue;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800103
104 struct Scsi_Host *scsi_host;
105 spinlock_t devlock; /* to protect hba[ctlr]->dev[]; */
106 int ndevices; /* number of used elements in .dev[] array. */
107#define HPSA_MAX_SCSI_DEVS_PER_HBA 256
108 struct hpsa_scsi_dev_t *dev[HPSA_MAX_SCSI_DEVS_PER_HBA];
Don Brace303932f2010-02-04 08:42:40 -0600109 /*
110 * Performant mode tables.
111 */
112 u32 trans_support;
113 u32 trans_offset;
114 struct TransTable_struct *transtable;
115 unsigned long transMethod;
116
117 /*
118 * Performant mode completion buffer
119 */
120 u64 *reply_pool;
121 dma_addr_t reply_pool_dhandle;
122 u64 *reply_pool_head;
123 size_t reply_pool_size;
124 unsigned char reply_pool_wraparound;
125 u32 *blockFetchTable;
Stephen M. Cameron339b2b12010-02-04 08:42:50 -0600126 unsigned char *hba_inquiry_data;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800127};
128#define HPSA_ABORT_MSG 0
129#define HPSA_DEVICE_RESET_MSG 1
130#define HPSA_BUS_RESET_MSG 2
131#define HPSA_HOST_RESET_MSG 3
132#define HPSA_MSG_SEND_RETRY_LIMIT 10
133#define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS 1000
134
135/* Maximum time in seconds driver will wait for command completions
136 * when polling before giving up.
137 */
138#define HPSA_MAX_POLL_TIME_SECS (20)
139
140/* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines
141 * how many times to retry TEST UNIT READY on a device
142 * while waiting for it to become ready before giving up.
143 * HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval
144 * between sending TURs while waiting for a device
145 * to become ready.
146 */
147#define HPSA_TUR_RETRY_LIMIT (20)
148#define HPSA_MAX_WAIT_INTERVAL_SECS (30)
149
150/* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board
151 * to become ready, in seconds, before giving up on it.
152 * HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait
153 * between polling the board to see if it is ready, in
154 * milliseconds. HPSA_BOARD_READY_POLL_INTERVAL and
155 * HPSA_BOARD_READY_ITERATIONS are derived from those.
156 */
157#define HPSA_BOARD_READY_WAIT_SECS (120)
158#define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100)
159#define HPSA_BOARD_READY_POLL_INTERVAL \
160 ((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000)
161#define HPSA_BOARD_READY_ITERATIONS \
162 ((HPSA_BOARD_READY_WAIT_SECS * 1000) / \
163 HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
164#define HPSA_POST_RESET_PAUSE_MSECS (3000)
165#define HPSA_POST_RESET_NOOP_RETRIES (12)
166
167/* Defining the diffent access_menthods */
168/*
169 * Memory mapped FIFO interface (SMART 53xx cards)
170 */
171#define SA5_DOORBELL 0x20
172#define SA5_REQUEST_PORT_OFFSET 0x40
173#define SA5_REPLY_INTR_MASK_OFFSET 0x34
174#define SA5_REPLY_PORT_OFFSET 0x44
175#define SA5_INTR_STATUS 0x30
176#define SA5_SCRATCHPAD_OFFSET 0xB0
177
178#define SA5_CTCFG_OFFSET 0xB4
179#define SA5_CTMEM_OFFSET 0xB8
180
181#define SA5_INTR_OFF 0x08
182#define SA5B_INTR_OFF 0x04
183#define SA5_INTR_PENDING 0x08
184#define SA5B_INTR_PENDING 0x04
185#define FIFO_EMPTY 0xffffffff
186#define HPSA_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */
187
188#define HPSA_ERROR_BIT 0x02
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800189
Don Brace303932f2010-02-04 08:42:40 -0600190/* Performant mode flags */
191#define SA5_PERF_INTR_PENDING 0x04
192#define SA5_PERF_INTR_OFF 0x05
193#define SA5_OUTDB_STATUS_PERF_BIT 0x01
194#define SA5_OUTDB_CLEAR_PERF_BIT 0x01
195#define SA5_OUTDB_CLEAR 0xA0
196#define SA5_OUTDB_CLEAR_PERF_BIT 0x01
197#define SA5_OUTDB_STATUS 0x9C
198
199
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800200#define HPSA_INTR_ON 1
201#define HPSA_INTR_OFF 0
202/*
203 Send the command to the hardware
204*/
205static void SA5_submit_command(struct ctlr_info *h,
206 struct CommandList *c)
207{
Don Brace303932f2010-02-04 08:42:40 -0600208 dev_dbg(&h->pdev->dev, "Sending %x, tag = %x\n", c->busaddr,
209 c->Header.Tag.lower);
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800210 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
211 h->commands_outstanding++;
212 if (h->commands_outstanding > h->max_outstanding)
213 h->max_outstanding = h->commands_outstanding;
214}
215
216/*
217 * This card is the opposite of the other cards.
218 * 0 turns interrupts on...
219 * 0x08 turns them off...
220 */
221static void SA5_intr_mask(struct ctlr_info *h, unsigned long val)
222{
223 if (val) { /* Turn interrupts on */
224 h->interrupts_enabled = 1;
225 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
226 } else { /* Turn them off */
227 h->interrupts_enabled = 0;
228 writel(SA5_INTR_OFF,
229 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
230 }
231}
Don Brace303932f2010-02-04 08:42:40 -0600232
233static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val)
234{
235 if (val) { /* turn on interrupts */
236 h->interrupts_enabled = 1;
237 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
238 } else {
239 h->interrupts_enabled = 0;
240 writel(SA5_PERF_INTR_OFF,
241 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
242 }
243}
244
245static unsigned long SA5_performant_completed(struct ctlr_info *h)
246{
247 unsigned long register_value = FIFO_EMPTY;
248
249 /* flush the controller write of the reply queue by reading
250 * outbound doorbell status register.
251 */
252 register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
253 /* msi auto clears the interrupt pending bit. */
254 if (!(h->msi_vector || h->msix_vector)) {
255 writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR);
256 /* Do a read in order to flush the write to the controller
257 * (as per spec.)
258 */
259 register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
260 }
261
262 if ((*(h->reply_pool_head) & 1) == (h->reply_pool_wraparound)) {
263 register_value = *(h->reply_pool_head);
264 (h->reply_pool_head)++;
265 h->commands_outstanding--;
266 } else {
267 register_value = FIFO_EMPTY;
268 }
269 /* Check for wraparound */
270 if (h->reply_pool_head == (h->reply_pool + h->max_commands)) {
271 h->reply_pool_head = h->reply_pool;
272 h->reply_pool_wraparound ^= 1;
273 }
274
275 return register_value;
276}
277
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800278/*
279 * Returns true if fifo is full.
280 *
281 */
282static unsigned long SA5_fifo_full(struct ctlr_info *h)
283{
284 if (h->commands_outstanding >= h->max_commands)
285 return 1;
286 else
287 return 0;
288
289}
290/*
291 * returns value read from hardware.
292 * returns FIFO_EMPTY if there is nothing to read
293 */
294static unsigned long SA5_completed(struct ctlr_info *h)
295{
296 unsigned long register_value
297 = readl(h->vaddr + SA5_REPLY_PORT_OFFSET);
298
299 if (register_value != FIFO_EMPTY)
300 h->commands_outstanding--;
301
302#ifdef HPSA_DEBUG
303 if (register_value != FIFO_EMPTY)
Stephen M. Cameron84ca0be2010-02-04 08:42:30 -0600304 dev_dbg(&h->pdev->dev, "Read %lx back from board\n",
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800305 register_value);
306 else
Stephen M. Cameron84ca0be2010-02-04 08:42:30 -0600307 dev_dbg(&h->pdev->dev, "hpsa: FIFO Empty read\n");
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800308#endif
309
310 return register_value;
311}
312/*
313 * Returns true if an interrupt is pending..
314 */
Stephen M. Cameron900c5442010-02-04 08:42:35 -0600315static bool SA5_intr_pending(struct ctlr_info *h)
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800316{
317 unsigned long register_value =
318 readl(h->vaddr + SA5_INTR_STATUS);
Stephen M. Cameron84ca0be2010-02-04 08:42:30 -0600319 dev_dbg(&h->pdev->dev, "intr_pending %lx\n", register_value);
Stephen M. Cameron900c5442010-02-04 08:42:35 -0600320 return register_value & SA5_INTR_PENDING;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800321}
322
Don Brace303932f2010-02-04 08:42:40 -0600323static bool SA5_performant_intr_pending(struct ctlr_info *h)
324{
325 unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);
326
327 if (!register_value)
328 return false;
329
330 if (h->msi_vector || h->msix_vector)
331 return true;
332
333 /* Read outbound doorbell to flush */
334 register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
335 return register_value & SA5_OUTDB_STATUS_PERF_BIT;
336}
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800337
338static struct access_method SA5_access = {
339 SA5_submit_command,
340 SA5_intr_mask,
341 SA5_fifo_full,
342 SA5_intr_pending,
343 SA5_completed,
344};
345
Don Brace303932f2010-02-04 08:42:40 -0600346static struct access_method SA5_performant_access = {
347 SA5_submit_command,
348 SA5_performant_intr_mask,
349 SA5_fifo_full,
350 SA5_performant_intr_pending,
351 SA5_performant_completed,
352};
353
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800354struct board_type {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600355 u32 board_id;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800356 char *product_name;
357 struct access_method *access;
358};
359
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800360#endif /* HPSA_H */
361