blob: c2df4e429b19d9c30495a5e38ba0ffa71bc9a43c [file] [log] [blame]
Eugeni Dodonov45244b82012-05-09 15:37:20 -03001/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28#include "i915_drv.h"
29#include "intel_drv.h"
30
Jani Nikula10122052014-08-27 16:27:30 +030031struct ddi_buf_trans {
32 u32 trans1; /* balance leg enable, de-emph level */
33 u32 trans2; /* vref sel, vswing */
David Weinehallf8896f52015-06-25 11:11:03 +030034 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
Jani Nikula10122052014-08-27 16:27:30 +030035};
36
Eugeni Dodonov45244b82012-05-09 15:37:20 -030037/* HDMI/DVI modes ignore everything but the last 2 items. So we share
38 * them for both DP and FDI transports, allowing those ports to
39 * automatically adapt to HDMI connections as well
40 */
Jani Nikula10122052014-08-27 16:27:30 +030041static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
David Weinehallf8896f52015-06-25 11:11:03 +030042 { 0x00FFFFFF, 0x0006000E, 0x0 },
43 { 0x00D75FFF, 0x0005000A, 0x0 },
44 { 0x00C30FFF, 0x00040006, 0x0 },
45 { 0x80AAAFFF, 0x000B0000, 0x0 },
46 { 0x00FFFFFF, 0x0005000A, 0x0 },
47 { 0x00D75FFF, 0x000C0004, 0x0 },
48 { 0x80C30FFF, 0x000B0000, 0x0 },
49 { 0x00FFFFFF, 0x00040006, 0x0 },
50 { 0x80D75FFF, 0x000B0000, 0x0 },
Eugeni Dodonov45244b82012-05-09 15:37:20 -030051};
52
Jani Nikula10122052014-08-27 16:27:30 +030053static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
David Weinehallf8896f52015-06-25 11:11:03 +030054 { 0x00FFFFFF, 0x0007000E, 0x0 },
55 { 0x00D75FFF, 0x000F000A, 0x0 },
56 { 0x00C30FFF, 0x00060006, 0x0 },
57 { 0x00AAAFFF, 0x001E0000, 0x0 },
58 { 0x00FFFFFF, 0x000F000A, 0x0 },
59 { 0x00D75FFF, 0x00160004, 0x0 },
60 { 0x00C30FFF, 0x001E0000, 0x0 },
61 { 0x00FFFFFF, 0x00060006, 0x0 },
62 { 0x00D75FFF, 0x001E0000, 0x0 },
Paulo Zanoni6acab152013-09-12 17:06:24 -030063};
64
Jani Nikula10122052014-08-27 16:27:30 +030065static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
66 /* Idx NT mV d T mV d db */
David Weinehallf8896f52015-06-25 11:11:03 +030067 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
68 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
69 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
70 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
71 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
72 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
73 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
74 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
75 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
76 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
77 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
78 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
Eugeni Dodonov45244b82012-05-09 15:37:20 -030079};
80
Jani Nikula10122052014-08-27 16:27:30 +030081static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
David Weinehallf8896f52015-06-25 11:11:03 +030082 { 0x00FFFFFF, 0x00000012, 0x0 },
83 { 0x00EBAFFF, 0x00020011, 0x0 },
84 { 0x00C71FFF, 0x0006000F, 0x0 },
85 { 0x00AAAFFF, 0x000E000A, 0x0 },
86 { 0x00FFFFFF, 0x00020011, 0x0 },
87 { 0x00DB6FFF, 0x0005000F, 0x0 },
88 { 0x00BEEFFF, 0x000A000C, 0x0 },
89 { 0x00FFFFFF, 0x0005000F, 0x0 },
90 { 0x00DB6FFF, 0x000A000C, 0x0 },
Paulo Zanoni300644c2013-11-02 21:07:42 -070091};
92
Jani Nikula10122052014-08-27 16:27:30 +030093static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
David Weinehallf8896f52015-06-25 11:11:03 +030094 { 0x00FFFFFF, 0x0007000E, 0x0 },
95 { 0x00D75FFF, 0x000E000A, 0x0 },
96 { 0x00BEFFFF, 0x00140006, 0x0 },
97 { 0x80B2CFFF, 0x001B0002, 0x0 },
98 { 0x00FFFFFF, 0x000E000A, 0x0 },
99 { 0x00DB6FFF, 0x00160005, 0x0 },
100 { 0x80C71FFF, 0x001A0002, 0x0 },
101 { 0x00F7DFFF, 0x00180004, 0x0 },
102 { 0x80D75FFF, 0x001B0002, 0x0 },
Art Runyane58623c2013-11-02 21:07:41 -0700103};
104
Jani Nikula10122052014-08-27 16:27:30 +0300105static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
David Weinehallf8896f52015-06-25 11:11:03 +0300106 { 0x00FFFFFF, 0x0001000E, 0x0 },
107 { 0x00D75FFF, 0x0004000A, 0x0 },
108 { 0x00C30FFF, 0x00070006, 0x0 },
109 { 0x00AAAFFF, 0x000C0000, 0x0 },
110 { 0x00FFFFFF, 0x0004000A, 0x0 },
111 { 0x00D75FFF, 0x00090004, 0x0 },
112 { 0x00C30FFF, 0x000C0000, 0x0 },
113 { 0x00FFFFFF, 0x00070006, 0x0 },
114 { 0x00D75FFF, 0x000C0000, 0x0 },
Art Runyane58623c2013-11-02 21:07:41 -0700115};
116
Jani Nikula10122052014-08-27 16:27:30 +0300117static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
118 /* Idx NT mV d T mV df db */
David Weinehallf8896f52015-06-25 11:11:03 +0300119 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
120 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
121 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
122 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
123 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
124 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
125 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
126 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
127 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
128 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
Damien Lespiaua26aa8b2014-08-01 11:07:55 +0100129};
130
Rodrigo Vivi5f8b2532015-08-24 16:48:44 -0700131/* Skylake H and S */
Damien Lespiau7f88e3a2013-12-03 13:56:25 +0000132static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
David Weinehallf8896f52015-06-25 11:11:03 +0300133 { 0x00002016, 0x000000A0, 0x0 },
134 { 0x00005012, 0x0000009B, 0x0 },
135 { 0x00007011, 0x00000088, 0x0 },
Rodrigo Vivid7097cf2016-01-05 11:18:55 -0800136 { 0x80009010, 0x000000C0, 0x1 },
David Weinehallf8896f52015-06-25 11:11:03 +0300137 { 0x00002016, 0x0000009B, 0x0 },
138 { 0x00005012, 0x00000088, 0x0 },
Rodrigo Vivid7097cf2016-01-05 11:18:55 -0800139 { 0x80007011, 0x000000C0, 0x1 },
David Weinehallf8896f52015-06-25 11:11:03 +0300140 { 0x00002016, 0x000000DF, 0x0 },
Rodrigo Vivid7097cf2016-01-05 11:18:55 -0800141 { 0x80005012, 0x000000C0, 0x1 },
Damien Lespiau7f88e3a2013-12-03 13:56:25 +0000142};
143
David Weinehallf8896f52015-06-25 11:11:03 +0300144/* Skylake U */
145static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
Rodrigo Vivi5f8b2532015-08-24 16:48:44 -0700146 { 0x0000201B, 0x000000A2, 0x0 },
David Weinehallf8896f52015-06-25 11:11:03 +0300147 { 0x00005012, 0x00000088, 0x0 },
Ville Syrjälä5ac90562016-08-02 15:21:57 +0300148 { 0x80007011, 0x000000CD, 0x1 },
Rodrigo Vivid7097cf2016-01-05 11:18:55 -0800149 { 0x80009010, 0x000000C0, 0x1 },
Rodrigo Vivi5f8b2532015-08-24 16:48:44 -0700150 { 0x0000201B, 0x0000009D, 0x0 },
Rodrigo Vivid7097cf2016-01-05 11:18:55 -0800151 { 0x80005012, 0x000000C0, 0x1 },
152 { 0x80007011, 0x000000C0, 0x1 },
David Weinehallf8896f52015-06-25 11:11:03 +0300153 { 0x00002016, 0x00000088, 0x0 },
Rodrigo Vivid7097cf2016-01-05 11:18:55 -0800154 { 0x80005012, 0x000000C0, 0x1 },
David Weinehallf8896f52015-06-25 11:11:03 +0300155};
156
Rodrigo Vivi5f8b2532015-08-24 16:48:44 -0700157/* Skylake Y */
158static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
David Weinehallf8896f52015-06-25 11:11:03 +0300159 { 0x00000018, 0x000000A2, 0x0 },
160 { 0x00005012, 0x00000088, 0x0 },
Ville Syrjälä5ac90562016-08-02 15:21:57 +0300161 { 0x80007011, 0x000000CD, 0x3 },
Rodrigo Vivid7097cf2016-01-05 11:18:55 -0800162 { 0x80009010, 0x000000C0, 0x3 },
David Weinehallf8896f52015-06-25 11:11:03 +0300163 { 0x00000018, 0x0000009D, 0x0 },
Rodrigo Vivid7097cf2016-01-05 11:18:55 -0800164 { 0x80005012, 0x000000C0, 0x3 },
165 { 0x80007011, 0x000000C0, 0x3 },
David Weinehallf8896f52015-06-25 11:11:03 +0300166 { 0x00000018, 0x00000088, 0x0 },
Rodrigo Vivid7097cf2016-01-05 11:18:55 -0800167 { 0x80005012, 0x000000C0, 0x3 },
David Weinehallf8896f52015-06-25 11:11:03 +0300168};
169
170/*
Rodrigo Vivi5f8b2532015-08-24 16:48:44 -0700171 * Skylake H and S
David Weinehallf8896f52015-06-25 11:11:03 +0300172 * eDP 1.4 low vswing translation parameters
173 */
Sonika Jindal7ad14a22015-02-25 10:29:12 +0530174static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
David Weinehallf8896f52015-06-25 11:11:03 +0300175 { 0x00000018, 0x000000A8, 0x0 },
176 { 0x00004013, 0x000000A9, 0x0 },
177 { 0x00007011, 0x000000A2, 0x0 },
178 { 0x00009010, 0x0000009C, 0x0 },
179 { 0x00000018, 0x000000A9, 0x0 },
180 { 0x00006013, 0x000000A2, 0x0 },
181 { 0x00007011, 0x000000A6, 0x0 },
182 { 0x00000018, 0x000000AB, 0x0 },
183 { 0x00007013, 0x0000009F, 0x0 },
184 { 0x00000018, 0x000000DF, 0x0 },
Sonika Jindal7ad14a22015-02-25 10:29:12 +0530185};
186
David Weinehallf8896f52015-06-25 11:11:03 +0300187/*
188 * Skylake U
189 * eDP 1.4 low vswing translation parameters
190 */
191static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
192 { 0x00000018, 0x000000A8, 0x0 },
193 { 0x00004013, 0x000000A9, 0x0 },
194 { 0x00007011, 0x000000A2, 0x0 },
195 { 0x00009010, 0x0000009C, 0x0 },
196 { 0x00000018, 0x000000A9, 0x0 },
197 { 0x00006013, 0x000000A2, 0x0 },
198 { 0x00007011, 0x000000A6, 0x0 },
199 { 0x00002016, 0x000000AB, 0x0 },
200 { 0x00005013, 0x0000009F, 0x0 },
201 { 0x00000018, 0x000000DF, 0x0 },
202};
Sonika Jindal7ad14a22015-02-25 10:29:12 +0530203
David Weinehallf8896f52015-06-25 11:11:03 +0300204/*
Rodrigo Vivi5f8b2532015-08-24 16:48:44 -0700205 * Skylake Y
David Weinehallf8896f52015-06-25 11:11:03 +0300206 * eDP 1.4 low vswing translation parameters
207 */
Rodrigo Vivi5f8b2532015-08-24 16:48:44 -0700208static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
David Weinehallf8896f52015-06-25 11:11:03 +0300209 { 0x00000018, 0x000000A8, 0x0 },
210 { 0x00004013, 0x000000AB, 0x0 },
211 { 0x00007011, 0x000000A4, 0x0 },
212 { 0x00009010, 0x000000DF, 0x0 },
213 { 0x00000018, 0x000000AA, 0x0 },
214 { 0x00006013, 0x000000A4, 0x0 },
215 { 0x00007011, 0x0000009D, 0x0 },
216 { 0x00000018, 0x000000A0, 0x0 },
217 { 0x00006012, 0x000000DF, 0x0 },
218 { 0x00000018, 0x0000008A, 0x0 },
219};
220
Rodrigo Vivi5f8b2532015-08-24 16:48:44 -0700221/* Skylake U, H and S */
Damien Lespiau7f88e3a2013-12-03 13:56:25 +0000222static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
David Weinehallf8896f52015-06-25 11:11:03 +0300223 { 0x00000018, 0x000000AC, 0x0 },
224 { 0x00005012, 0x0000009D, 0x0 },
225 { 0x00007011, 0x00000088, 0x0 },
226 { 0x00000018, 0x000000A1, 0x0 },
227 { 0x00000018, 0x00000098, 0x0 },
228 { 0x00004013, 0x00000088, 0x0 },
Rodrigo Vivi2e784162016-01-05 11:11:27 -0800229 { 0x80006012, 0x000000CD, 0x1 },
David Weinehallf8896f52015-06-25 11:11:03 +0300230 { 0x00000018, 0x000000DF, 0x0 },
Rodrigo Vivi2e784162016-01-05 11:11:27 -0800231 { 0x80003015, 0x000000CD, 0x1 }, /* Default */
232 { 0x80003015, 0x000000C0, 0x1 },
233 { 0x80000018, 0x000000C0, 0x1 },
David Weinehallf8896f52015-06-25 11:11:03 +0300234};
235
Rodrigo Vivi5f8b2532015-08-24 16:48:44 -0700236/* Skylake Y */
237static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
David Weinehallf8896f52015-06-25 11:11:03 +0300238 { 0x00000018, 0x000000A1, 0x0 },
239 { 0x00005012, 0x000000DF, 0x0 },
Rodrigo Vivi2e784162016-01-05 11:11:27 -0800240 { 0x80007011, 0x000000CB, 0x3 },
David Weinehallf8896f52015-06-25 11:11:03 +0300241 { 0x00000018, 0x000000A4, 0x0 },
242 { 0x00000018, 0x0000009D, 0x0 },
243 { 0x00004013, 0x00000080, 0x0 },
Rodrigo Vivi2e784162016-01-05 11:11:27 -0800244 { 0x80006013, 0x000000C0, 0x3 },
David Weinehallf8896f52015-06-25 11:11:03 +0300245 { 0x00000018, 0x0000008A, 0x0 },
Rodrigo Vivi2e784162016-01-05 11:11:27 -0800246 { 0x80003015, 0x000000C0, 0x3 }, /* Default */
247 { 0x80003015, 0x000000C0, 0x3 },
248 { 0x80000018, 0x000000C0, 0x3 },
Damien Lespiau7f88e3a2013-12-03 13:56:25 +0000249};
250
Vandana Kannan96fb9f92014-11-18 15:45:27 +0530251struct bxt_ddi_buf_trans {
252 u32 margin; /* swing value */
253 u32 scale; /* scale value */
254 u32 enable; /* scale enable */
255 u32 deemphasis;
256 bool default_index; /* true if the entry represents default value */
257};
258
Vandana Kannan96fb9f92014-11-18 15:45:27 +0530259static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
260 /* Idx NT mV diff db */
Imre Deakfe4c63c2015-06-04 18:01:35 +0300261 { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */
262 { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
263 { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */
264 { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
265 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
266 { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
267 { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */
268 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
269 { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
David Weinehallf8896f52015-06-25 11:11:03 +0300270 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
Vandana Kannan96fb9f92014-11-18 15:45:27 +0530271};
272
Sonika Jindald9d70002015-09-24 10:24:56 +0530273static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
274 /* Idx NT mV diff db */
275 { 26, 0, 0, 128, false }, /* 0: 200 0 */
276 { 38, 0, 0, 112, false }, /* 1: 200 1.5 */
277 { 48, 0, 0, 96, false }, /* 2: 200 4 */
278 { 54, 0, 0, 69, false }, /* 3: 200 6 */
279 { 32, 0, 0, 128, false }, /* 4: 250 0 */
280 { 48, 0, 0, 104, false }, /* 5: 250 1.5 */
281 { 54, 0, 0, 85, false }, /* 6: 250 4 */
282 { 43, 0, 0, 128, false }, /* 7: 300 0 */
283 { 54, 0, 0, 101, false }, /* 8: 300 1.5 */
284 { 48, 0, 0, 128, false }, /* 9: 300 0 */
285};
286
Vandana Kannan96fb9f92014-11-18 15:45:27 +0530287/* BSpec has 2 recommended values - entries 0 and 8.
288 * Using the entry with higher vswing.
289 */
290static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
291 /* Idx NT mV diff db */
Imre Deakfe4c63c2015-06-04 18:01:35 +0300292 { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */
293 { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
294 { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */
295 { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
296 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
297 { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
298 { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */
299 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
300 { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
Vandana Kannan96fb9f92014-11-18 15:45:27 +0530301 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
302};
303
Ville Syrjälä5a5d24d2016-07-12 15:59:35 +0300304enum port intel_ddi_get_encoder_port(struct intel_encoder *encoder)
Paulo Zanonifc914632012-10-05 12:05:54 -0300305{
Ville Syrjälä5a5d24d2016-07-12 15:59:35 +0300306 switch (encoder->type) {
Jani Nikula8cd21b72015-09-29 10:24:26 +0300307 case INTEL_OUTPUT_DP_MST:
Ville Syrjälä5a5d24d2016-07-12 15:59:35 +0300308 return enc_to_mst(&encoder->base)->primary->port;
Ville Syrjäläcca05022016-06-22 21:57:06 +0300309 case INTEL_OUTPUT_DP:
Jani Nikula8cd21b72015-09-29 10:24:26 +0300310 case INTEL_OUTPUT_EDP:
311 case INTEL_OUTPUT_HDMI:
312 case INTEL_OUTPUT_UNKNOWN:
Ville Syrjälä5a5d24d2016-07-12 15:59:35 +0300313 return enc_to_dig_port(&encoder->base)->port;
Jani Nikula8cd21b72015-09-29 10:24:26 +0300314 case INTEL_OUTPUT_ANALOG:
Ville Syrjälä5a5d24d2016-07-12 15:59:35 +0300315 return PORT_E;
316 default:
317 MISSING_CASE(encoder->type);
318 return PORT_A;
Paulo Zanonifc914632012-10-05 12:05:54 -0300319 }
320}
321
Ville Syrjäläacee2992015-12-08 19:59:39 +0200322static const struct ddi_buf_trans *
Ville Syrjäläa930acd2016-07-12 15:59:36 +0300323bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
324{
325 if (dev_priv->vbt.edp.low_vswing) {
326 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
327 return bdw_ddi_translations_edp;
328 } else {
329 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
330 return bdw_ddi_translations_dp;
331 }
332}
333
334static const struct ddi_buf_trans *
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +0200335skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
David Weinehallf8896f52015-06-25 11:11:03 +0300336{
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +0200337 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
Rodrigo Vivi5f8b2532015-08-24 16:48:44 -0700338 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
Ville Syrjäläacee2992015-12-08 19:59:39 +0200339 return skl_y_ddi_translations_dp;
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +0200340 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) {
David Weinehallf8896f52015-06-25 11:11:03 +0300341 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
Ville Syrjäläacee2992015-12-08 19:59:39 +0200342 return skl_u_ddi_translations_dp;
David Weinehallf8896f52015-06-25 11:11:03 +0300343 } else {
David Weinehallf8896f52015-06-25 11:11:03 +0300344 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
Ville Syrjäläacee2992015-12-08 19:59:39 +0200345 return skl_ddi_translations_dp;
David Weinehallf8896f52015-06-25 11:11:03 +0300346 }
David Weinehallf8896f52015-06-25 11:11:03 +0300347}
348
349static const struct ddi_buf_trans *
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +0200350skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
David Weinehallf8896f52015-06-25 11:11:03 +0300351{
Jani Nikula06411f02016-03-24 17:50:21 +0200352 if (dev_priv->vbt.edp.low_vswing) {
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +0200353 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
Ville Syrjäläacee2992015-12-08 19:59:39 +0200354 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
355 return skl_y_ddi_translations_edp;
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +0200356 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) {
Ville Syrjäläacee2992015-12-08 19:59:39 +0200357 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
358 return skl_u_ddi_translations_edp;
359 } else {
Ville Syrjäläacee2992015-12-08 19:59:39 +0200360 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
361 return skl_ddi_translations_edp;
Ville Syrjäläacee2992015-12-08 19:59:39 +0200362 }
David Weinehallf8896f52015-06-25 11:11:03 +0300363 }
Ville Syrjäläcd1101c2015-12-08 19:59:40 +0200364
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +0200365 return skl_get_buf_trans_dp(dev_priv, n_entries);
Ville Syrjäläacee2992015-12-08 19:59:39 +0200366}
David Weinehallf8896f52015-06-25 11:11:03 +0300367
Ville Syrjäläacee2992015-12-08 19:59:39 +0200368static const struct ddi_buf_trans *
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +0200369skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
Ville Syrjäläacee2992015-12-08 19:59:39 +0200370{
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +0200371 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
Ville Syrjäläacee2992015-12-08 19:59:39 +0200372 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
373 return skl_y_ddi_translations_hdmi;
374 } else {
375 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
376 return skl_ddi_translations_hdmi;
377 }
David Weinehallf8896f52015-06-25 11:11:03 +0300378}
379
Ville Syrjälä8d8bb852016-07-12 15:59:30 +0300380static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
381{
382 int n_hdmi_entries;
383 int hdmi_level;
384 int hdmi_default_entry;
385
386 hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
387
388 if (IS_BROXTON(dev_priv))
389 return hdmi_level;
390
391 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
392 skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
393 hdmi_default_entry = 8;
394 } else if (IS_BROADWELL(dev_priv)) {
395 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
396 hdmi_default_entry = 7;
397 } else if (IS_HASWELL(dev_priv)) {
398 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
399 hdmi_default_entry = 6;
400 } else {
401 WARN(1, "ddi translation table missing\n");
402 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
403 hdmi_default_entry = 7;
404 }
405
406 /* Choose a good default if VBT is badly populated */
407 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
408 hdmi_level >= n_hdmi_entries)
409 hdmi_level = hdmi_default_entry;
410
411 return hdmi_level;
412}
413
Art Runyane58623c2013-11-02 21:07:41 -0700414/*
415 * Starting with Haswell, DDI port buffers must be programmed with correct
Ville Syrjälä32bdc402016-07-12 15:59:33 +0300416 * values in advance. This function programs the correct values for
417 * DP/eDP/FDI use cases.
Eugeni Dodonov45244b82012-05-09 15:37:20 -0300418 */
Ville Syrjälä32bdc402016-07-12 15:59:33 +0300419void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder)
Eugeni Dodonov45244b82012-05-09 15:37:20 -0300420{
Ville Syrjälä6a7e4f92015-12-08 19:59:44 +0200421 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
Antti Koskipaa75067dd2015-07-10 14:10:55 +0300422 u32 iboost_bit = 0;
Ville Syrjälä32bdc402016-07-12 15:59:33 +0300423 int i, n_dp_entries, n_edp_entries, size;
424 enum port port = intel_ddi_get_encoder_port(encoder);
Jani Nikula10122052014-08-27 16:27:30 +0300425 const struct ddi_buf_trans *ddi_translations_fdi;
426 const struct ddi_buf_trans *ddi_translations_dp;
427 const struct ddi_buf_trans *ddi_translations_edp;
Jani Nikula10122052014-08-27 16:27:30 +0300428 const struct ddi_buf_trans *ddi_translations;
Art Runyane58623c2013-11-02 21:07:41 -0700429
Ville Syrjälä9f332432016-07-12 15:59:31 +0300430 if (IS_BROXTON(dev_priv))
Vandana Kannan96fb9f92014-11-18 15:45:27 +0530431 return;
Ville Syrjälä6a7e4f92015-12-08 19:59:44 +0200432
433 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
Paulo Zanonic30400f2015-07-03 12:31:30 -0300434 ddi_translations_fdi = NULL;
David Weinehallf8896f52015-06-25 11:11:03 +0300435 ddi_translations_dp =
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +0200436 skl_get_buf_trans_dp(dev_priv, &n_dp_entries);
David Weinehallf8896f52015-06-25 11:11:03 +0300437 ddi_translations_edp =
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +0200438 skl_get_buf_trans_edp(dev_priv, &n_edp_entries);
Ville Syrjälä32bdc402016-07-12 15:59:33 +0300439
Antti Koskipaa75067dd2015-07-10 14:10:55 +0300440 /* If we're boosting the current, set bit 31 of trans1 */
Ville Syrjälä1edaaa22016-07-12 15:59:34 +0300441 if (dev_priv->vbt.ddi_port_info[port].dp_boost_level)
Ville Syrjäläc110ae62016-07-12 15:59:29 +0300442 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
Ville Syrjälä10afa0b2015-12-08 19:59:43 +0200443
Ville Syrjäläceccad52016-01-12 17:28:16 +0200444 if (WARN_ON(encoder->type == INTEL_OUTPUT_EDP &&
445 port != PORT_A && port != PORT_E &&
446 n_edp_entries > 9))
Ville Syrjälä10afa0b2015-12-08 19:59:43 +0200447 n_edp_entries = 9;
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +0200448 } else if (IS_BROADWELL(dev_priv)) {
Art Runyane58623c2013-11-02 21:07:41 -0700449 ddi_translations_fdi = bdw_ddi_translations_fdi;
450 ddi_translations_dp = bdw_ddi_translations_dp;
Ville Syrjäläa930acd2016-07-12 15:59:36 +0300451 ddi_translations_edp = bdw_get_buf_trans_edp(dev_priv, &n_edp_entries);
Sonika Jindal7ad14a22015-02-25 10:29:12 +0530452 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +0200453 } else if (IS_HASWELL(dev_priv)) {
Art Runyane58623c2013-11-02 21:07:41 -0700454 ddi_translations_fdi = hsw_ddi_translations_fdi;
455 ddi_translations_dp = hsw_ddi_translations_dp;
Paulo Zanoni300644c2013-11-02 21:07:42 -0700456 ddi_translations_edp = hsw_ddi_translations_dp;
Sonika Jindal7ad14a22015-02-25 10:29:12 +0530457 n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
Art Runyane58623c2013-11-02 21:07:41 -0700458 } else {
459 WARN(1, "ddi translation table missing\n");
Paulo Zanoni300644c2013-11-02 21:07:42 -0700460 ddi_translations_edp = bdw_ddi_translations_dp;
Art Runyane58623c2013-11-02 21:07:41 -0700461 ddi_translations_fdi = bdw_ddi_translations_fdi;
462 ddi_translations_dp = bdw_ddi_translations_dp;
Sonika Jindal7ad14a22015-02-25 10:29:12 +0530463 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
464 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
Art Runyane58623c2013-11-02 21:07:41 -0700465 }
466
Ville Syrjälä6a7e4f92015-12-08 19:59:44 +0200467 switch (encoder->type) {
468 case INTEL_OUTPUT_EDP:
Paulo Zanoni300644c2013-11-02 21:07:42 -0700469 ddi_translations = ddi_translations_edp;
Sonika Jindal7ad14a22015-02-25 10:29:12 +0530470 size = n_edp_entries;
Paulo Zanoni300644c2013-11-02 21:07:42 -0700471 break;
Ville Syrjäläcca05022016-06-22 21:57:06 +0300472 case INTEL_OUTPUT_DP:
Paulo Zanoni300644c2013-11-02 21:07:42 -0700473 ddi_translations = ddi_translations_dp;
Sonika Jindal7ad14a22015-02-25 10:29:12 +0530474 size = n_dp_entries;
Paulo Zanoni300644c2013-11-02 21:07:42 -0700475 break;
Ville Syrjälä6a7e4f92015-12-08 19:59:44 +0200476 case INTEL_OUTPUT_ANALOG:
477 ddi_translations = ddi_translations_fdi;
Sonika Jindal7ad14a22015-02-25 10:29:12 +0530478 size = n_dp_entries;
Paulo Zanoni300644c2013-11-02 21:07:42 -0700479 break;
480 default:
481 BUG();
482 }
Eugeni Dodonov45244b82012-05-09 15:37:20 -0300483
Ville Syrjälä9712e682015-09-18 20:03:22 +0300484 for (i = 0; i < size; i++) {
485 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
486 ddi_translations[i].trans1 | iboost_bit);
487 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
488 ddi_translations[i].trans2);
Eugeni Dodonov45244b82012-05-09 15:37:20 -0300489 }
Ville Syrjälä32bdc402016-07-12 15:59:33 +0300490}
Damien Lespiauce4dd492014-08-01 11:07:54 +0100491
Ville Syrjälä32bdc402016-07-12 15:59:33 +0300492/*
493 * Starting with Haswell, DDI port buffers must be programmed with correct
494 * values in advance. This function programs the correct values for
495 * HDMI/DVI use cases.
496 */
497static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder)
498{
499 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
500 u32 iboost_bit = 0;
501 int n_hdmi_entries, hdmi_level;
502 enum port port = intel_ddi_get_encoder_port(encoder);
503 const struct ddi_buf_trans *ddi_translations_hdmi;
504
505 if (IS_BROXTON(dev_priv))
Damien Lespiauce3b7e92014-08-04 15:04:43 +0100506 return;
507
Ville Syrjälä32bdc402016-07-12 15:59:33 +0300508 hdmi_level = intel_ddi_hdmi_level(dev_priv, port);
509
510 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
511 ddi_translations_hdmi = skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
Ville Syrjälä1edaaa22016-07-12 15:59:34 +0300512
Ville Syrjälä32bdc402016-07-12 15:59:33 +0300513 /* If we're boosting the current, set bit 31 of trans1 */
Ville Syrjälä1edaaa22016-07-12 15:59:34 +0300514 if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
Ville Syrjälä32bdc402016-07-12 15:59:33 +0300515 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
516 } else if (IS_BROADWELL(dev_priv)) {
517 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
518 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
519 } else if (IS_HASWELL(dev_priv)) {
520 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
521 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
522 } else {
523 WARN(1, "ddi translation table missing\n");
524 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
525 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
526 }
527
Paulo Zanoni6acab152013-09-12 17:06:24 -0300528 /* Entry 9 is for HDMI: */
Ville Syrjäläed9c77d2016-07-12 15:59:32 +0300529 I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
Ville Syrjälä9712e682015-09-18 20:03:22 +0300530 ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit);
Ville Syrjäläed9c77d2016-07-12 15:59:32 +0300531 I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
Ville Syrjälä9712e682015-09-18 20:03:22 +0300532 ddi_translations_hdmi[hdmi_level].trans2);
Eugeni Dodonov45244b82012-05-09 15:37:20 -0300533}
534
Paulo Zanoni248138b2012-11-29 11:29:31 -0200535static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
536 enum port port)
537{
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200538 i915_reg_t reg = DDI_BUF_CTL(port);
Paulo Zanoni248138b2012-11-29 11:29:31 -0200539 int i;
540
Vandana Kannan3449ca82015-03-27 14:19:09 +0200541 for (i = 0; i < 16; i++) {
Paulo Zanoni248138b2012-11-29 11:29:31 -0200542 udelay(1);
543 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
544 return;
545 }
546 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
547}
Eugeni Dodonovc82e4d22012-05-09 15:37:21 -0300548
549/* Starting with Haswell, different DDI ports can work in FDI mode for
550 * connection to the PCH-located connectors. For this, it is necessary to train
551 * both the DDI port and PCH receiver for the desired DDI buffer settings.
552 *
553 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
554 * please note that when FDI mode is active on DDI E, it shares 2 lines with
555 * DDI A (which is used for eDP)
556 */
557
558void hsw_fdi_link_train(struct drm_crtc *crtc)
559{
560 struct drm_device *dev = crtc->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +0100561 struct drm_i915_private *dev_priv = to_i915(dev);
Eugeni Dodonovc82e4d22012-05-09 15:37:21 -0300562 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Ville Syrjälä6a7e4f92015-12-08 19:59:44 +0200563 struct intel_encoder *encoder;
Paulo Zanoni04945642012-11-01 21:00:59 -0200564 u32 temp, i, rx_ctl_val;
Eugeni Dodonovc82e4d22012-05-09 15:37:21 -0300565
Ville Syrjälä6a7e4f92015-12-08 19:59:44 +0200566 for_each_encoder_on_crtc(dev, crtc, encoder) {
567 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
Ville Syrjälä32bdc402016-07-12 15:59:33 +0300568 intel_prepare_dp_ddi_buffers(encoder);
Ville Syrjälä6a7e4f92015-12-08 19:59:44 +0200569 }
570
Paulo Zanoni04945642012-11-01 21:00:59 -0200571 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
572 * mode set "sequence for CRT port" document:
573 * - TP1 to TP2 time with the default value
574 * - FDI delay to 90h
Damien Lespiau8693a822013-05-03 18:48:11 +0100575 *
576 * WaFDIAutoLinkSetTimingOverrride:hsw
Paulo Zanoni04945642012-11-01 21:00:59 -0200577 */
Ville Syrjäläeede3b52015-09-18 20:03:30 +0300578 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
Paulo Zanoni04945642012-11-01 21:00:59 -0200579 FDI_RX_PWRDN_LANE0_VAL(2) |
580 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
581
582 /* Enable the PCH Receiver FDI PLL */
Damien Lespiau3e683202012-12-11 18:48:29 +0000583 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
Daniel Vetter33d29b12013-02-13 18:04:45 +0100584 FDI_RX_PLL_ENABLE |
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +0200585 FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
Ville Syrjäläeede3b52015-09-18 20:03:30 +0300586 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
587 POSTING_READ(FDI_RX_CTL(PIPE_A));
Paulo Zanoni04945642012-11-01 21:00:59 -0200588 udelay(220);
589
590 /* Switch from Rawclk to PCDclk */
591 rx_ctl_val |= FDI_PCDCLK;
Ville Syrjäläeede3b52015-09-18 20:03:30 +0300592 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
Paulo Zanoni04945642012-11-01 21:00:59 -0200593
594 /* Configure Port Clock Select */
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +0200595 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
596 WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
Paulo Zanoni04945642012-11-01 21:00:59 -0200597
598 /* Start the training iterating through available voltages and emphasis,
599 * testing each value twice. */
Jani Nikula10122052014-08-27 16:27:30 +0300600 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
Eugeni Dodonovc82e4d22012-05-09 15:37:21 -0300601 /* Configure DP_TP_CTL with auto-training */
602 I915_WRITE(DP_TP_CTL(PORT_E),
603 DP_TP_CTL_FDI_AUTOTRAIN |
604 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
605 DP_TP_CTL_LINK_TRAIN_PAT1 |
606 DP_TP_CTL_ENABLE);
607
Damien Lespiau876a8cd2012-12-11 18:48:30 +0000608 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
609 * DDI E does not support port reversal, the functionality is
610 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
611 * port reversal bit */
Eugeni Dodonovc82e4d22012-05-09 15:37:21 -0300612 I915_WRITE(DDI_BUF_CTL(PORT_E),
Paulo Zanoni04945642012-11-01 21:00:59 -0200613 DDI_BUF_CTL_ENABLE |
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +0200614 ((intel_crtc->config->fdi_lanes - 1) << 1) |
Sonika Jindalc5fe6a02014-08-11 08:57:36 +0530615 DDI_BUF_TRANS_SELECT(i / 2));
Paulo Zanoni04945642012-11-01 21:00:59 -0200616 POSTING_READ(DDI_BUF_CTL(PORT_E));
Eugeni Dodonovc82e4d22012-05-09 15:37:21 -0300617
618 udelay(600);
619
Paulo Zanoni04945642012-11-01 21:00:59 -0200620 /* Program PCH FDI Receiver TU */
Ville Syrjäläeede3b52015-09-18 20:03:30 +0300621 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
Eugeni Dodonov4acf5182012-07-04 20:15:16 -0300622
Paulo Zanoni04945642012-11-01 21:00:59 -0200623 /* Enable PCH FDI Receiver with auto-training */
624 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
Ville Syrjäläeede3b52015-09-18 20:03:30 +0300625 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
626 POSTING_READ(FDI_RX_CTL(PIPE_A));
Paulo Zanoni04945642012-11-01 21:00:59 -0200627
628 /* Wait for FDI receiver lane calibration */
629 udelay(30);
630
631 /* Unset FDI_RX_MISC pwrdn lanes */
Ville Syrjäläeede3b52015-09-18 20:03:30 +0300632 temp = I915_READ(FDI_RX_MISC(PIPE_A));
Paulo Zanoni04945642012-11-01 21:00:59 -0200633 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
Ville Syrjäläeede3b52015-09-18 20:03:30 +0300634 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
635 POSTING_READ(FDI_RX_MISC(PIPE_A));
Paulo Zanoni04945642012-11-01 21:00:59 -0200636
637 /* Wait for FDI auto training time */
638 udelay(5);
Eugeni Dodonovc82e4d22012-05-09 15:37:21 -0300639
640 temp = I915_READ(DP_TP_STATUS(PORT_E));
641 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
Paulo Zanoni04945642012-11-01 21:00:59 -0200642 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
Ville Syrjäläa308ccb2015-12-04 22:22:50 +0200643 break;
644 }
Eugeni Dodonovc82e4d22012-05-09 15:37:21 -0300645
Ville Syrjäläa308ccb2015-12-04 22:22:50 +0200646 /*
647 * Leave things enabled even if we failed to train FDI.
648 * Results in less fireworks from the state checker.
649 */
650 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
651 DRM_ERROR("FDI link training failed!\n");
652 break;
Eugeni Dodonovc82e4d22012-05-09 15:37:21 -0300653 }
Paulo Zanoni04945642012-11-01 21:00:59 -0200654
Ville Syrjälä5b421c52016-03-01 16:16:23 +0200655 rx_ctl_val &= ~FDI_RX_ENABLE;
656 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
657 POSTING_READ(FDI_RX_CTL(PIPE_A));
658
Paulo Zanoni248138b2012-11-29 11:29:31 -0200659 temp = I915_READ(DDI_BUF_CTL(PORT_E));
660 temp &= ~DDI_BUF_CTL_ENABLE;
661 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
662 POSTING_READ(DDI_BUF_CTL(PORT_E));
663
Paulo Zanoni04945642012-11-01 21:00:59 -0200664 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
Paulo Zanoni248138b2012-11-29 11:29:31 -0200665 temp = I915_READ(DP_TP_CTL(PORT_E));
666 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
667 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
668 I915_WRITE(DP_TP_CTL(PORT_E), temp);
669 POSTING_READ(DP_TP_CTL(PORT_E));
670
671 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
Paulo Zanoni04945642012-11-01 21:00:59 -0200672
Paulo Zanoni04945642012-11-01 21:00:59 -0200673 /* Reset FDI_RX_MISC pwrdn lanes */
Ville Syrjäläeede3b52015-09-18 20:03:30 +0300674 temp = I915_READ(FDI_RX_MISC(PIPE_A));
Paulo Zanoni04945642012-11-01 21:00:59 -0200675 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
676 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
Ville Syrjäläeede3b52015-09-18 20:03:30 +0300677 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
678 POSTING_READ(FDI_RX_MISC(PIPE_A));
Eugeni Dodonovc82e4d22012-05-09 15:37:21 -0300679 }
680
Ville Syrjäläa308ccb2015-12-04 22:22:50 +0200681 /* Enable normal pixel sending for FDI */
682 I915_WRITE(DP_TP_CTL(PORT_E),
683 DP_TP_CTL_FDI_AUTOTRAIN |
684 DP_TP_CTL_LINK_TRAIN_NORMAL |
685 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
686 DP_TP_CTL_ENABLE);
Eugeni Dodonovc82e4d22012-05-09 15:37:21 -0300687}
Eugeni Dodonov0e72a5b2012-05-09 15:37:27 -0300688
Dave Airlie44905a272014-05-02 13:36:43 +1000689void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
690{
691 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
692 struct intel_digital_port *intel_dig_port =
693 enc_to_dig_port(&encoder->base);
694
695 intel_dp->DP = intel_dig_port->saved_port_bits |
Sonika Jindalc5fe6a02014-08-11 08:57:36 +0530696 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
Ville Syrjälä901c2da2015-08-17 18:05:12 +0300697 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
Dave Airlie44905a272014-05-02 13:36:43 +1000698}
699
Paulo Zanoni8d9ddbc2012-10-05 12:05:53 -0300700static struct intel_encoder *
701intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
702{
703 struct drm_device *dev = crtc->dev;
704 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
705 struct intel_encoder *intel_encoder, *ret = NULL;
706 int num_encoders = 0;
707
708 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
709 ret = intel_encoder;
710 num_encoders++;
711 }
712
713 if (num_encoders != 1)
Ville Syrjälä84f44ce2013-04-17 17:48:49 +0300714 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
715 pipe_name(intel_crtc->pipe));
Paulo Zanoni8d9ddbc2012-10-05 12:05:53 -0300716
717 BUG_ON(ret == NULL);
718 return ret;
719}
720
Satheeshakrishna Mbcddf612014-08-22 09:49:10 +0530721struct intel_encoder *
Ander Conselvan de Oliveira3165c072015-03-20 16:18:12 +0200722intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200723{
Ander Conselvan de Oliveira3165c072015-03-20 16:18:12 +0200724 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
725 struct intel_encoder *ret = NULL;
726 struct drm_atomic_state *state;
Ander Conselvan de Oliveirada3ced22015-04-21 17:12:59 +0300727 struct drm_connector *connector;
728 struct drm_connector_state *connector_state;
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200729 int num_encoders = 0;
Ander Conselvan de Oliveira3165c072015-03-20 16:18:12 +0200730 int i;
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200731
Ander Conselvan de Oliveira3165c072015-03-20 16:18:12 +0200732 state = crtc_state->base.state;
733
Ander Conselvan de Oliveirada3ced22015-04-21 17:12:59 +0300734 for_each_connector_in_state(state, connector, connector_state, i) {
735 if (connector_state->crtc != crtc_state->base.crtc)
Ander Conselvan de Oliveira3165c072015-03-20 16:18:12 +0200736 continue;
737
Ander Conselvan de Oliveirada3ced22015-04-21 17:12:59 +0300738 ret = to_intel_encoder(connector_state->best_encoder);
Ander Conselvan de Oliveira3165c072015-03-20 16:18:12 +0200739 num_encoders++;
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200740 }
741
742 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
743 pipe_name(crtc->pipe));
744
745 BUG_ON(ret == NULL);
746 return ret;
747}
748
Damien Lespiau1c0b85c2013-05-10 14:01:51 +0100749#define LC_FREQ 2700
Damien Lespiau1c0b85c2013-05-10 14:01:51 +0100750
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200751static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
752 i915_reg_t reg)
Jesse Barnes11578552014-01-21 12:42:10 -0800753{
754 int refclk = LC_FREQ;
755 int n, p, r;
756 u32 wrpll;
757
758 wrpll = I915_READ(reg);
Daniel Vetter114fe482014-06-25 22:01:48 +0300759 switch (wrpll & WRPLL_PLL_REF_MASK) {
760 case WRPLL_PLL_SSC:
761 case WRPLL_PLL_NON_SSC:
Jesse Barnes11578552014-01-21 12:42:10 -0800762 /*
763 * We could calculate spread here, but our checking
764 * code only cares about 5% accuracy, and spread is a max of
765 * 0.5% downspread.
766 */
767 refclk = 135;
768 break;
Daniel Vetter114fe482014-06-25 22:01:48 +0300769 case WRPLL_PLL_LCPLL:
Jesse Barnes11578552014-01-21 12:42:10 -0800770 refclk = LC_FREQ;
771 break;
772 default:
773 WARN(1, "bad wrpll refclk\n");
774 return 0;
775 }
776
777 r = wrpll & WRPLL_DIVIDER_REF_MASK;
778 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
779 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
780
Jesse Barnes20f0ec12014-01-22 12:58:04 -0800781 /* Convert to KHz, p & r have a fixed point portion */
782 return (refclk * n * 100) / (p * r);
Jesse Barnes11578552014-01-21 12:42:10 -0800783}
784
Satheeshakrishna M540e7322014-11-13 14:55:16 +0000785static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
786 uint32_t dpll)
787{
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200788 i915_reg_t cfgcr1_reg, cfgcr2_reg;
Satheeshakrishna M540e7322014-11-13 14:55:16 +0000789 uint32_t cfgcr1_val, cfgcr2_val;
790 uint32_t p0, p1, p2, dco_freq;
791
Ville Syrjälä923c12412015-09-30 17:06:43 +0300792 cfgcr1_reg = DPLL_CFGCR1(dpll);
793 cfgcr2_reg = DPLL_CFGCR2(dpll);
Satheeshakrishna M540e7322014-11-13 14:55:16 +0000794
795 cfgcr1_val = I915_READ(cfgcr1_reg);
796 cfgcr2_val = I915_READ(cfgcr2_reg);
797
798 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
799 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
800
801 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
802 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
803 else
804 p1 = 1;
805
806
807 switch (p0) {
808 case DPLL_CFGCR2_PDIV_1:
809 p0 = 1;
810 break;
811 case DPLL_CFGCR2_PDIV_2:
812 p0 = 2;
813 break;
814 case DPLL_CFGCR2_PDIV_3:
815 p0 = 3;
816 break;
817 case DPLL_CFGCR2_PDIV_7:
818 p0 = 7;
819 break;
820 }
821
822 switch (p2) {
823 case DPLL_CFGCR2_KDIV_5:
824 p2 = 5;
825 break;
826 case DPLL_CFGCR2_KDIV_2:
827 p2 = 2;
828 break;
829 case DPLL_CFGCR2_KDIV_3:
830 p2 = 3;
831 break;
832 case DPLL_CFGCR2_KDIV_1:
833 p2 = 1;
834 break;
835 }
836
837 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
838
839 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
840 1000) / 0x8000;
841
842 return dco_freq / (p0 * p1 * p2 * 5);
843}
844
Ville Syrjälä398a0172015-06-30 15:33:51 +0300845static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
846{
847 int dotclock;
848
849 if (pipe_config->has_pch_encoder)
850 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
851 &pipe_config->fdi_m_n);
Ville Syrjälä37a56502016-06-22 21:57:04 +0300852 else if (intel_crtc_has_dp_encoder(pipe_config))
Ville Syrjälä398a0172015-06-30 15:33:51 +0300853 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
854 &pipe_config->dp_m_n);
855 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
856 dotclock = pipe_config->port_clock * 2 / 3;
857 else
858 dotclock = pipe_config->port_clock;
859
860 if (pipe_config->pixel_multiplier)
861 dotclock /= pipe_config->pixel_multiplier;
862
863 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
864}
Satheeshakrishna M540e7322014-11-13 14:55:16 +0000865
866static void skl_ddi_clock_get(struct intel_encoder *encoder,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +0200867 struct intel_crtc_state *pipe_config)
Satheeshakrishna M540e7322014-11-13 14:55:16 +0000868{
Chris Wilsonfac5e232016-07-04 11:34:36 +0100869 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
Satheeshakrishna M540e7322014-11-13 14:55:16 +0000870 int link_clock = 0;
871 uint32_t dpll_ctl1, dpll;
872
Damien Lespiau134ffa42014-11-14 17:24:34 +0000873 dpll = pipe_config->ddi_pll_sel;
Satheeshakrishna M540e7322014-11-13 14:55:16 +0000874
875 dpll_ctl1 = I915_READ(DPLL_CTRL1);
876
877 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
878 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
879 } else {
Damien Lespiau71cd8422015-04-30 16:39:17 +0100880 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
881 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
Satheeshakrishna M540e7322014-11-13 14:55:16 +0000882
883 switch (link_clock) {
Damien Lespiau71cd8422015-04-30 16:39:17 +0100884 case DPLL_CTRL1_LINK_RATE_810:
Satheeshakrishna M540e7322014-11-13 14:55:16 +0000885 link_clock = 81000;
886 break;
Damien Lespiau71cd8422015-04-30 16:39:17 +0100887 case DPLL_CTRL1_LINK_RATE_1080:
Sonika Jindala8f3ef62015-03-05 10:02:30 +0530888 link_clock = 108000;
889 break;
Damien Lespiau71cd8422015-04-30 16:39:17 +0100890 case DPLL_CTRL1_LINK_RATE_1350:
Satheeshakrishna M540e7322014-11-13 14:55:16 +0000891 link_clock = 135000;
892 break;
Damien Lespiau71cd8422015-04-30 16:39:17 +0100893 case DPLL_CTRL1_LINK_RATE_1620:
Sonika Jindala8f3ef62015-03-05 10:02:30 +0530894 link_clock = 162000;
895 break;
Damien Lespiau71cd8422015-04-30 16:39:17 +0100896 case DPLL_CTRL1_LINK_RATE_2160:
Sonika Jindala8f3ef62015-03-05 10:02:30 +0530897 link_clock = 216000;
898 break;
Damien Lespiau71cd8422015-04-30 16:39:17 +0100899 case DPLL_CTRL1_LINK_RATE_2700:
Satheeshakrishna M540e7322014-11-13 14:55:16 +0000900 link_clock = 270000;
901 break;
902 default:
903 WARN(1, "Unsupported link rate\n");
904 break;
905 }
906 link_clock *= 2;
907 }
908
909 pipe_config->port_clock = link_clock;
910
Ville Syrjälä398a0172015-06-30 15:33:51 +0300911 ddi_dotclock_get(pipe_config);
Satheeshakrishna M540e7322014-11-13 14:55:16 +0000912}
913
Daniel Vetter3d51278a2014-07-29 20:57:08 +0200914static void hsw_ddi_clock_get(struct intel_encoder *encoder,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +0200915 struct intel_crtc_state *pipe_config)
Jesse Barnes11578552014-01-21 12:42:10 -0800916{
Chris Wilsonfac5e232016-07-04 11:34:36 +0100917 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
Jesse Barnes11578552014-01-21 12:42:10 -0800918 int link_clock = 0;
919 u32 val, pll;
920
Daniel Vetter26804af2014-06-25 22:01:55 +0300921 val = pipe_config->ddi_pll_sel;
Jesse Barnes11578552014-01-21 12:42:10 -0800922 switch (val & PORT_CLK_SEL_MASK) {
923 case PORT_CLK_SEL_LCPLL_810:
924 link_clock = 81000;
925 break;
926 case PORT_CLK_SEL_LCPLL_1350:
927 link_clock = 135000;
928 break;
929 case PORT_CLK_SEL_LCPLL_2700:
930 link_clock = 270000;
931 break;
932 case PORT_CLK_SEL_WRPLL1:
Ville Syrjälä01403de2015-09-18 20:03:33 +0300933 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
Jesse Barnes11578552014-01-21 12:42:10 -0800934 break;
935 case PORT_CLK_SEL_WRPLL2:
Ville Syrjälä01403de2015-09-18 20:03:33 +0300936 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
Jesse Barnes11578552014-01-21 12:42:10 -0800937 break;
938 case PORT_CLK_SEL_SPLL:
939 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
940 if (pll == SPLL_PLL_FREQ_810MHz)
941 link_clock = 81000;
942 else if (pll == SPLL_PLL_FREQ_1350MHz)
943 link_clock = 135000;
944 else if (pll == SPLL_PLL_FREQ_2700MHz)
945 link_clock = 270000;
946 else {
947 WARN(1, "bad spll freq\n");
948 return;
949 }
950 break;
951 default:
952 WARN(1, "bad port clock sel\n");
953 return;
954 }
955
956 pipe_config->port_clock = link_clock * 2;
957
Ville Syrjälä398a0172015-06-30 15:33:51 +0300958 ddi_dotclock_get(pipe_config);
Jesse Barnes11578552014-01-21 12:42:10 -0800959}
960
Satheeshakrishna M977bb382014-08-22 09:49:12 +0530961static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
962 enum intel_dpll_id dpll)
963{
Imre Deakaa610dc2015-06-22 23:35:52 +0300964 struct intel_shared_dpll *pll;
965 struct intel_dpll_hw_state *state;
Ander Conselvan de Oliveira9e2c8472016-05-04 12:11:57 +0300966 struct dpll clock;
Imre Deakaa610dc2015-06-22 23:35:52 +0300967
968 /* For DDI ports we always use a shared PLL. */
969 if (WARN_ON(dpll == DPLL_ID_PRIVATE))
970 return 0;
971
972 pll = &dev_priv->shared_dplls[dpll];
973 state = &pll->config.hw_state;
974
975 clock.m1 = 2;
976 clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
977 if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
978 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
979 clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
980 clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
981 clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
982
983 return chv_calc_dpll_params(100000, &clock);
Satheeshakrishna M977bb382014-08-22 09:49:12 +0530984}
985
986static void bxt_ddi_clock_get(struct intel_encoder *encoder,
987 struct intel_crtc_state *pipe_config)
988{
Chris Wilsonfac5e232016-07-04 11:34:36 +0100989 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
Satheeshakrishna M977bb382014-08-22 09:49:12 +0530990 enum port port = intel_ddi_get_encoder_port(encoder);
991 uint32_t dpll = port;
992
Ville Syrjälä398a0172015-06-30 15:33:51 +0300993 pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll);
Satheeshakrishna M977bb382014-08-22 09:49:12 +0530994
Ville Syrjälä398a0172015-06-30 15:33:51 +0300995 ddi_dotclock_get(pipe_config);
Satheeshakrishna M977bb382014-08-22 09:49:12 +0530996}
997
Daniel Vetter3d51278a2014-07-29 20:57:08 +0200998void intel_ddi_clock_get(struct intel_encoder *encoder,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +0200999 struct intel_crtc_state *pipe_config)
Daniel Vetter3d51278a2014-07-29 20:57:08 +02001000{
Damien Lespiau22606a12014-12-12 14:26:57 +00001001 struct drm_device *dev = encoder->base.dev;
1002
1003 if (INTEL_INFO(dev)->gen <= 8)
1004 hsw_ddi_clock_get(encoder, pipe_config);
Rodrigo Vivief11bdb2015-10-28 04:16:45 -07001005 else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
Damien Lespiau22606a12014-12-12 14:26:57 +00001006 skl_ddi_clock_get(encoder, pipe_config);
Satheeshakrishna M977bb382014-08-22 09:49:12 +05301007 else if (IS_BROXTON(dev))
1008 bxt_ddi_clock_get(encoder, pipe_config);
Daniel Vetter3d51278a2014-07-29 20:57:08 +02001009}
1010
Damien Lespiau0220ab62014-07-29 18:06:22 +01001011static bool
Damien Lespiaud664c0c2014-07-29 18:06:23 +01001012hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02001013 struct intel_crtc_state *crtc_state,
Ville Syrjälä96f3f1f2015-07-06 15:10:02 +03001014 struct intel_encoder *intel_encoder)
Paulo Zanoni6441ab52012-10-05 12:05:58 -03001015{
Ander Conselvan de Oliveiradaedf202016-03-08 17:46:23 +02001016 struct intel_shared_dpll *pll;
Ville Syrjälä96f3f1f2015-07-06 15:10:02 +03001017
Ander Conselvan de Oliveira9d16da62016-03-08 17:46:26 +02001018 pll = intel_get_shared_dpll(intel_crtc, crtc_state,
1019 intel_encoder);
1020 if (!pll)
1021 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1022 pipe_name(intel_crtc->pipe));
1023
1024 return pll;
Paulo Zanoni6441ab52012-10-05 12:05:58 -03001025}
1026
Satheeshakrishna M82d35432014-11-13 14:55:20 +00001027static bool
1028skl_ddi_pll_select(struct intel_crtc *intel_crtc,
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02001029 struct intel_crtc_state *crtc_state,
Ville Syrjälä96f3f1f2015-07-06 15:10:02 +03001030 struct intel_encoder *intel_encoder)
Satheeshakrishna M82d35432014-11-13 14:55:20 +00001031{
1032 struct intel_shared_dpll *pll;
Satheeshakrishna M82d35432014-11-13 14:55:20 +00001033
Ander Conselvan de Oliveiradaedf202016-03-08 17:46:23 +02001034 pll = intel_get_shared_dpll(intel_crtc, crtc_state, intel_encoder);
Satheeshakrishna M82d35432014-11-13 14:55:20 +00001035 if (pll == NULL) {
1036 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1037 pipe_name(intel_crtc->pipe));
1038 return false;
1039 }
1040
Satheeshakrishna M82d35432014-11-13 14:55:20 +00001041 return true;
1042}
Damien Lespiau0220ab62014-07-29 18:06:22 +01001043
Satheeshakrishna Md683f3b2014-08-22 09:49:08 +05301044static bool
1045bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
1046 struct intel_crtc_state *crtc_state,
Ville Syrjälä96f3f1f2015-07-06 15:10:02 +03001047 struct intel_encoder *intel_encoder)
Satheeshakrishna Md683f3b2014-08-22 09:49:08 +05301048{
Ander Conselvan de Oliveira34177c22016-03-08 17:46:25 +02001049 return !!intel_get_shared_dpll(intel_crtc, crtc_state, intel_encoder);
Satheeshakrishna Md683f3b2014-08-22 09:49:08 +05301050}
1051
Damien Lespiau0220ab62014-07-29 18:06:22 +01001052/*
1053 * Tries to find a *shared* PLL for the CRTC and store it in
1054 * intel_crtc->ddi_pll_sel.
1055 *
1056 * For private DPLLs, compute_config() should do the selection for us. This
1057 * function should be folded into compute_config() eventually.
1058 */
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02001059bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
1060 struct intel_crtc_state *crtc_state)
Damien Lespiau0220ab62014-07-29 18:06:22 +01001061{
Satheeshakrishna M82d35432014-11-13 14:55:20 +00001062 struct drm_device *dev = intel_crtc->base.dev;
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02001063 struct intel_encoder *intel_encoder =
Ander Conselvan de Oliveira3165c072015-03-20 16:18:12 +02001064 intel_ddi_get_crtc_new_encoder(crtc_state);
Damien Lespiau0220ab62014-07-29 18:06:22 +01001065
Rodrigo Vivief11bdb2015-10-28 04:16:45 -07001066 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02001067 return skl_ddi_pll_select(intel_crtc, crtc_state,
Ville Syrjälä96f3f1f2015-07-06 15:10:02 +03001068 intel_encoder);
Satheeshakrishna Md683f3b2014-08-22 09:49:08 +05301069 else if (IS_BROXTON(dev))
1070 return bxt_ddi_pll_select(intel_crtc, crtc_state,
Ville Syrjälä96f3f1f2015-07-06 15:10:02 +03001071 intel_encoder);
Satheeshakrishna M82d35432014-11-13 14:55:20 +00001072 else
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02001073 return hsw_ddi_pll_select(intel_crtc, crtc_state,
Ville Syrjälä96f3f1f2015-07-06 15:10:02 +03001074 intel_encoder);
Damien Lespiau0220ab62014-07-29 18:06:22 +01001075}
1076
Paulo Zanonidae84792012-10-15 15:51:30 -03001077void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
1078{
Chris Wilsonfac5e232016-07-04 11:34:36 +01001079 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
Paulo Zanonidae84792012-10-15 15:51:30 -03001080 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1081 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001082 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
Paulo Zanonidae84792012-10-15 15:51:30 -03001083 int type = intel_encoder->type;
1084 uint32_t temp;
1085
Ville Syrjäläcca05022016-06-22 21:57:06 +03001086 if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
Jani Nikula4d1de972016-03-18 17:05:42 +02001087 WARN_ON(transcoder_is_dsi(cpu_transcoder));
1088
Paulo Zanonic9809792012-10-23 18:30:00 -02001089 temp = TRANS_MSA_SYNC_CLK;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001090 switch (intel_crtc->config->pipe_bpp) {
Paulo Zanonidae84792012-10-15 15:51:30 -03001091 case 18:
Paulo Zanonic9809792012-10-23 18:30:00 -02001092 temp |= TRANS_MSA_6_BPC;
Paulo Zanonidae84792012-10-15 15:51:30 -03001093 break;
1094 case 24:
Paulo Zanonic9809792012-10-23 18:30:00 -02001095 temp |= TRANS_MSA_8_BPC;
Paulo Zanonidae84792012-10-15 15:51:30 -03001096 break;
1097 case 30:
Paulo Zanonic9809792012-10-23 18:30:00 -02001098 temp |= TRANS_MSA_10_BPC;
Paulo Zanonidae84792012-10-15 15:51:30 -03001099 break;
1100 case 36:
Paulo Zanonic9809792012-10-23 18:30:00 -02001101 temp |= TRANS_MSA_12_BPC;
Paulo Zanonidae84792012-10-15 15:51:30 -03001102 break;
1103 default:
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01001104 BUG();
Paulo Zanonidae84792012-10-15 15:51:30 -03001105 }
Paulo Zanonic9809792012-10-23 18:30:00 -02001106 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
Paulo Zanonidae84792012-10-15 15:51:30 -03001107 }
1108}
1109
Dave Airlie0e32b392014-05-02 14:02:48 +10001110void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
1111{
1112 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1113 struct drm_device *dev = crtc->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01001114 struct drm_i915_private *dev_priv = to_i915(dev);
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001115 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
Dave Airlie0e32b392014-05-02 14:02:48 +10001116 uint32_t temp;
1117 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1118 if (state == true)
1119 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1120 else
1121 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1122 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1123}
1124
Damien Lespiau8228c252013-03-07 15:30:27 +00001125void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
Paulo Zanoni8d9ddbc2012-10-05 12:05:53 -03001126{
1127 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1128 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
Paulo Zanonic7670b12013-11-02 21:07:37 -07001129 struct drm_device *dev = crtc->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01001130 struct drm_i915_private *dev_priv = to_i915(dev);
Paulo Zanoni8d9ddbc2012-10-05 12:05:53 -03001131 enum pipe pipe = intel_crtc->pipe;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001132 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
Paulo Zanoni174edf12012-10-26 19:05:50 -02001133 enum port port = intel_ddi_get_encoder_port(intel_encoder);
Paulo Zanoni7739c332012-10-15 15:51:29 -03001134 int type = intel_encoder->type;
Paulo Zanoni8d9ddbc2012-10-05 12:05:53 -03001135 uint32_t temp;
1136
Paulo Zanoniad80a812012-10-24 16:06:19 -02001137 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1138 temp = TRANS_DDI_FUNC_ENABLE;
Paulo Zanoni174edf12012-10-26 19:05:50 -02001139 temp |= TRANS_DDI_SELECT_PORT(port);
Paulo Zanonidfcef252012-08-08 14:15:29 -03001140
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001141 switch (intel_crtc->config->pipe_bpp) {
Paulo Zanonidfcef252012-08-08 14:15:29 -03001142 case 18:
Paulo Zanoniad80a812012-10-24 16:06:19 -02001143 temp |= TRANS_DDI_BPC_6;
Paulo Zanonidfcef252012-08-08 14:15:29 -03001144 break;
1145 case 24:
Paulo Zanoniad80a812012-10-24 16:06:19 -02001146 temp |= TRANS_DDI_BPC_8;
Paulo Zanonidfcef252012-08-08 14:15:29 -03001147 break;
1148 case 30:
Paulo Zanoniad80a812012-10-24 16:06:19 -02001149 temp |= TRANS_DDI_BPC_10;
Paulo Zanonidfcef252012-08-08 14:15:29 -03001150 break;
1151 case 36:
Paulo Zanoniad80a812012-10-24 16:06:19 -02001152 temp |= TRANS_DDI_BPC_12;
Paulo Zanonidfcef252012-08-08 14:15:29 -03001153 break;
1154 default:
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01001155 BUG();
Paulo Zanonidfcef252012-08-08 14:15:29 -03001156 }
Eugeni Dodonov72662e12012-05-09 15:37:31 -03001157
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001158 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
Paulo Zanoniad80a812012-10-24 16:06:19 -02001159 temp |= TRANS_DDI_PVSYNC;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001160 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
Paulo Zanoniad80a812012-10-24 16:06:19 -02001161 temp |= TRANS_DDI_PHSYNC;
Paulo Zanonif63eb7c42012-08-08 14:15:28 -03001162
Paulo Zanonie6f0bfc2012-10-23 18:30:04 -02001163 if (cpu_transcoder == TRANSCODER_EDP) {
1164 switch (pipe) {
1165 case PIPE_A:
Paulo Zanonic7670b12013-11-02 21:07:37 -07001166 /* On Haswell, can only use the always-on power well for
1167 * eDP when not using the panel fitter, and when not
1168 * using motion blur mitigation (which we don't
1169 * support). */
Daniel Vetterfabf6e52014-05-29 14:10:22 +02001170 if (IS_HASWELL(dev) &&
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001171 (intel_crtc->config->pch_pfit.enabled ||
1172 intel_crtc->config->pch_pfit.force_thru))
Daniel Vetterd6dd9eb2013-01-29 16:35:20 -02001173 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1174 else
1175 temp |= TRANS_DDI_EDP_INPUT_A_ON;
Paulo Zanonie6f0bfc2012-10-23 18:30:04 -02001176 break;
1177 case PIPE_B:
1178 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1179 break;
1180 case PIPE_C:
1181 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1182 break;
1183 default:
1184 BUG();
1185 break;
1186 }
1187 }
1188
Paulo Zanoni7739c332012-10-15 15:51:29 -03001189 if (type == INTEL_OUTPUT_HDMI) {
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001190 if (intel_crtc->config->has_hdmi_sink)
Paulo Zanoniad80a812012-10-24 16:06:19 -02001191 temp |= TRANS_DDI_MODE_SELECT_HDMI;
Paulo Zanoni8d9ddbc2012-10-05 12:05:53 -03001192 else
Paulo Zanoniad80a812012-10-24 16:06:19 -02001193 temp |= TRANS_DDI_MODE_SELECT_DVI;
Paulo Zanoni7739c332012-10-15 15:51:29 -03001194 } else if (type == INTEL_OUTPUT_ANALOG) {
Paulo Zanoniad80a812012-10-24 16:06:19 -02001195 temp |= TRANS_DDI_MODE_SELECT_FDI;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001196 temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
Ville Syrjäläcca05022016-06-22 21:57:06 +03001197 } else if (type == INTEL_OUTPUT_DP ||
Paulo Zanoni7739c332012-10-15 15:51:29 -03001198 type == INTEL_OUTPUT_EDP) {
Ville Syrjälä64ee2fd2016-07-28 17:50:39 +03001199 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
Ville Syrjälä90a6b7b2015-07-06 16:39:15 +03001200 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
Dave Airlie0e32b392014-05-02 14:02:48 +10001201 } else if (type == INTEL_OUTPUT_DP_MST) {
Ville Syrjälä64ee2fd2016-07-28 17:50:39 +03001202 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
Ville Syrjälä90a6b7b2015-07-06 16:39:15 +03001203 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
Paulo Zanoni8d9ddbc2012-10-05 12:05:53 -03001204 } else {
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03001205 WARN(1, "Invalid encoder type %d for pipe %c\n",
1206 intel_encoder->type, pipe_name(pipe));
Paulo Zanoni8d9ddbc2012-10-05 12:05:53 -03001207 }
1208
Paulo Zanoniad80a812012-10-24 16:06:19 -02001209 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
Paulo Zanoni8d9ddbc2012-10-05 12:05:53 -03001210}
1211
Paulo Zanoniad80a812012-10-24 16:06:19 -02001212void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1213 enum transcoder cpu_transcoder)
Paulo Zanoni8d9ddbc2012-10-05 12:05:53 -03001214{
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001215 i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
Paulo Zanoni8d9ddbc2012-10-05 12:05:53 -03001216 uint32_t val = I915_READ(reg);
1217
Dave Airlie0e32b392014-05-02 14:02:48 +10001218 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
Paulo Zanoniad80a812012-10-24 16:06:19 -02001219 val |= TRANS_DDI_PORT_NONE;
Paulo Zanoni8d9ddbc2012-10-05 12:05:53 -03001220 I915_WRITE(reg, val);
Eugeni Dodonov72662e12012-05-09 15:37:31 -03001221}
1222
Paulo Zanonibcbc8892012-10-26 19:05:51 -02001223bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1224{
1225 struct drm_device *dev = intel_connector->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01001226 struct drm_i915_private *dev_priv = to_i915(dev);
Paulo Zanonibcbc8892012-10-26 19:05:51 -02001227 struct intel_encoder *intel_encoder = intel_connector->encoder;
1228 int type = intel_connector->base.connector_type;
1229 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1230 enum pipe pipe = 0;
1231 enum transcoder cpu_transcoder;
Paulo Zanoni882244a2014-04-01 14:55:12 -03001232 enum intel_display_power_domain power_domain;
Paulo Zanonibcbc8892012-10-26 19:05:51 -02001233 uint32_t tmp;
Imre Deake27daab2016-02-12 18:55:16 +02001234 bool ret;
Paulo Zanonibcbc8892012-10-26 19:05:51 -02001235
Paulo Zanoni882244a2014-04-01 14:55:12 -03001236 power_domain = intel_display_port_power_domain(intel_encoder);
Imre Deake27daab2016-02-12 18:55:16 +02001237 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
Paulo Zanoni882244a2014-04-01 14:55:12 -03001238 return false;
1239
Imre Deake27daab2016-02-12 18:55:16 +02001240 if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) {
1241 ret = false;
1242 goto out;
1243 }
Paulo Zanonibcbc8892012-10-26 19:05:51 -02001244
1245 if (port == PORT_A)
1246 cpu_transcoder = TRANSCODER_EDP;
1247 else
Daniel Vetter1a240d42012-11-29 22:18:51 +01001248 cpu_transcoder = (enum transcoder) pipe;
Paulo Zanonibcbc8892012-10-26 19:05:51 -02001249
1250 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1251
1252 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1253 case TRANS_DDI_MODE_SELECT_HDMI:
1254 case TRANS_DDI_MODE_SELECT_DVI:
Imre Deake27daab2016-02-12 18:55:16 +02001255 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1256 break;
Paulo Zanonibcbc8892012-10-26 19:05:51 -02001257
1258 case TRANS_DDI_MODE_SELECT_DP_SST:
Imre Deake27daab2016-02-12 18:55:16 +02001259 ret = type == DRM_MODE_CONNECTOR_eDP ||
1260 type == DRM_MODE_CONNECTOR_DisplayPort;
1261 break;
1262
Dave Airlie0e32b392014-05-02 14:02:48 +10001263 case TRANS_DDI_MODE_SELECT_DP_MST:
1264 /* if the transcoder is in MST state then
1265 * connector isn't connected */
Imre Deake27daab2016-02-12 18:55:16 +02001266 ret = false;
1267 break;
Paulo Zanonibcbc8892012-10-26 19:05:51 -02001268
1269 case TRANS_DDI_MODE_SELECT_FDI:
Imre Deake27daab2016-02-12 18:55:16 +02001270 ret = type == DRM_MODE_CONNECTOR_VGA;
1271 break;
Paulo Zanonibcbc8892012-10-26 19:05:51 -02001272
1273 default:
Imre Deake27daab2016-02-12 18:55:16 +02001274 ret = false;
1275 break;
Paulo Zanonibcbc8892012-10-26 19:05:51 -02001276 }
Imre Deake27daab2016-02-12 18:55:16 +02001277
1278out:
1279 intel_display_power_put(dev_priv, power_domain);
1280
1281 return ret;
Paulo Zanonibcbc8892012-10-26 19:05:51 -02001282}
1283
Daniel Vetter85234cd2012-07-02 13:27:29 +02001284bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1285 enum pipe *pipe)
1286{
1287 struct drm_device *dev = encoder->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01001288 struct drm_i915_private *dev_priv = to_i915(dev);
Paulo Zanonife43d3f2012-10-15 15:51:39 -03001289 enum port port = intel_ddi_get_encoder_port(encoder);
Imre Deak6d129be2014-03-05 16:20:54 +02001290 enum intel_display_power_domain power_domain;
Daniel Vetter85234cd2012-07-02 13:27:29 +02001291 u32 tmp;
1292 int i;
Imre Deake27daab2016-02-12 18:55:16 +02001293 bool ret;
Daniel Vetter85234cd2012-07-02 13:27:29 +02001294
Imre Deak6d129be2014-03-05 16:20:54 +02001295 power_domain = intel_display_port_power_domain(encoder);
Imre Deake27daab2016-02-12 18:55:16 +02001296 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
Imre Deak6d129be2014-03-05 16:20:54 +02001297 return false;
1298
Imre Deake27daab2016-02-12 18:55:16 +02001299 ret = false;
1300
Paulo Zanonife43d3f2012-10-15 15:51:39 -03001301 tmp = I915_READ(DDI_BUF_CTL(port));
Daniel Vetter85234cd2012-07-02 13:27:29 +02001302
1303 if (!(tmp & DDI_BUF_CTL_ENABLE))
Imre Deake27daab2016-02-12 18:55:16 +02001304 goto out;
Daniel Vetter85234cd2012-07-02 13:27:29 +02001305
Paulo Zanoniad80a812012-10-24 16:06:19 -02001306 if (port == PORT_A) {
1307 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
Daniel Vetter85234cd2012-07-02 13:27:29 +02001308
Paulo Zanoniad80a812012-10-24 16:06:19 -02001309 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1310 case TRANS_DDI_EDP_INPUT_A_ON:
1311 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1312 *pipe = PIPE_A;
1313 break;
1314 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1315 *pipe = PIPE_B;
1316 break;
1317 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1318 *pipe = PIPE_C;
1319 break;
1320 }
1321
Imre Deake27daab2016-02-12 18:55:16 +02001322 ret = true;
Paulo Zanoniad80a812012-10-24 16:06:19 -02001323
Imre Deake27daab2016-02-12 18:55:16 +02001324 goto out;
1325 }
Dave Airlie0e32b392014-05-02 14:02:48 +10001326
Imre Deake27daab2016-02-12 18:55:16 +02001327 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1328 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1329
1330 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) {
1331 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
1332 TRANS_DDI_MODE_SELECT_DP_MST)
1333 goto out;
1334
1335 *pipe = i;
1336 ret = true;
1337
1338 goto out;
Daniel Vetter85234cd2012-07-02 13:27:29 +02001339 }
1340 }
1341
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03001342 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
Daniel Vetter85234cd2012-07-02 13:27:29 +02001343
Imre Deake27daab2016-02-12 18:55:16 +02001344out:
Imre Deake93da0a2016-06-13 16:44:37 +03001345 if (ret && IS_BROXTON(dev_priv)) {
1346 tmp = I915_READ(BXT_PHY_CTL(port));
1347 if ((tmp & (BXT_PHY_LANE_POWERDOWN_ACK |
1348 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
1349 DRM_ERROR("Port %c enabled but PHY powered down? "
1350 "(PHY_CTL %08x)\n", port_name(port), tmp);
1351 }
1352
Imre Deake27daab2016-02-12 18:55:16 +02001353 intel_display_power_put(dev_priv, power_domain);
1354
1355 return ret;
Daniel Vetter85234cd2012-07-02 13:27:29 +02001356}
1357
Paulo Zanonifc914632012-10-05 12:05:54 -03001358void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1359{
1360 struct drm_crtc *crtc = &intel_crtc->base;
Shashank Sharma7d4aefd2015-10-01 22:23:49 +05301361 struct drm_device *dev = crtc->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01001362 struct drm_i915_private *dev_priv = to_i915(dev);
Paulo Zanonifc914632012-10-05 12:05:54 -03001363 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1364 enum port port = intel_ddi_get_encoder_port(intel_encoder);
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001365 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
Paulo Zanonifc914632012-10-05 12:05:54 -03001366
Paulo Zanonibb523fc2012-10-23 18:29:56 -02001367 if (cpu_transcoder != TRANSCODER_EDP)
1368 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1369 TRANS_CLK_SEL_PORT(port));
Paulo Zanonifc914632012-10-05 12:05:54 -03001370}
1371
1372void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1373{
Chris Wilsonfac5e232016-07-04 11:34:36 +01001374 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001375 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
Paulo Zanonifc914632012-10-05 12:05:54 -03001376
Paulo Zanonibb523fc2012-10-23 18:29:56 -02001377 if (cpu_transcoder != TRANSCODER_EDP)
1378 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1379 TRANS_CLK_SEL_DISABLED);
Paulo Zanonifc914632012-10-05 12:05:54 -03001380}
1381
Ville Syrjäläa7d8dbc2016-07-12 15:59:28 +03001382static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
1383 enum port port, uint8_t iboost)
David Weinehallf8896f52015-06-25 11:11:03 +03001384{
Ville Syrjäläa7d8dbc2016-07-12 15:59:28 +03001385 u32 tmp;
1386
1387 tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
1388 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
1389 if (iboost)
1390 tmp |= iboost << BALANCE_LEG_SHIFT(port);
1391 else
1392 tmp |= BALANCE_LEG_DISABLE(port);
1393 I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
1394}
1395
1396static void skl_ddi_set_iboost(struct intel_encoder *encoder, u32 level)
1397{
1398 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
1399 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
1400 enum port port = intel_dig_port->port;
1401 int type = encoder->type;
David Weinehallf8896f52015-06-25 11:11:03 +03001402 const struct ddi_buf_trans *ddi_translations;
1403 uint8_t iboost;
Antti Koskipaa75067dd2015-07-10 14:10:55 +03001404 uint8_t dp_iboost, hdmi_iboost;
David Weinehallf8896f52015-06-25 11:11:03 +03001405 int n_entries;
David Weinehallf8896f52015-06-25 11:11:03 +03001406
Antti Koskipaa75067dd2015-07-10 14:10:55 +03001407 /* VBT may override standard boost values */
1408 dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
1409 hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
1410
Ville Syrjäläcca05022016-06-22 21:57:06 +03001411 if (type == INTEL_OUTPUT_DP) {
Antti Koskipaa75067dd2015-07-10 14:10:55 +03001412 if (dp_iboost) {
1413 iboost = dp_iboost;
1414 } else {
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +02001415 ddi_translations = skl_get_buf_trans_dp(dev_priv, &n_entries);
Ander Conselvan de Oliveirae4d4c052015-11-11 15:15:54 +02001416 iboost = ddi_translations[level].i_boost;
Antti Koskipaa75067dd2015-07-10 14:10:55 +03001417 }
David Weinehallf8896f52015-06-25 11:11:03 +03001418 } else if (type == INTEL_OUTPUT_EDP) {
Antti Koskipaa75067dd2015-07-10 14:10:55 +03001419 if (dp_iboost) {
1420 iboost = dp_iboost;
1421 } else {
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +02001422 ddi_translations = skl_get_buf_trans_edp(dev_priv, &n_entries);
Ville Syrjälä10afa0b2015-12-08 19:59:43 +02001423
1424 if (WARN_ON(port != PORT_A &&
1425 port != PORT_E && n_entries > 9))
1426 n_entries = 9;
1427
Ander Conselvan de Oliveirae4d4c052015-11-11 15:15:54 +02001428 iboost = ddi_translations[level].i_boost;
Antti Koskipaa75067dd2015-07-10 14:10:55 +03001429 }
David Weinehallf8896f52015-06-25 11:11:03 +03001430 } else if (type == INTEL_OUTPUT_HDMI) {
Antti Koskipaa75067dd2015-07-10 14:10:55 +03001431 if (hdmi_iboost) {
1432 iboost = hdmi_iboost;
1433 } else {
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +02001434 ddi_translations = skl_get_buf_trans_hdmi(dev_priv, &n_entries);
Ander Conselvan de Oliveirae4d4c052015-11-11 15:15:54 +02001435 iboost = ddi_translations[level].i_boost;
Antti Koskipaa75067dd2015-07-10 14:10:55 +03001436 }
David Weinehallf8896f52015-06-25 11:11:03 +03001437 } else {
1438 return;
1439 }
1440
1441 /* Make sure that the requested I_boost is valid */
1442 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
1443 DRM_ERROR("Invalid I_boost value %u\n", iboost);
1444 return;
1445 }
1446
Ville Syrjäläa7d8dbc2016-07-12 15:59:28 +03001447 _skl_ddi_set_iboost(dev_priv, port, iboost);
David Weinehallf8896f52015-06-25 11:11:03 +03001448
Ville Syrjäläa7d8dbc2016-07-12 15:59:28 +03001449 if (port == PORT_A && intel_dig_port->max_lanes == 4)
1450 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
David Weinehallf8896f52015-06-25 11:11:03 +03001451}
1452
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +02001453static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
1454 u32 level, enum port port, int type)
Vandana Kannan96fb9f92014-11-18 15:45:27 +05301455{
Vandana Kannan96fb9f92014-11-18 15:45:27 +05301456 const struct bxt_ddi_buf_trans *ddi_translations;
1457 u32 n_entries, i;
1458 uint32_t val;
1459
Jani Nikula06411f02016-03-24 17:50:21 +02001460 if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
Sonika Jindald9d70002015-09-24 10:24:56 +05301461 n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
1462 ddi_translations = bxt_ddi_translations_edp;
Ville Syrjäläcca05022016-06-22 21:57:06 +03001463 } else if (type == INTEL_OUTPUT_DP
Sonika Jindald9d70002015-09-24 10:24:56 +05301464 || type == INTEL_OUTPUT_EDP) {
Vandana Kannan96fb9f92014-11-18 15:45:27 +05301465 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
1466 ddi_translations = bxt_ddi_translations_dp;
1467 } else if (type == INTEL_OUTPUT_HDMI) {
1468 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
1469 ddi_translations = bxt_ddi_translations_hdmi;
1470 } else {
1471 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
1472 type);
1473 return;
1474 }
1475
1476 /* Check if default value has to be used */
1477 if (level >= n_entries ||
1478 (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
1479 for (i = 0; i < n_entries; i++) {
1480 if (ddi_translations[i].default_index) {
1481 level = i;
1482 break;
1483 }
1484 }
1485 }
1486
1487 /*
1488 * While we write to the group register to program all lanes at once we
1489 * can read only lane registers and we pick lanes 0/1 for that.
1490 */
1491 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
1492 val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
1493 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
1494
1495 val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
1496 val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
1497 val |= ddi_translations[level].margin << MARGIN_000_SHIFT |
1498 ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT;
1499 I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
1500
1501 val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
Sonika Jindal9c58a042015-09-24 10:22:54 +05301502 val &= ~SCALE_DCOMP_METHOD;
Vandana Kannan96fb9f92014-11-18 15:45:27 +05301503 if (ddi_translations[level].enable)
Sonika Jindal9c58a042015-09-24 10:22:54 +05301504 val |= SCALE_DCOMP_METHOD;
1505
1506 if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
1507 DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set");
1508
Vandana Kannan96fb9f92014-11-18 15:45:27 +05301509 I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
1510
1511 val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
1512 val &= ~DE_EMPHASIS;
1513 val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT;
1514 I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
1515
1516 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
1517 val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
1518 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
1519}
1520
David Weinehallf8896f52015-06-25 11:11:03 +03001521static uint32_t translate_signal_level(int signal_levels)
1522{
1523 uint32_t level;
1524
1525 switch (signal_levels) {
1526 default:
1527 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n",
1528 signal_levels);
1529 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1530 level = 0;
1531 break;
1532 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1533 level = 1;
1534 break;
1535 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1536 level = 2;
1537 break;
1538 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
1539 level = 3;
1540 break;
1541
1542 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1543 level = 4;
1544 break;
1545 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1546 level = 5;
1547 break;
1548 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1549 level = 6;
1550 break;
1551
1552 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1553 level = 7;
1554 break;
1555 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1556 level = 8;
1557 break;
1558
1559 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1560 level = 9;
1561 break;
1562 }
1563
1564 return level;
1565}
1566
1567uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
1568{
1569 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +02001570 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
David Weinehallf8896f52015-06-25 11:11:03 +03001571 struct intel_encoder *encoder = &dport->base;
1572 uint8_t train_set = intel_dp->train_set[0];
1573 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1574 DP_TRAIN_PRE_EMPHASIS_MASK);
1575 enum port port = dport->port;
1576 uint32_t level;
1577
1578 level = translate_signal_level(signal_levels);
1579
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +02001580 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
Ville Syrjäläa7d8dbc2016-07-12 15:59:28 +03001581 skl_ddi_set_iboost(encoder, level);
Ville Syrjälä78ab0ba2015-12-08 19:59:41 +02001582 else if (IS_BROXTON(dev_priv))
1583 bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
David Weinehallf8896f52015-06-25 11:11:03 +03001584
1585 return DDI_BUF_TRANS_SELECT(level);
1586}
1587
Ville Syrjäläe404ba8d2015-08-17 18:46:20 +03001588void intel_ddi_clk_select(struct intel_encoder *encoder,
1589 const struct intel_crtc_state *pipe_config)
Paulo Zanoni6441ab52012-10-05 12:05:58 -03001590{
Ville Syrjäläe404ba8d2015-08-17 18:46:20 +03001591 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1592 enum port port = intel_ddi_get_encoder_port(encoder);
Paulo Zanoni82a4d9c2012-10-23 18:30:07 -02001593
Ville Syrjäläe404ba8d2015-08-17 18:46:20 +03001594 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
1595 uint32_t dpll = pipe_config->ddi_pll_sel;
Satheeshakrishna Mefa80ad2014-11-13 14:55:19 +00001596 uint32_t val;
1597
Damien Lespiau5416d872014-11-14 17:24:33 +00001598 /* DDI -> PLL mapping */
Satheeshakrishna Mefa80ad2014-11-13 14:55:19 +00001599 val = I915_READ(DPLL_CTRL2);
1600
1601 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
1602 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
1603 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
1604 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
1605
1606 I915_WRITE(DPLL_CTRL2, val);
Damien Lespiau5416d872014-11-14 17:24:33 +00001607
Ville Syrjäläe404ba8d2015-08-17 18:46:20 +03001608 } else if (INTEL_INFO(dev_priv)->gen < 9) {
1609 WARN_ON(pipe_config->ddi_pll_sel == PORT_CLK_SEL_NONE);
1610 I915_WRITE(PORT_CLK_SEL(port), pipe_config->ddi_pll_sel);
Satheeshakrishna Mefa80ad2014-11-13 14:55:19 +00001611 }
Ville Syrjäläe404ba8d2015-08-17 18:46:20 +03001612}
1613
1614static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
1615{
1616 struct drm_encoder *encoder = &intel_encoder->base;
Ville Syrjälä6a7e4f92015-12-08 19:59:44 +02001617 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
Ville Syrjäläe404ba8d2015-08-17 18:46:20 +03001618 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
1619 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1620 int type = intel_encoder->type;
Ville Syrjälä6a7e4f92015-12-08 19:59:44 +02001621
Ville Syrjäläb2ccb822016-05-02 22:08:24 +03001622 if (type == INTEL_OUTPUT_HDMI) {
1623 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1624
1625 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
1626 }
1627
Ville Syrjäläe404ba8d2015-08-17 18:46:20 +03001628 if (type == INTEL_OUTPUT_EDP) {
1629 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1630 intel_edp_panel_on(intel_dp);
1631 }
1632
1633 intel_ddi_clk_select(intel_encoder, crtc->config);
Paulo Zanonic19b0662012-10-15 15:51:41 -03001634
Ville Syrjäläcca05022016-06-22 21:57:06 +03001635 if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
Paulo Zanonic19b0662012-10-15 15:51:41 -03001636 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
Daniel Vetter30cf6db2014-04-24 23:54:58 +02001637
Ville Syrjälä32bdc402016-07-12 15:59:33 +03001638 intel_prepare_dp_ddi_buffers(intel_encoder);
1639
Ville Syrjälä901c2da2015-08-17 18:05:12 +03001640 intel_dp_set_link_params(intel_dp, crtc->config);
1641
Dave Airlie44905a272014-05-02 13:36:43 +10001642 intel_ddi_init_dp_buf_reg(intel_encoder);
Paulo Zanonic19b0662012-10-15 15:51:41 -03001643
1644 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1645 intel_dp_start_link_train(intel_dp);
Ville Syrjälä6a7e4f92015-12-08 19:59:44 +02001646 if (port != PORT_A || INTEL_INFO(dev_priv)->gen >= 9)
Imre Deak3ab9c632013-05-03 12:57:41 +03001647 intel_dp_stop_link_train(intel_dp);
Daniel Vetter30cf6db2014-04-24 23:54:58 +02001648 } else if (type == INTEL_OUTPUT_HDMI) {
1649 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
Ville Syrjälä8d8bb852016-07-12 15:59:30 +03001650 int level = intel_ddi_hdmi_level(dev_priv, port);
1651
Ville Syrjälä32bdc402016-07-12 15:59:33 +03001652 intel_prepare_hdmi_ddi_buffers(intel_encoder);
1653
Ville Syrjälä8d8bb852016-07-12 15:59:30 +03001654 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
1655 skl_ddi_set_iboost(intel_encoder, level);
Ville Syrjälä9f332432016-07-12 15:59:31 +03001656 else if (IS_BROXTON(dev_priv))
1657 bxt_ddi_vswing_sequence(dev_priv, level, port,
1658 INTEL_OUTPUT_HDMI);
Daniel Vetter30cf6db2014-04-24 23:54:58 +02001659
1660 intel_hdmi->set_infoframes(encoder,
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001661 crtc->config->has_hdmi_sink,
1662 &crtc->config->base.adjusted_mode);
Paulo Zanonic19b0662012-10-15 15:51:41 -03001663 }
Paulo Zanoni6441ab52012-10-05 12:05:58 -03001664}
1665
Paulo Zanoni00c09d72012-10-26 19:05:52 -02001666static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
Paulo Zanoni6441ab52012-10-05 12:05:58 -03001667{
1668 struct drm_encoder *encoder = &intel_encoder->base;
Satheeshakrishna Mefa80ad2014-11-13 14:55:19 +00001669 struct drm_device *dev = encoder->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01001670 struct drm_i915_private *dev_priv = to_i915(dev);
Paulo Zanoni6441ab52012-10-05 12:05:58 -03001671 enum port port = intel_ddi_get_encoder_port(intel_encoder);
Paulo Zanoni82a4d9c2012-10-23 18:30:07 -02001672 int type = intel_encoder->type;
Paulo Zanoni2886e932012-10-05 12:06:00 -03001673 uint32_t val;
Paulo Zanonia836bdf2012-10-15 15:51:32 -03001674 bool wait = false;
Paulo Zanoni2886e932012-10-05 12:06:00 -03001675
1676 val = I915_READ(DDI_BUF_CTL(port));
1677 if (val & DDI_BUF_CTL_ENABLE) {
1678 val &= ~DDI_BUF_CTL_ENABLE;
1679 I915_WRITE(DDI_BUF_CTL(port), val);
Paulo Zanonia836bdf2012-10-15 15:51:32 -03001680 wait = true;
Paulo Zanoni2886e932012-10-05 12:06:00 -03001681 }
Paulo Zanoni6441ab52012-10-05 12:05:58 -03001682
Paulo Zanonia836bdf2012-10-15 15:51:32 -03001683 val = I915_READ(DP_TP_CTL(port));
1684 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1685 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1686 I915_WRITE(DP_TP_CTL(port), val);
1687
1688 if (wait)
1689 intel_wait_ddi_buf_idle(dev_priv, port);
1690
Ville Syrjäläcca05022016-06-22 21:57:06 +03001691 if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
Paulo Zanoni82a4d9c2012-10-23 18:30:07 -02001692 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
Jani Nikula76bb80e2013-11-15 15:29:57 +02001693 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
Jani Nikula24f3e092014-03-17 16:43:36 +02001694 intel_edp_panel_vdd_on(intel_dp);
Daniel Vetter4be73782014-01-17 14:39:48 +01001695 intel_edp_panel_off(intel_dp);
Paulo Zanoni82a4d9c2012-10-23 18:30:07 -02001696 }
1697
Rodrigo Vivief11bdb2015-10-28 04:16:45 -07001698 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
Satheeshakrishna Mefa80ad2014-11-13 14:55:19 +00001699 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
1700 DPLL_CTRL2_DDI_CLK_OFF(port)));
Satheeshakrishna M1ab23382014-08-22 09:49:06 +05301701 else if (INTEL_INFO(dev)->gen < 9)
Satheeshakrishna Mefa80ad2014-11-13 14:55:19 +00001702 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
Ville Syrjäläb2ccb822016-05-02 22:08:24 +03001703
1704 if (type == INTEL_OUTPUT_HDMI) {
1705 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1706
1707 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
1708 }
Paulo Zanoni6441ab52012-10-05 12:05:58 -03001709}
1710
Paulo Zanoni00c09d72012-10-26 19:05:52 -02001711static void intel_enable_ddi(struct intel_encoder *intel_encoder)
Eugeni Dodonov72662e12012-05-09 15:37:31 -03001712{
Paulo Zanoni6547fef2012-10-15 15:51:40 -03001713 struct drm_encoder *encoder = &intel_encoder->base;
Wang Xingchao7b9f35a2013-01-22 23:25:25 +08001714 struct drm_crtc *crtc = encoder->crtc;
1715 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Paulo Zanoni6547fef2012-10-15 15:51:40 -03001716 struct drm_device *dev = encoder->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01001717 struct drm_i915_private *dev_priv = to_i915(dev);
Paulo Zanoni6547fef2012-10-15 15:51:40 -03001718 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1719 int type = intel_encoder->type;
Eugeni Dodonov72662e12012-05-09 15:37:31 -03001720
Paulo Zanoni6547fef2012-10-15 15:51:40 -03001721 if (type == INTEL_OUTPUT_HDMI) {
Damien Lespiau876a8cd2012-12-11 18:48:30 +00001722 struct intel_digital_port *intel_dig_port =
1723 enc_to_dig_port(encoder);
1724
Paulo Zanoni6547fef2012-10-15 15:51:40 -03001725 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1726 * are ignored so nothing special needs to be done besides
1727 * enabling the port.
1728 */
Damien Lespiau876a8cd2012-12-11 18:48:30 +00001729 I915_WRITE(DDI_BUF_CTL(port),
Stéphane Marchesinbcf53de2013-07-12 13:54:41 -07001730 intel_dig_port->saved_port_bits |
1731 DDI_BUF_CTL_ENABLE);
Paulo Zanonid6c50ff2012-10-23 18:30:06 -02001732 } else if (type == INTEL_OUTPUT_EDP) {
1733 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1734
Vandana Kannan23f08d82014-11-13 14:55:22 +00001735 if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
Imre Deak3ab9c632013-05-03 12:57:41 +03001736 intel_dp_stop_link_train(intel_dp);
1737
Daniel Vetter4be73782014-01-17 14:39:48 +01001738 intel_edp_backlight_on(intel_dp);
Rodrigo Vivi0bc12bc2014-11-14 08:52:28 -08001739 intel_psr_enable(intel_dp);
Vandana Kannanc3955782015-01-22 15:17:40 +05301740 intel_edp_drrs_enable(intel_dp);
Paulo Zanoni6547fef2012-10-15 15:51:40 -03001741 }
Wang Xingchao7b9f35a2013-01-22 23:25:25 +08001742
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001743 if (intel_crtc->config->has_audio) {
Paulo Zanonid45a0bf2014-05-21 17:29:31 -03001744 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
Jani Nikula69bfe1a2014-10-27 16:26:50 +02001745 intel_audio_codec_enable(intel_encoder);
Wang Xingchao7b9f35a2013-01-22 23:25:25 +08001746 }
Daniel Vetter5ab432e2012-06-30 08:59:56 +02001747}
1748
Paulo Zanoni00c09d72012-10-26 19:05:52 -02001749static void intel_disable_ddi(struct intel_encoder *intel_encoder)
Daniel Vetter5ab432e2012-06-30 08:59:56 +02001750{
Paulo Zanonid6c50ff2012-10-23 18:30:06 -02001751 struct drm_encoder *encoder = &intel_encoder->base;
Wang Xingchao7b9f35a2013-01-22 23:25:25 +08001752 struct drm_crtc *crtc = encoder->crtc;
1753 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Paulo Zanonid6c50ff2012-10-23 18:30:06 -02001754 int type = intel_encoder->type;
Wang Xingchao7b9f35a2013-01-22 23:25:25 +08001755 struct drm_device *dev = encoder->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01001756 struct drm_i915_private *dev_priv = to_i915(dev);
Paulo Zanonid6c50ff2012-10-23 18:30:06 -02001757
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001758 if (intel_crtc->config->has_audio) {
Jani Nikula69bfe1a2014-10-27 16:26:50 +02001759 intel_audio_codec_disable(intel_encoder);
Paulo Zanonid45a0bf2014-05-21 17:29:31 -03001760 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
1761 }
Paulo Zanoni2831d8422013-03-06 20:03:09 -03001762
Paulo Zanonid6c50ff2012-10-23 18:30:06 -02001763 if (type == INTEL_OUTPUT_EDP) {
1764 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1765
Vandana Kannanc3955782015-01-22 15:17:40 +05301766 intel_edp_drrs_disable(intel_dp);
Rodrigo Vivi0bc12bc2014-11-14 08:52:28 -08001767 intel_psr_disable(intel_dp);
Daniel Vetter4be73782014-01-17 14:39:48 +01001768 intel_edp_backlight_off(intel_dp);
Paulo Zanonid6c50ff2012-10-23 18:30:06 -02001769 }
Eugeni Dodonov72662e12012-05-09 15:37:31 -03001770}
Paulo Zanoni79f689a2012-10-05 12:05:52 -03001771
Imre Deak9c8d0b82016-06-13 16:44:34 +03001772bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
1773 enum dpio_phy phy)
Imre Deakbd480062016-04-01 16:02:44 +03001774{
Imre Deake93da0a2016-06-13 16:44:37 +03001775 enum port port;
1776
Imre Deakbd480062016-04-01 16:02:44 +03001777 if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) & GT_DISPLAY_POWER_ON(phy)))
1778 return false;
1779
1780 if ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
1781 (PHY_POWER_GOOD | PHY_RESERVED)) != PHY_POWER_GOOD) {
1782 DRM_DEBUG_DRIVER("DDI PHY %d powered, but power hasn't settled\n",
1783 phy);
1784
1785 return false;
1786 }
1787
1788 if (phy == DPIO_PHY1 &&
1789 !(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE)) {
1790 DRM_DEBUG_DRIVER("DDI PHY 1 powered, but GRC isn't done\n");
1791
1792 return false;
1793 }
1794
1795 if (!(I915_READ(BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) {
1796 DRM_DEBUG_DRIVER("DDI PHY %d powered, but still in reset\n",
1797 phy);
1798
1799 return false;
1800 }
1801
Imre Deake93da0a2016-06-13 16:44:37 +03001802 for_each_port_masked(port,
1803 phy == DPIO_PHY0 ? BIT(PORT_B) | BIT(PORT_C) :
1804 BIT(PORT_A)) {
1805 u32 tmp = I915_READ(BXT_PHY_CTL(port));
1806
1807 if (tmp & BXT_PHY_CMNLANE_POWERDOWN_ACK) {
1808 DRM_DEBUG_DRIVER("DDI PHY %d powered, but common lane "
1809 "for port %c powered down "
1810 "(PHY_CTL %08x)\n",
1811 phy, port_name(port), tmp);
1812
1813 return false;
1814 }
1815 }
1816
Imre Deakbd480062016-04-01 16:02:44 +03001817 return true;
1818}
1819
Imre Deak324513c2016-06-13 16:44:36 +03001820static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy)
Imre Deakadc7f042016-04-04 17:27:10 +03001821{
1822 u32 val = I915_READ(BXT_PORT_REF_DW6(phy));
1823
1824 return (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
1825}
1826
Imre Deak324513c2016-06-13 16:44:36 +03001827static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv,
1828 enum dpio_phy phy)
Imre Deak01a01ef2016-04-21 19:19:21 +03001829{
Chris Wilson058fee92016-06-30 15:32:52 +01001830 if (intel_wait_for_register(dev_priv,
1831 BXT_PORT_REF_DW3(phy),
1832 GRC_DONE, GRC_DONE,
1833 10))
Imre Deak01a01ef2016-04-21 19:19:21 +03001834 DRM_ERROR("timeout waiting for PHY%d GRC\n", phy);
1835}
1836
Imre Deak9c8d0b82016-06-13 16:44:34 +03001837void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
Vandana Kannan5c6706e2014-11-24 13:37:39 +05301838{
Imre Deak95a7a2a2016-06-13 16:44:35 +03001839 u32 val;
Vandana Kannan5c6706e2014-11-24 13:37:39 +05301840
Imre Deak9c8d0b82016-06-13 16:44:34 +03001841 if (bxt_ddi_phy_is_enabled(dev_priv, phy)) {
Imre Deakadc7f042016-04-04 17:27:10 +03001842 /* Still read out the GRC value for state verification */
Imre Deak67856d42016-04-20 20:46:04 +03001843 if (phy == DPIO_PHY0)
Imre Deak324513c2016-06-13 16:44:36 +03001844 dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, phy);
Imre Deakbd480062016-04-01 16:02:44 +03001845
Imre Deak9c8d0b82016-06-13 16:44:34 +03001846 if (bxt_ddi_phy_verify_state(dev_priv, phy)) {
Imre Deak47baf2a2016-04-20 20:46:06 +03001847 DRM_DEBUG_DRIVER("DDI PHY %d already enabled, "
1848 "won't reprogram it\n", phy);
Imre Deakbd480062016-04-01 16:02:44 +03001849
Imre Deak47baf2a2016-04-20 20:46:06 +03001850 return;
1851 }
1852
1853 DRM_DEBUG_DRIVER("DDI PHY %d enabled with invalid state, "
1854 "force reprogramming it\n", phy);
Imre Deak47baf2a2016-04-20 20:46:06 +03001855 }
Imre Deakbd480062016-04-01 16:02:44 +03001856
Vandana Kannan5c6706e2014-11-24 13:37:39 +05301857 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
1858 val |= GT_DISPLAY_POWER_ON(phy);
1859 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
1860
Vandana Kannanb61e7992016-03-31 23:15:54 +05301861 /*
1862 * The PHY registers start out inaccessible and respond to reads with
1863 * all 1s. Eventually they become accessible as they power up, then
1864 * the reserved bit will give the default 0. Poll on the reserved bit
1865 * becoming 0 to find when the PHY is accessible.
1866 * HW team confirmed that the time to reach phypowergood status is
1867 * anywhere between 50 us and 100us.
1868 */
1869 if (wait_for_us(((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
1870 (PHY_RESERVED | PHY_POWER_GOOD)) == PHY_POWER_GOOD), 100)) {
Vandana Kannan5c6706e2014-11-24 13:37:39 +05301871 DRM_ERROR("timeout during PHY%d power on\n", phy);
Vandana Kannanb61e7992016-03-31 23:15:54 +05301872 }
Vandana Kannan5c6706e2014-11-24 13:37:39 +05301873
Vandana Kannan5c6706e2014-11-24 13:37:39 +05301874 /* Program PLL Rcomp code offset */
1875 val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
1876 val &= ~IREF0RC_OFFSET_MASK;
1877 val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
1878 I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
1879
1880 val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
1881 val &= ~IREF1RC_OFFSET_MASK;
1882 val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
1883 I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
1884
1885 /* Program power gating */
1886 val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
1887 val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
1888 SUS_CLK_CONFIG;
1889 I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
1890
1891 if (phy == DPIO_PHY0) {
1892 val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
1893 val |= DW6_OLDO_DYN_PWR_DOWN_EN;
1894 I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
1895 }
1896
1897 val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
1898 val &= ~OCL2_LDOFUSE_PWR_DIS;
1899 /*
1900 * On PHY1 disable power on the second channel, since no port is
1901 * connected there. On PHY0 both channels have a port, so leave it
1902 * enabled.
1903 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
1904 * power down the second channel on PHY0 as well.
Imre Deak28ca6932016-04-01 16:02:34 +03001905 *
1906 * FIXME: Clarify programming of the following, the register is
1907 * read-only with bit 6 fixed at 0 at least in stepping A.
Vandana Kannan5c6706e2014-11-24 13:37:39 +05301908 */
1909 if (phy == DPIO_PHY1)
1910 val |= OCL2_LDOFUSE_PWR_DIS;
1911 I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
1912
1913 if (phy == DPIO_PHY0) {
1914 uint32_t grc_code;
1915 /*
1916 * PHY0 isn't connected to an RCOMP resistor so copy over
1917 * the corresponding calibrated value from PHY1, and disable
1918 * the automatic calibration on PHY0.
1919 */
Imre Deak324513c2016-06-13 16:44:36 +03001920 val = dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, DPIO_PHY1);
Vandana Kannan5c6706e2014-11-24 13:37:39 +05301921 grc_code = val << GRC_CODE_FAST_SHIFT |
1922 val << GRC_CODE_SLOW_SHIFT |
1923 val;
1924 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
1925
1926 val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
1927 val |= GRC_DIS | GRC_RDY_OVRD;
1928 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
1929 }
1930
1931 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
1932 val |= COMMON_RESET_DIS;
1933 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
Imre Deake4c49e02016-06-13 16:44:32 +03001934
1935 if (phy == DPIO_PHY1)
Imre Deak324513c2016-06-13 16:44:36 +03001936 bxt_phy_wait_grc_done(dev_priv, DPIO_PHY1);
Vandana Kannan5c6706e2014-11-24 13:37:39 +05301937}
1938
Imre Deak9c8d0b82016-06-13 16:44:34 +03001939void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)
Vandana Kannan5c6706e2014-11-24 13:37:39 +05301940{
1941 uint32_t val;
1942
1943 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
1944 val &= ~COMMON_RESET_DIS;
1945 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
Imre Deakd7d33fd2016-04-01 16:02:41 +03001946
1947 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
1948 val &= ~GT_DISPLAY_POWER_ON(phy);
1949 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
Vandana Kannan5c6706e2014-11-24 13:37:39 +05301950}
1951
Imre Deakadc7f042016-04-04 17:27:10 +03001952static bool __printf(6, 7)
1953__phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1954 i915_reg_t reg, u32 mask, u32 expected,
1955 const char *reg_fmt, ...)
1956{
1957 struct va_format vaf;
1958 va_list args;
1959 u32 val;
1960
1961 val = I915_READ(reg);
1962 if ((val & mask) == expected)
1963 return true;
1964
1965 va_start(args, reg_fmt);
1966 vaf.fmt = reg_fmt;
1967 vaf.va = &args;
1968
1969 DRM_DEBUG_DRIVER("DDI PHY %d reg %pV [%08x] state mismatch: "
1970 "current %08x, expected %08x (mask %08x)\n",
1971 phy, &vaf, reg.reg, val, (val & ~mask) | expected,
1972 mask);
1973
1974 va_end(args);
1975
1976 return false;
1977}
1978
Imre Deak9c8d0b82016-06-13 16:44:34 +03001979bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
1980 enum dpio_phy phy)
Imre Deakadc7f042016-04-04 17:27:10 +03001981{
Imre Deakadc7f042016-04-04 17:27:10 +03001982 uint32_t mask;
1983 bool ok;
1984
1985#define _CHK(reg, mask, exp, fmt, ...) \
1986 __phy_reg_verify_state(dev_priv, phy, reg, mask, exp, fmt, \
1987 ## __VA_ARGS__)
1988
Imre Deak9c8d0b82016-06-13 16:44:34 +03001989 if (!bxt_ddi_phy_is_enabled(dev_priv, phy))
Imre Deakadc7f042016-04-04 17:27:10 +03001990 return false;
1991
1992 ok = true;
1993
Imre Deakadc7f042016-04-04 17:27:10 +03001994 /* PLL Rcomp code offset */
1995 ok &= _CHK(BXT_PORT_CL1CM_DW9(phy),
1996 IREF0RC_OFFSET_MASK, 0xe4 << IREF0RC_OFFSET_SHIFT,
1997 "BXT_PORT_CL1CM_DW9(%d)", phy);
1998 ok &= _CHK(BXT_PORT_CL1CM_DW10(phy),
1999 IREF1RC_OFFSET_MASK, 0xe4 << IREF1RC_OFFSET_SHIFT,
2000 "BXT_PORT_CL1CM_DW10(%d)", phy);
2001
2002 /* Power gating */
2003 mask = OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG;
2004 ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask,
2005 "BXT_PORT_CL1CM_DW28(%d)", phy);
2006
2007 if (phy == DPIO_PHY0)
2008 ok &= _CHK(BXT_PORT_CL2CM_DW6_BC,
2009 DW6_OLDO_DYN_PWR_DOWN_EN, DW6_OLDO_DYN_PWR_DOWN_EN,
2010 "BXT_PORT_CL2CM_DW6_BC");
2011
2012 /*
2013 * TODO: Verify BXT_PORT_CL1CM_DW30 bit OCL2_LDOFUSE_PWR_DIS,
2014 * at least on stepping A this bit is read-only and fixed at 0.
2015 */
2016
2017 if (phy == DPIO_PHY0) {
2018 u32 grc_code = dev_priv->bxt_phy_grc;
2019
2020 grc_code = grc_code << GRC_CODE_FAST_SHIFT |
2021 grc_code << GRC_CODE_SLOW_SHIFT |
2022 grc_code;
2023 mask = GRC_CODE_FAST_MASK | GRC_CODE_SLOW_MASK |
2024 GRC_CODE_NOM_MASK;
2025 ok &= _CHK(BXT_PORT_REF_DW6(DPIO_PHY0), mask, grc_code,
2026 "BXT_PORT_REF_DW6(%d)", DPIO_PHY0);
2027
2028 mask = GRC_DIS | GRC_RDY_OVRD;
2029 ok &= _CHK(BXT_PORT_REF_DW8(DPIO_PHY0), mask, mask,
2030 "BXT_PORT_REF_DW8(%d)", DPIO_PHY0);
2031 }
2032
2033 return ok;
2034#undef _CHK
2035}
2036
Imre Deak95a7a2a2016-06-13 16:44:35 +03002037static uint8_t
2038bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder,
2039 struct intel_crtc_state *pipe_config)
2040{
2041 switch (pipe_config->lane_count) {
2042 case 1:
2043 return 0;
2044 case 2:
2045 return BIT(2) | BIT(0);
2046 case 4:
2047 return BIT(3) | BIT(2) | BIT(0);
2048 default:
2049 MISSING_CASE(pipe_config->lane_count);
2050
2051 return 0;
2052 }
2053}
2054
2055static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder)
2056{
2057 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2058 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2059 enum port port = dport->port;
2060 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2061 int lane;
2062
2063 for (lane = 0; lane < 4; lane++) {
2064 u32 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
2065
2066 /*
2067 * Note that on CHV this flag is called UPAR, but has
2068 * the same function.
2069 */
2070 val &= ~LATENCY_OPTIM;
2071 if (intel_crtc->config->lane_lat_optim_mask & BIT(lane))
2072 val |= LATENCY_OPTIM;
2073
2074 I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
2075 }
2076}
2077
2078static uint8_t
2079bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder)
2080{
2081 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2082 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2083 enum port port = dport->port;
2084 int lane;
2085 uint8_t mask;
2086
2087 mask = 0;
2088 for (lane = 0; lane < 4; lane++) {
2089 u32 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
2090
2091 if (val & LATENCY_OPTIM)
2092 mask |= BIT(lane);
2093 }
2094
2095 return mask;
2096}
2097
Ander Conselvan de Oliveiraad642172015-10-23 13:01:49 +03002098void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
Paulo Zanonic19b0662012-10-15 15:51:41 -03002099{
Ander Conselvan de Oliveiraad642172015-10-23 13:01:49 +03002100 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2101 struct drm_i915_private *dev_priv =
2102 to_i915(intel_dig_port->base.base.dev);
Paulo Zanoni174edf12012-10-26 19:05:50 -02002103 enum port port = intel_dig_port->port;
Paulo Zanonic19b0662012-10-15 15:51:41 -03002104 uint32_t val;
Syam Sidhardhanf3e227d2013-02-25 04:05:38 +05302105 bool wait = false;
Paulo Zanonic19b0662012-10-15 15:51:41 -03002106
2107 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
2108 val = I915_READ(DDI_BUF_CTL(port));
2109 if (val & DDI_BUF_CTL_ENABLE) {
2110 val &= ~DDI_BUF_CTL_ENABLE;
2111 I915_WRITE(DDI_BUF_CTL(port), val);
2112 wait = true;
2113 }
2114
2115 val = I915_READ(DP_TP_CTL(port));
2116 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2117 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2118 I915_WRITE(DP_TP_CTL(port), val);
2119 POSTING_READ(DP_TP_CTL(port));
2120
2121 if (wait)
2122 intel_wait_ddi_buf_idle(dev_priv, port);
2123 }
2124
Dave Airlie0e32b392014-05-02 14:02:48 +10002125 val = DP_TP_CTL_ENABLE |
Paulo Zanonic19b0662012-10-15 15:51:41 -03002126 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
Ville Syrjälä64ee2fd2016-07-28 17:50:39 +03002127 if (intel_dp->link_mst)
Dave Airlie0e32b392014-05-02 14:02:48 +10002128 val |= DP_TP_CTL_MODE_MST;
2129 else {
2130 val |= DP_TP_CTL_MODE_SST;
2131 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2132 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
2133 }
Paulo Zanonic19b0662012-10-15 15:51:41 -03002134 I915_WRITE(DP_TP_CTL(port), val);
2135 POSTING_READ(DP_TP_CTL(port));
2136
2137 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
2138 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
2139 POSTING_READ(DDI_BUF_CTL(port));
2140
2141 udelay(600);
2142}
Paulo Zanoni00c09d72012-10-26 19:05:52 -02002143
Paulo Zanoni1ad960f2012-11-01 21:05:05 -02002144void intel_ddi_fdi_disable(struct drm_crtc *crtc)
2145{
Chris Wilsonfac5e232016-07-04 11:34:36 +01002146 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
Paulo Zanoni1ad960f2012-11-01 21:05:05 -02002147 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
2148 uint32_t val;
2149
Ville Syrjälä5b421c52016-03-01 16:16:23 +02002150 /*
2151 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
2152 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
2153 * step 13 is the correct place for it. Step 18 is where it was
2154 * originally before the BUN.
2155 */
Ville Syrjäläeede3b52015-09-18 20:03:30 +03002156 val = I915_READ(FDI_RX_CTL(PIPE_A));
Paulo Zanoni1ad960f2012-11-01 21:05:05 -02002157 val &= ~FDI_RX_ENABLE;
Ville Syrjäläeede3b52015-09-18 20:03:30 +03002158 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
Paulo Zanoni1ad960f2012-11-01 21:05:05 -02002159
Ville Syrjälä5b421c52016-03-01 16:16:23 +02002160 intel_ddi_post_disable(intel_encoder);
2161
Ville Syrjäläeede3b52015-09-18 20:03:30 +03002162 val = I915_READ(FDI_RX_MISC(PIPE_A));
Paulo Zanoni1ad960f2012-11-01 21:05:05 -02002163 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
2164 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
Ville Syrjäläeede3b52015-09-18 20:03:30 +03002165 I915_WRITE(FDI_RX_MISC(PIPE_A), val);
Paulo Zanoni1ad960f2012-11-01 21:05:05 -02002166
Ville Syrjäläeede3b52015-09-18 20:03:30 +03002167 val = I915_READ(FDI_RX_CTL(PIPE_A));
Paulo Zanoni1ad960f2012-11-01 21:05:05 -02002168 val &= ~FDI_PCDCLK;
Ville Syrjäläeede3b52015-09-18 20:03:30 +03002169 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
Paulo Zanoni1ad960f2012-11-01 21:05:05 -02002170
Ville Syrjäläeede3b52015-09-18 20:03:30 +03002171 val = I915_READ(FDI_RX_CTL(PIPE_A));
Paulo Zanoni1ad960f2012-11-01 21:05:05 -02002172 val &= ~FDI_RX_PLL_ENABLE;
Ville Syrjäläeede3b52015-09-18 20:03:30 +03002173 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
Paulo Zanoni1ad960f2012-11-01 21:05:05 -02002174}
2175
Ville Syrjälä6801c182013-09-24 14:24:05 +03002176void intel_ddi_get_config(struct intel_encoder *encoder,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02002177 struct intel_crtc_state *pipe_config)
Jesse Barnes045ac3b2013-05-14 17:08:26 -07002178{
Chris Wilsonfac5e232016-07-04 11:34:36 +01002179 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
Jesse Barnes045ac3b2013-05-14 17:08:26 -07002180 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
Ander Conselvan de Oliveira0cb09a92015-01-30 12:17:23 +02002181 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
Daniel Vetterbbd440f2014-11-20 22:33:59 +01002182 struct intel_hdmi *intel_hdmi;
Jesse Barnes045ac3b2013-05-14 17:08:26 -07002183 u32 temp, flags = 0;
2184
Jani Nikula4d1de972016-03-18 17:05:42 +02002185 /* XXX: DSI transcoder paranoia */
2186 if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
2187 return;
2188
Jesse Barnes045ac3b2013-05-14 17:08:26 -07002189 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2190 if (temp & TRANS_DDI_PHSYNC)
2191 flags |= DRM_MODE_FLAG_PHSYNC;
2192 else
2193 flags |= DRM_MODE_FLAG_NHSYNC;
2194 if (temp & TRANS_DDI_PVSYNC)
2195 flags |= DRM_MODE_FLAG_PVSYNC;
2196 else
2197 flags |= DRM_MODE_FLAG_NVSYNC;
2198
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +02002199 pipe_config->base.adjusted_mode.flags |= flags;
Ville Syrjälä42571ae2013-09-06 23:29:00 +03002200
2201 switch (temp & TRANS_DDI_BPC_MASK) {
2202 case TRANS_DDI_BPC_6:
2203 pipe_config->pipe_bpp = 18;
2204 break;
2205 case TRANS_DDI_BPC_8:
2206 pipe_config->pipe_bpp = 24;
2207 break;
2208 case TRANS_DDI_BPC_10:
2209 pipe_config->pipe_bpp = 30;
2210 break;
2211 case TRANS_DDI_BPC_12:
2212 pipe_config->pipe_bpp = 36;
2213 break;
2214 default:
2215 break;
2216 }
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03002217
2218 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
2219 case TRANS_DDI_MODE_SELECT_HDMI:
Daniel Vetter6897b4b2014-04-24 23:54:47 +02002220 pipe_config->has_hdmi_sink = true;
Daniel Vetterbbd440f2014-11-20 22:33:59 +01002221 intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2222
Ville Syrjäläcda0aaa2015-11-26 18:27:07 +02002223 if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
Daniel Vetterbbd440f2014-11-20 22:33:59 +01002224 pipe_config->has_infoframe = true;
Ander Conselvan de Oliveirad4d62792016-04-27 15:44:16 +03002225 /* fall through */
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03002226 case TRANS_DDI_MODE_SELECT_DVI:
Ander Conselvan de Oliveirad4d62792016-04-27 15:44:16 +03002227 pipe_config->lane_count = 4;
2228 break;
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03002229 case TRANS_DDI_MODE_SELECT_FDI:
2230 break;
2231 case TRANS_DDI_MODE_SELECT_DP_SST:
2232 case TRANS_DDI_MODE_SELECT_DP_MST:
Ville Syrjälä90a6b7b2015-07-06 16:39:15 +03002233 pipe_config->lane_count =
2234 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03002235 intel_dp_get_m_n(intel_crtc, pipe_config);
2236 break;
2237 default:
2238 break;
2239 }
Daniel Vetter10214422013-11-18 07:38:16 +01002240
Lyude5a8f97e2016-05-03 11:01:32 -04002241 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
2242 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
2243 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
2244 pipe_config->has_audio = true;
2245 }
Daniel Vetter9ed109a2014-04-24 23:54:52 +02002246
Jani Nikula6aa23e62016-03-24 17:50:20 +02002247 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
2248 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
Daniel Vetter10214422013-11-18 07:38:16 +01002249 /*
2250 * This is a big fat ugly hack.
2251 *
2252 * Some machines in UEFI boot mode provide us a VBT that has 18
2253 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2254 * unknown we fail to light up. Yet the same BIOS boots up with
2255 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2256 * max, not what it tells us to use.
2257 *
2258 * Note: This will still be broken if the eDP panel is not lit
2259 * up by the BIOS, and thus we can't get the mode at module
2260 * load.
2261 */
2262 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
Jani Nikula6aa23e62016-03-24 17:50:20 +02002263 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2264 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
Daniel Vetter10214422013-11-18 07:38:16 +01002265 }
Jesse Barnes11578552014-01-21 12:42:10 -08002266
Damien Lespiau22606a12014-12-12 14:26:57 +00002267 intel_ddi_clock_get(encoder, pipe_config);
Imre Deak95a7a2a2016-06-13 16:44:35 +03002268
2269 if (IS_BROXTON(dev_priv))
2270 pipe_config->lane_lat_optim_mask =
2271 bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
Jesse Barnes045ac3b2013-05-14 17:08:26 -07002272}
2273
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01002274static bool intel_ddi_compute_config(struct intel_encoder *encoder,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02002275 struct intel_crtc_state *pipe_config)
Paulo Zanoni00c09d72012-10-26 19:05:52 -02002276{
Chris Wilsonfac5e232016-07-04 11:34:36 +01002277 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01002278 int type = encoder->type;
Daniel Vettereccb1402013-05-22 00:50:22 +02002279 int port = intel_ddi_get_encoder_port(encoder);
Imre Deak95a7a2a2016-06-13 16:44:35 +03002280 int ret;
Paulo Zanoni00c09d72012-10-26 19:05:52 -02002281
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01002282 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
Paulo Zanoni00c09d72012-10-26 19:05:52 -02002283
Daniel Vettereccb1402013-05-22 00:50:22 +02002284 if (port == PORT_A)
2285 pipe_config->cpu_transcoder = TRANSCODER_EDP;
2286
Paulo Zanoni00c09d72012-10-26 19:05:52 -02002287 if (type == INTEL_OUTPUT_HDMI)
Imre Deak95a7a2a2016-06-13 16:44:35 +03002288 ret = intel_hdmi_compute_config(encoder, pipe_config);
Paulo Zanoni00c09d72012-10-26 19:05:52 -02002289 else
Imre Deak95a7a2a2016-06-13 16:44:35 +03002290 ret = intel_dp_compute_config(encoder, pipe_config);
2291
2292 if (IS_BROXTON(dev_priv) && ret)
2293 pipe_config->lane_lat_optim_mask =
2294 bxt_ddi_phy_calc_lane_lat_optim_mask(encoder,
2295 pipe_config);
2296
2297 return ret;
2298
Paulo Zanoni00c09d72012-10-26 19:05:52 -02002299}
2300
2301static const struct drm_encoder_funcs intel_ddi_funcs = {
Imre Deakbf93ba62016-04-18 10:04:21 +03002302 .reset = intel_dp_encoder_reset,
2303 .destroy = intel_dp_encoder_destroy,
Paulo Zanoni00c09d72012-10-26 19:05:52 -02002304};
2305
Paulo Zanoni4a28ae52013-10-09 13:52:36 -03002306static struct intel_connector *
2307intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
2308{
2309 struct intel_connector *connector;
2310 enum port port = intel_dig_port->port;
2311
Ander Conselvan de Oliveira9bdbd0b2015-04-10 10:59:10 +03002312 connector = intel_connector_alloc();
Paulo Zanoni4a28ae52013-10-09 13:52:36 -03002313 if (!connector)
2314 return NULL;
2315
2316 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
2317 if (!intel_dp_init_connector(intel_dig_port, connector)) {
2318 kfree(connector);
2319 return NULL;
2320 }
2321
2322 return connector;
2323}
2324
2325static struct intel_connector *
2326intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
2327{
2328 struct intel_connector *connector;
2329 enum port port = intel_dig_port->port;
2330
Ander Conselvan de Oliveira9bdbd0b2015-04-10 10:59:10 +03002331 connector = intel_connector_alloc();
Paulo Zanoni4a28ae52013-10-09 13:52:36 -03002332 if (!connector)
2333 return NULL;
2334
2335 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
2336 intel_hdmi_init_connector(intel_dig_port, connector);
2337
2338 return connector;
2339}
2340
Paulo Zanoni00c09d72012-10-26 19:05:52 -02002341void intel_ddi_init(struct drm_device *dev, enum port port)
2342{
Chris Wilsonfac5e232016-07-04 11:34:36 +01002343 struct drm_i915_private *dev_priv = to_i915(dev);
Paulo Zanoni00c09d72012-10-26 19:05:52 -02002344 struct intel_digital_port *intel_dig_port;
2345 struct intel_encoder *intel_encoder;
2346 struct drm_encoder *encoder;
Paulo Zanoni311a2092013-09-12 17:12:18 -03002347 bool init_hdmi, init_dp;
Ville Syrjälä10e7bec2015-12-08 19:59:37 +02002348 int max_lanes;
2349
2350 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) {
2351 switch (port) {
2352 case PORT_A:
2353 max_lanes = 4;
2354 break;
2355 case PORT_E:
2356 max_lanes = 0;
2357 break;
2358 default:
2359 max_lanes = 4;
2360 break;
2361 }
2362 } else {
2363 switch (port) {
2364 case PORT_A:
2365 max_lanes = 2;
2366 break;
2367 case PORT_E:
2368 max_lanes = 2;
2369 break;
2370 default:
2371 max_lanes = 4;
2372 break;
2373 }
2374 }
Paulo Zanoni311a2092013-09-12 17:12:18 -03002375
2376 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
2377 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
2378 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
2379 if (!init_dp && !init_hdmi) {
Rodrigo Vivi500ea702015-08-07 17:01:16 -07002380 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
Paulo Zanoni311a2092013-09-12 17:12:18 -03002381 port_name(port));
Rodrigo Vivi500ea702015-08-07 17:01:16 -07002382 return;
Paulo Zanoni311a2092013-09-12 17:12:18 -03002383 }
Paulo Zanoni00c09d72012-10-26 19:05:52 -02002384
Daniel Vetterb14c5672013-09-19 12:18:32 +02002385 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
Paulo Zanoni00c09d72012-10-26 19:05:52 -02002386 if (!intel_dig_port)
2387 return;
2388
Paulo Zanoni00c09d72012-10-26 19:05:52 -02002389 intel_encoder = &intel_dig_port->base;
2390 encoder = &intel_encoder->base;
2391
2392 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
Ville Syrjälä580d8ed2016-05-27 20:59:24 +03002393 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
Paulo Zanoni00c09d72012-10-26 19:05:52 -02002394
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01002395 intel_encoder->compute_config = intel_ddi_compute_config;
Paulo Zanoni00c09d72012-10-26 19:05:52 -02002396 intel_encoder->enable = intel_enable_ddi;
Imre Deak95a7a2a2016-06-13 16:44:35 +03002397 if (IS_BROXTON(dev_priv))
2398 intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
Paulo Zanoni00c09d72012-10-26 19:05:52 -02002399 intel_encoder->pre_enable = intel_ddi_pre_enable;
2400 intel_encoder->disable = intel_disable_ddi;
2401 intel_encoder->post_disable = intel_ddi_post_disable;
2402 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
Jesse Barnes045ac3b2013-05-14 17:08:26 -07002403 intel_encoder->get_config = intel_ddi_get_config;
Imre Deakbf93ba62016-04-18 10:04:21 +03002404 intel_encoder->suspend = intel_dp_encoder_suspend;
Paulo Zanoni00c09d72012-10-26 19:05:52 -02002405
2406 intel_dig_port->port = port;
Stéphane Marchesinbcf53de2013-07-12 13:54:41 -07002407 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
2408 (DDI_BUF_PORT_REVERSAL |
2409 DDI_A_4_LANES);
Paulo Zanoni00c09d72012-10-26 19:05:52 -02002410
Matt Roper6c566dc2015-11-05 14:53:32 -08002411 /*
2412 * Bspec says that DDI_A_4_LANES is the only supported configuration
2413 * for Broxton. Yet some BIOS fail to set this bit on port A if eDP
2414 * wasn't lit up at boot. Force this bit on in our internal
2415 * configuration so that we use the proper lane count for our
2416 * calculations.
2417 */
2418 if (IS_BROXTON(dev) && port == PORT_A) {
2419 if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
2420 DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
2421 intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
Matt Ropered8d60f2016-01-28 15:09:37 -08002422 max_lanes = 4;
Matt Roper6c566dc2015-11-05 14:53:32 -08002423 }
2424 }
2425
Matt Ropered8d60f2016-01-28 15:09:37 -08002426 intel_dig_port->max_lanes = max_lanes;
2427
Paulo Zanoni00c09d72012-10-26 19:05:52 -02002428 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
Chris Wilsonf68d6972014-08-04 07:15:09 +01002429 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
Ville Syrjäläbc079e82014-03-03 16:15:28 +02002430 intel_encoder->cloneable = 0;
Paulo Zanoni00c09d72012-10-26 19:05:52 -02002431
Chris Wilsonf68d6972014-08-04 07:15:09 +01002432 if (init_dp) {
2433 if (!intel_ddi_init_dp_connector(intel_dig_port))
2434 goto err;
Dave Airlie13cf5502014-06-18 11:29:35 +10002435
Chris Wilsonf68d6972014-08-04 07:15:09 +01002436 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
Sonika Jindalcf1d5882015-08-10 10:35:36 +05302437 /*
2438 * On BXT A0/A1, sw needs to activate DDIA HPD logic and
2439 * interrupts to check the external panel connection.
2440 */
Jani Nikulae87a0052015-10-20 15:22:02 +03002441 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) && port == PORT_B)
Sonika Jindalcf1d5882015-08-10 10:35:36 +05302442 dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port;
2443 else
2444 dev_priv->hotplug.irq_port[port] = intel_dig_port;
Chris Wilsonf68d6972014-08-04 07:15:09 +01002445 }
Daniel Vetter21a8e6a2013-04-10 23:28:35 +02002446
Paulo Zanoni311a2092013-09-12 17:12:18 -03002447 /* In theory we don't need the encoder->type check, but leave it just in
2448 * case we have some really bad VBTs... */
Chris Wilsonf68d6972014-08-04 07:15:09 +01002449 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
2450 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
2451 goto err;
Daniel Vetter21a8e6a2013-04-10 23:28:35 +02002452 }
Chris Wilsonf68d6972014-08-04 07:15:09 +01002453
2454 return;
2455
2456err:
2457 drm_encoder_cleanup(encoder);
2458 kfree(intel_dig_port);
Paulo Zanoni00c09d72012-10-26 19:05:52 -02002459}