blob: 01130e93126deb087ccc0da3cad9bf18256eea00 [file] [log] [blame]
David Daney5b3b1682009-01-08 16:46:40 -08001/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004-2007 Cavium Networks
Ralf Baechlef65aad42012-10-17 00:39:09 +02007 * Copyright (C) 2008, 2009 Wind River Systems
8 * written by Ralf Baechle <ralf@linux-mips.org>
David Daney5b3b1682009-01-08 16:46:40 -08009 */
Ralf Baechle39205752013-06-13 01:29:24 +020010#include <linux/compiler.h>
Aaro Koskinend8b74272013-07-25 20:26:48 +030011#include <linux/vmalloc.h>
David Daney5b3b1682009-01-08 16:46:40 -080012#include <linux/init.h>
Ralf Baechlef65aad42012-10-17 00:39:09 +020013#include <linux/kernel.h>
David Daney5b3b1682009-01-08 16:46:40 -080014#include <linux/console.h>
15#include <linux/delay.h>
Paul Gortmakerf9ded562012-02-28 19:24:46 -050016#include <linux/export.h>
David Daney5b3b1682009-01-08 16:46:40 -080017#include <linux/interrupt.h>
18#include <linux/io.h>
David Daney5b3b1682009-01-08 16:46:40 -080019#include <linux/serial.h>
Ralf Baechle631330f2009-06-19 14:05:26 +010020#include <linux/smp.h>
David Daney5b3b1682009-01-08 16:46:40 -080021#include <linux/types.h>
22#include <linux/string.h> /* for memset */
David Daney5b3b1682009-01-08 16:46:40 -080023#include <linux/tty.h>
24#include <linux/time.h>
25#include <linux/platform_device.h>
26#include <linux/serial_core.h>
27#include <linux/serial_8250.h>
David Daney7ed18152012-07-05 18:12:38 +020028#include <linux/of_fdt.h>
29#include <linux/libfdt.h>
Ralf Baechleabe77f92012-10-25 16:23:31 +020030#include <linux/kexec.h>
David Daney5b3b1682009-01-08 16:46:40 -080031
32#include <asm/processor.h>
33#include <asm/reboot.h>
34#include <asm/smp-ops.h>
David Daney5b3b1682009-01-08 16:46:40 -080035#include <asm/irq_cpu.h>
36#include <asm/mipsregs.h>
37#include <asm/bootinfo.h>
38#include <asm/sections.h>
39#include <asm/time.h>
40
41#include <asm/octeon/octeon.h>
David Daney2b5987a2010-08-04 14:53:57 -070042#include <asm/octeon/pci-octeon.h>
David Daneye195aa32010-10-07 16:03:49 -070043#include <asm/octeon/cvmx-mio-defs.h>
Chandrakala Chavvaac6d9b32015-01-15 16:11:17 +030044#include <asm/octeon/cvmx-rst-defs.h>
David Daney5b3b1682009-01-08 16:46:40 -080045
David Daney5b3b1682009-01-08 16:46:40 -080046extern struct plat_smp_ops octeon_smp_ops;
47
48#ifdef CONFIG_PCI
49extern void pci_console_init(const char *arg);
50#endif
51
David Daney5b3b1682009-01-08 16:46:40 -080052static unsigned long long MAX_MEMORY = 512ull << 20;
53
David Daney24d4e7f62015-03-05 17:31:29 +030054DEFINE_SEMAPHORE(octeon_bootbus_sem);
55EXPORT_SYMBOL(octeon_bootbus_sem);
56
David Daney5b3b1682009-01-08 16:46:40 -080057struct octeon_boot_descriptor *octeon_boot_desc_ptr;
58
59struct cvmx_bootinfo *octeon_bootinfo;
60EXPORT_SYMBOL(octeon_bootinfo);
61
Ralf Baechleabe77f92012-10-25 16:23:31 +020062static unsigned long long RESERVE_LOW_MEM = 0ull;
63#ifdef CONFIG_KEXEC
64#ifdef CONFIG_SMP
65/*
66 * Wait for relocation code is prepared and send
67 * secondary CPUs to spin until kernel is relocated.
68 */
69static void octeon_kexec_smp_down(void *ignored)
70{
71 int cpu = smp_processor_id();
72
73 local_irq_disable();
74 set_cpu_online(cpu, false);
75 while (!atomic_read(&kexec_ready_to_reboot))
76 cpu_relax();
77
78 asm volatile (
79 " sync \n"
80 " synci ($0) \n");
81
82 relocated_kexec_smp_wait(NULL);
83}
84#endif
85
86#define OCTEON_DDR0_BASE (0x0ULL)
87#define OCTEON_DDR0_SIZE (0x010000000ULL)
88#define OCTEON_DDR1_BASE (0x410000000ULL)
89#define OCTEON_DDR1_SIZE (0x010000000ULL)
90#define OCTEON_DDR2_BASE (0x020000000ULL)
91#define OCTEON_DDR2_SIZE (0x3e0000000ULL)
92#define OCTEON_MAX_PHY_MEM_SIZE (16*1024*1024*1024ULL)
93
94static struct kimage *kimage_ptr;
95
96static void kexec_bootmem_init(uint64_t mem_size, uint32_t low_reserved_bytes)
97{
98 int64_t addr;
99 struct cvmx_bootmem_desc *bootmem_desc;
100
101 bootmem_desc = cvmx_bootmem_get_desc();
102
103 if (mem_size > OCTEON_MAX_PHY_MEM_SIZE) {
104 mem_size = OCTEON_MAX_PHY_MEM_SIZE;
105 pr_err("Error: requested memory too large,"
106 "truncating to maximum size\n");
107 }
108
109 bootmem_desc->major_version = CVMX_BOOTMEM_DESC_MAJ_VER;
110 bootmem_desc->minor_version = CVMX_BOOTMEM_DESC_MIN_VER;
111
112 addr = (OCTEON_DDR0_BASE + RESERVE_LOW_MEM + low_reserved_bytes);
113 bootmem_desc->head_addr = 0;
114
115 if (mem_size <= OCTEON_DDR0_SIZE) {
116 __cvmx_bootmem_phy_free(addr,
117 mem_size - RESERVE_LOW_MEM -
118 low_reserved_bytes, 0);
119 return;
120 }
121
122 __cvmx_bootmem_phy_free(addr,
123 OCTEON_DDR0_SIZE - RESERVE_LOW_MEM -
124 low_reserved_bytes, 0);
125
126 mem_size -= OCTEON_DDR0_SIZE;
127
128 if (mem_size > OCTEON_DDR1_SIZE) {
129 __cvmx_bootmem_phy_free(OCTEON_DDR1_BASE, OCTEON_DDR1_SIZE, 0);
130 __cvmx_bootmem_phy_free(OCTEON_DDR2_BASE,
131 mem_size - OCTEON_DDR1_SIZE, 0);
132 } else
133 __cvmx_bootmem_phy_free(OCTEON_DDR1_BASE, mem_size, 0);
134}
135
136static int octeon_kexec_prepare(struct kimage *image)
137{
138 int i;
139 char *bootloader = "kexec";
140
141 octeon_boot_desc_ptr->argc = 0;
142 for (i = 0; i < image->nr_segments; i++) {
143 if (!strncmp(bootloader, (char *)image->segment[i].buf,
144 strlen(bootloader))) {
145 /*
146 * convert command line string to array
147 * of parameters (as bootloader does).
148 */
149 int argc = 0, offt;
150 char *str = (char *)image->segment[i].buf;
151 char *ptr = strchr(str, ' ');
152 while (ptr && (OCTEON_ARGV_MAX_ARGS > argc)) {
153 *ptr = '\0';
154 if (ptr[1] != ' ') {
155 offt = (int)(ptr - str + 1);
156 octeon_boot_desc_ptr->argv[argc] =
157 image->segment[i].mem + offt;
158 argc++;
159 }
160 ptr = strchr(ptr + 1, ' ');
161 }
162 octeon_boot_desc_ptr->argc = argc;
163 break;
164 }
165 }
166
167 /*
168 * Information about segments will be needed during pre-boot memory
169 * initialization.
170 */
171 kimage_ptr = image;
172 return 0;
173}
174
175static void octeon_generic_shutdown(void)
176{
EunBong Songed1197f2013-03-24 22:18:35 +0000177 int i;
178#ifdef CONFIG_SMP
179 int cpu;
180#endif
Ralf Baechleabe77f92012-10-25 16:23:31 +0200181 struct cvmx_bootmem_desc *bootmem_desc;
182 void *named_block_array_ptr;
183
184 bootmem_desc = cvmx_bootmem_get_desc();
185 named_block_array_ptr =
186 cvmx_phys_to_ptr(bootmem_desc->named_block_array_addr);
187
188#ifdef CONFIG_SMP
189 /* disable watchdogs */
190 for_each_online_cpu(cpu)
191 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0);
192#else
193 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);
194#endif
195 if (kimage_ptr != kexec_crash_image) {
196 memset(named_block_array_ptr,
197 0x0,
198 CVMX_BOOTMEM_NUM_NAMED_BLOCKS *
199 sizeof(struct cvmx_bootmem_named_block_desc));
200 /*
201 * Mark all memory (except low 0x100000 bytes) as free.
202 * It is the same thing that bootloader does.
203 */
204 kexec_bootmem_init(octeon_bootinfo->dram_size*1024ULL*1024ULL,
205 0x100000);
206 /*
207 * Allocate all segments to avoid their corruption during boot.
208 */
209 for (i = 0; i < kimage_ptr->nr_segments; i++)
210 cvmx_bootmem_alloc_address(
211 kimage_ptr->segment[i].memsz + 2*PAGE_SIZE,
212 kimage_ptr->segment[i].mem - PAGE_SIZE,
213 PAGE_SIZE);
214 } else {
215 /*
216 * Do not mark all memory as free. Free only named sections
217 * leaving the rest of memory unchanged.
218 */
219 struct cvmx_bootmem_named_block_desc *ptr =
220 (struct cvmx_bootmem_named_block_desc *)
221 named_block_array_ptr;
222
223 for (i = 0; i < bootmem_desc->named_block_num_blocks; i++)
224 if (ptr[i].size)
225 cvmx_bootmem_free_named(ptr[i].name);
226 }
227 kexec_args[2] = 1UL; /* running on octeon_main_processor */
228 kexec_args[3] = (unsigned long)octeon_boot_desc_ptr;
229#ifdef CONFIG_SMP
230 secondary_kexec_args[2] = 0UL; /* running on secondary cpu */
231 secondary_kexec_args[3] = (unsigned long)octeon_boot_desc_ptr;
232#endif
233}
234
235static void octeon_shutdown(void)
236{
237 octeon_generic_shutdown();
238#ifdef CONFIG_SMP
239 smp_call_function(octeon_kexec_smp_down, NULL, 0);
240 smp_wmb();
241 while (num_online_cpus() > 1) {
242 cpu_relax();
243 mdelay(1);
244 }
245#endif
246}
247
248static void octeon_crash_shutdown(struct pt_regs *regs)
249{
250 octeon_generic_shutdown();
251 default_machine_crash_shutdown(regs);
252}
253
254#endif /* CONFIG_KEXEC */
255
David Daney5b3b1682009-01-08 16:46:40 -0800256#ifdef CONFIG_CAVIUM_RESERVE32
257uint64_t octeon_reserve32_memory;
258EXPORT_SYMBOL(octeon_reserve32_memory);
259#endif
260
Ralf Baechleabe77f92012-10-25 16:23:31 +0200261#ifdef CONFIG_KEXEC
262/* crashkernel cmdline parameter is parsed _after_ memory setup
263 * we also parse it here (workaround for EHB5200) */
264static uint64_t crashk_size, crashk_base;
265#endif
266
David Daney5b3b1682009-01-08 16:46:40 -0800267static int octeon_uart;
268
269extern asmlinkage void handle_int(void);
David Daney5b3b1682009-01-08 16:46:40 -0800270
271/**
272 * Return non zero if we are currently running in the Octeon simulator
273 *
274 * Returns
275 */
276int octeon_is_simulation(void)
277{
278 return octeon_bootinfo->board_type == CVMX_BOARD_TYPE_SIM;
279}
280EXPORT_SYMBOL(octeon_is_simulation);
281
282/**
283 * Return true if Octeon is in PCI Host mode. This means
284 * Linux can control the PCI bus.
285 *
286 * Returns Non zero if Octeon in host mode.
287 */
288int octeon_is_pci_host(void)
289{
290#ifdef CONFIG_PCI
291 return octeon_bootinfo->config_flags & CVMX_BOOTINFO_CFG_FLAG_PCI_HOST;
292#else
293 return 0;
294#endif
295}
296
297/**
298 * Get the clock rate of Octeon
299 *
300 * Returns Clock rate in HZ
301 */
302uint64_t octeon_get_clock_rate(void)
303{
David Daneye195aa32010-10-07 16:03:49 -0700304 struct cvmx_sysinfo *sysinfo = cvmx_sysinfo_get();
305
306 return sysinfo->cpu_clock_hz;
David Daney5b3b1682009-01-08 16:46:40 -0800307}
308EXPORT_SYMBOL(octeon_get_clock_rate);
309
David Daneye195aa32010-10-07 16:03:49 -0700310static u64 octeon_io_clock_rate;
311
312u64 octeon_get_io_clock_rate(void)
313{
314 return octeon_io_clock_rate;
315}
316EXPORT_SYMBOL(octeon_get_io_clock_rate);
317
318
David Daney5b3b1682009-01-08 16:46:40 -0800319/**
320 * Write to the LCD display connected to the bootbus. This display
321 * exists on most Cavium evaluation boards. If it doesn't exist, then
322 * this function doesn't do anything.
323 *
Ralf Baechle70342282013-01-22 12:59:30 +0100324 * @s: String to write
David Daney5b3b1682009-01-08 16:46:40 -0800325 */
326void octeon_write_lcd(const char *s)
327{
328 if (octeon_bootinfo->led_display_base_addr) {
329 void __iomem *lcd_address =
330 ioremap_nocache(octeon_bootinfo->led_display_base_addr,
331 8);
332 int i;
333 for (i = 0; i < 8; i++, s++) {
334 if (*s)
335 iowrite8(*s, lcd_address + i);
336 else
337 iowrite8(' ', lcd_address + i);
338 }
339 iounmap(lcd_address);
340 }
341}
342
343/**
344 * Return the console uart passed by the bootloader
345 *
Ralf Baechle70342282013-01-22 12:59:30 +0100346 * Returns uart (0 or 1)
David Daney5b3b1682009-01-08 16:46:40 -0800347 */
348int octeon_get_boot_uart(void)
349{
350 int uart;
351#ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
352 uart = 1;
353#else
354 uart = (octeon_boot_desc_ptr->flags & OCTEON_BL_FLAG_CONSOLE_UART1) ?
355 1 : 0;
356#endif
357 return uart;
358}
359
360/**
361 * Get the coremask Linux was booted on.
362 *
363 * Returns Core mask
364 */
365int octeon_get_boot_coremask(void)
366{
367 return octeon_boot_desc_ptr->core_mask;
368}
369
370/**
371 * Check the hardware BIST results for a CPU
372 */
373void octeon_check_cpu_bist(void)
374{
375 const int coreid = cvmx_get_core_num();
376 unsigned long long mask;
377 unsigned long long bist_val;
378
379 /* Check BIST results for COP0 registers */
380 mask = 0x1f00000000ull;
381 bist_val = read_octeon_c0_icacheerr();
382 if (bist_val & mask)
383 pr_err("Core%d BIST Failure: CacheErr(icache) = 0x%llx\n",
384 coreid, bist_val);
385
386 bist_val = read_octeon_c0_dcacheerr();
387 if (bist_val & 1)
388 pr_err("Core%d L1 Dcache parity error: "
389 "CacheErr(dcache) = 0x%llx\n",
390 coreid, bist_val);
391
392 mask = 0xfc00000000000000ull;
393 bist_val = read_c0_cvmmemctl();
394 if (bist_val & mask)
395 pr_err("Core%d BIST Failure: COP0_CVM_MEM_CTL = 0x%llx\n",
396 coreid, bist_val);
397
398 write_octeon_c0_dcacheerr(0);
399}
400
David Daney5b3b1682009-01-08 16:46:40 -0800401/**
402 * Reboot Octeon
403 *
404 * @command: Command to pass to the bootloader. Currently ignored.
405 */
406static void octeon_restart(char *command)
407{
408 /* Disable all watchdogs before soft reset. They don't get cleared */
409#ifdef CONFIG_SMP
410 int cpu;
411 for_each_online_cpu(cpu)
412 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0);
413#else
414 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);
415#endif
416
417 mb();
418 while (1)
419 cvmx_write_csr(CVMX_CIU_SOFT_RST, 1);
420}
421
422
423/**
424 * Permanently stop a core.
425 *
426 * @arg: Ignored.
427 */
428static void octeon_kill_core(void *arg)
429{
David Daney38c3c0f2013-05-24 16:23:02 +0000430 if (octeon_is_simulation())
David Daney5b3b1682009-01-08 16:46:40 -0800431 /* A break instruction causes the simulator stop a core */
David Daney38c3c0f2013-05-24 16:23:02 +0000432 asm volatile ("break" ::: "memory");
433
434 local_irq_disable();
435 /* Disable watchdog on this core. */
436 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);
437 /* Spin in a low power mode. */
438 while (true)
439 asm volatile ("wait" ::: "memory");
David Daney5b3b1682009-01-08 16:46:40 -0800440}
441
442
443/**
444 * Halt the system
445 */
446static void octeon_halt(void)
447{
448 smp_call_function(octeon_kill_core, NULL, 0);
449
450 switch (octeon_bootinfo->board_type) {
451 case CVMX_BOARD_TYPE_NAO38:
452 /* Driving a 1 to GPIO 12 shuts off this board */
453 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(12), 1);
454 cvmx_write_csr(CVMX_GPIO_TX_SET, 0x1000);
455 break;
456 default:
457 octeon_write_lcd("PowerOff");
458 break;
459 }
460
461 octeon_kill_core(NULL);
462}
463
Aaro Koskinen60830862014-07-22 14:51:08 +0300464static char __read_mostly octeon_system_type[80];
465
466static int __init init_octeon_system_type(void)
467{
468 snprintf(octeon_system_type, sizeof(octeon_system_type), "%s (%s)",
469 cvmx_board_type_to_string(octeon_bootinfo->board_type),
470 octeon_model_get_string(read_c0_prid()));
471
472 return 0;
473}
474early_initcall(init_octeon_system_type);
475
David Daney5b3b1682009-01-08 16:46:40 -0800476/**
David Daney5b3b1682009-01-08 16:46:40 -0800477 * Return a string representing the system type
478 *
479 * Returns
480 */
481const char *octeon_board_type_string(void)
482{
Aaro Koskinen60830862014-07-22 14:51:08 +0300483 return octeon_system_type;
David Daney5b3b1682009-01-08 16:46:40 -0800484}
485
486const char *get_system_type(void)
487 __attribute__ ((alias("octeon_board_type_string")));
488
489void octeon_user_io_init(void)
490{
491 union octeon_cvmemctl cvmmemctl;
492 union cvmx_iob_fau_timeout fau_timeout;
493 union cvmx_pow_nw_tim nm_tim;
David Daney5b3b1682009-01-08 16:46:40 -0800494
495 /* Get the current settings for CP0_CVMMEMCTL_REG */
496 cvmmemctl.u64 = read_c0_cvmmemctl();
497 /* R/W If set, marked write-buffer entries time out the same
498 * as as other entries; if clear, marked write-buffer entries
499 * use the maximum timeout. */
500 cvmmemctl.s.dismarkwblongto = 1;
501 /* R/W If set, a merged store does not clear the write-buffer
502 * entry timeout state. */
503 cvmmemctl.s.dismrgclrwbto = 0;
504 /* R/W Two bits that are the MSBs of the resultant CVMSEG LM
505 * word location for an IOBDMA. The other 8 bits come from the
506 * SCRADDR field of the IOBDMA. */
507 cvmmemctl.s.iobdmascrmsb = 0;
508 /* R/W If set, SYNCWS and SYNCS only order marked stores; if
509 * clear, SYNCWS and SYNCS only order unmarked
510 * stores. SYNCWSMARKED has no effect when DISSYNCWS is
511 * set. */
512 cvmmemctl.s.syncwsmarked = 0;
513 /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as SYNC. */
514 cvmmemctl.s.dissyncws = 0;
515 /* R/W If set, no stall happens on write buffer full. */
516 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2))
517 cvmmemctl.s.diswbfst = 1;
518 else
519 cvmmemctl.s.diswbfst = 0;
520 /* R/W If set (and SX set), supervisor-level loads/stores can
521 * use XKPHYS addresses with <48>==0 */
522 cvmmemctl.s.xkmemenas = 0;
523
524 /* R/W If set (and UX set), user-level loads/stores can use
525 * XKPHYS addresses with VA<48>==0 */
526 cvmmemctl.s.xkmemenau = 0;
527
528 /* R/W If set (and SX set), supervisor-level loads/stores can
529 * use XKPHYS addresses with VA<48>==1 */
530 cvmmemctl.s.xkioenas = 0;
531
532 /* R/W If set (and UX set), user-level loads/stores can use
533 * XKPHYS addresses with VA<48>==1 */
534 cvmmemctl.s.xkioenau = 0;
535
536 /* R/W If set, all stores act as SYNCW (NOMERGE must be set
537 * when this is set) RW, reset to 0. */
538 cvmmemctl.s.allsyncw = 0;
539
540 /* R/W If set, no stores merge, and all stores reach the
541 * coherent bus in order. */
542 cvmmemctl.s.nomerge = 0;
543 /* R/W Selects the bit in the counter used for DID time-outs 0
544 * = 231, 1 = 230, 2 = 229, 3 = 214. Actual time-out is
545 * between 1x and 2x this interval. For example, with
546 * DIDTTO=3, expiration interval is between 16K and 32K. */
547 cvmmemctl.s.didtto = 0;
548 /* R/W If set, the (mem) CSR clock never turns off. */
549 cvmmemctl.s.csrckalwys = 0;
550 /* R/W If set, mclk never turns off. */
551 cvmmemctl.s.mclkalwys = 0;
552 /* R/W Selects the bit in the counter used for write buffer
553 * flush time-outs (WBFLT+11) is the bit position in an
554 * internal counter used to determine expiration. The write
555 * buffer expires between 1x and 2x this interval. For
556 * example, with WBFLT = 0, a write buffer expires between 2K
557 * and 4K cycles after the write buffer entry is allocated. */
558 cvmmemctl.s.wbfltime = 0;
559 /* R/W If set, do not put Istream in the L2 cache. */
560 cvmmemctl.s.istrnol2 = 0;
David Daneyc9941152010-10-07 16:03:53 -0700561
562 /*
563 * R/W The write buffer threshold. As per erratum Core-14752
564 * for CN63XX, a sc/scd might fail if the write buffer is
565 * full. Lowering WBTHRESH greatly lowers the chances of the
566 * write buffer ever being full and triggering the erratum.
567 */
568 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X))
569 cvmmemctl.s.wbthresh = 4;
570 else
571 cvmmemctl.s.wbthresh = 10;
572
David Daney5b3b1682009-01-08 16:46:40 -0800573 /* R/W If set, CVMSEG is available for loads/stores in
574 * kernel/debug mode. */
575#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
576 cvmmemctl.s.cvmsegenak = 1;
577#else
578 cvmmemctl.s.cvmsegenak = 0;
579#endif
580 /* R/W If set, CVMSEG is available for loads/stores in
581 * supervisor mode. */
582 cvmmemctl.s.cvmsegenas = 0;
583 /* R/W If set, CVMSEG is available for loads/stores in user
584 * mode. */
585 cvmmemctl.s.cvmsegenau = 0;
David Daney5b3b1682009-01-08 16:46:40 -0800586
David Daneyc9941152010-10-07 16:03:53 -0700587 write_c0_cvmmemctl(cvmmemctl.u64);
David Daney5b3b1682009-01-08 16:46:40 -0800588
David Daney726da2f2015-01-15 16:11:15 +0300589 /* Setup of CVMSEG is done in kernel-entry-init.h */
David Daney5b3b1682009-01-08 16:46:40 -0800590 if (smp_processor_id() == 0)
591 pr_notice("CVMSEG size: %d cache lines (%d bytes)\n",
592 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE,
593 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128);
594
David Daney5b3b1682009-01-08 16:46:40 -0800595 /* Set a default for the hardware timeouts */
596 fau_timeout.u64 = 0;
597 fau_timeout.s.tout_val = 0xfff;
598 /* Disable tagwait FAU timeout */
599 fau_timeout.s.tout_enb = 0;
600 cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_timeout.u64);
601
602 nm_tim.u64 = 0;
603 /* 4096 cycles */
604 nm_tim.s.nw_tim = 3;
605 cvmx_write_csr(CVMX_POW_NW_TIM, nm_tim.u64);
606
607 write_octeon_c0_icacheerr(0);
608 write_c0_derraddr1(0);
609}
610
611/**
612 * Early entry point for arch setup
613 */
614void __init prom_init(void)
615{
616 struct cvmx_sysinfo *sysinfo;
Ralf Baechleabe77f92012-10-25 16:23:31 +0200617 const char *arg;
618 char *p;
David Daney5b3b1682009-01-08 16:46:40 -0800619 int i;
David Daneyac655fb2015-01-15 16:11:05 +0300620 u64 t;
David Daney5b3b1682009-01-08 16:46:40 -0800621 int argc;
David Daney5b3b1682009-01-08 16:46:40 -0800622#ifdef CONFIG_CAVIUM_RESERVE32
623 int64_t addr = -1;
624#endif
625 /*
626 * The bootloader passes a pointer to the boot descriptor in
627 * $a3, this is available as fw_arg3.
628 */
629 octeon_boot_desc_ptr = (struct octeon_boot_descriptor *)fw_arg3;
630 octeon_bootinfo =
631 cvmx_phys_to_ptr(octeon_boot_desc_ptr->cvmx_desc_vaddr);
632 cvmx_bootmem_init(cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr));
633
David Daneye195aa32010-10-07 16:03:49 -0700634 sysinfo = cvmx_sysinfo_get();
635 memset(sysinfo, 0, sizeof(*sysinfo));
636 sysinfo->system_dram_size = octeon_bootinfo->dram_size << 20;
637 sysinfo->phy_mem_desc_ptr =
638 cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr);
639 sysinfo->core_mask = octeon_bootinfo->core_mask;
640 sysinfo->exception_base_addr = octeon_bootinfo->exception_base_addr;
641 sysinfo->cpu_clock_hz = octeon_bootinfo->eclock_hz;
642 sysinfo->dram_data_rate_hz = octeon_bootinfo->dclock_hz * 2;
643 sysinfo->board_type = octeon_bootinfo->board_type;
644 sysinfo->board_rev_major = octeon_bootinfo->board_rev_major;
645 sysinfo->board_rev_minor = octeon_bootinfo->board_rev_minor;
646 memcpy(sysinfo->mac_addr_base, octeon_bootinfo->mac_addr_base,
647 sizeof(sysinfo->mac_addr_base));
648 sysinfo->mac_addr_count = octeon_bootinfo->mac_addr_count;
649 memcpy(sysinfo->board_serial_number,
650 octeon_bootinfo->board_serial_number,
651 sizeof(sysinfo->board_serial_number));
652 sysinfo->compact_flash_common_base_addr =
653 octeon_bootinfo->compact_flash_common_base_addr;
654 sysinfo->compact_flash_attribute_base_addr =
655 octeon_bootinfo->compact_flash_attribute_base_addr;
656 sysinfo->led_display_base_addr = octeon_bootinfo->led_display_base_addr;
657 sysinfo->dfa_ref_clock_hz = octeon_bootinfo->dfa_ref_clock_hz;
658 sysinfo->bootloader_config_flags = octeon_bootinfo->config_flags;
659
Chandrakala Chavvaac6d9b32015-01-15 16:11:17 +0300660 if (OCTEON_IS_OCTEON2()) {
David Daneye195aa32010-10-07 16:03:49 -0700661 /* I/O clock runs at a different rate than the CPU. */
662 union cvmx_mio_rst_boot rst_boot;
663 rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);
664 octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul;
Chandrakala Chavvaac6d9b32015-01-15 16:11:17 +0300665 } else if (OCTEON_IS_OCTEON3()) {
666 /* I/O clock runs at a different rate than the CPU. */
667 union cvmx_rst_boot rst_boot;
668 rst_boot.u64 = cvmx_read_csr(CVMX_RST_BOOT);
669 octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul;
David Daneye195aa32010-10-07 16:03:49 -0700670 } else {
671 octeon_io_clock_rate = sysinfo->cpu_clock_hz;
672 }
673
David Daneyac655fb2015-01-15 16:11:05 +0300674 t = read_c0_cvmctl();
675 if ((t & (1ull << 27)) == 0) {
676 /*
677 * Setup the multiplier save/restore code if
678 * CvmCtl[NOMUL] clear.
679 */
680 void *save;
681 void *save_end;
682 void *restore;
683 void *restore_end;
684 int save_len;
685 int restore_len;
686 int save_max = (char *)octeon_mult_save_end -
687 (char *)octeon_mult_save;
688 int restore_max = (char *)octeon_mult_restore_end -
689 (char *)octeon_mult_restore;
690 if (current_cpu_data.cputype == CPU_CAVIUM_OCTEON3) {
691 save = octeon_mult_save3;
692 save_end = octeon_mult_save3_end;
693 restore = octeon_mult_restore3;
694 restore_end = octeon_mult_restore3_end;
695 } else {
696 save = octeon_mult_save2;
697 save_end = octeon_mult_save2_end;
698 restore = octeon_mult_restore2;
699 restore_end = octeon_mult_restore2_end;
700 }
701 save_len = (char *)save_end - (char *)save;
702 restore_len = (char *)restore_end - (char *)restore;
703 if (!WARN_ON(save_len > save_max ||
704 restore_len > restore_max)) {
705 memcpy(octeon_mult_save, save, save_len);
706 memcpy(octeon_mult_restore, restore, restore_len);
707 }
708 }
709
David Daney5b3b1682009-01-08 16:46:40 -0800710 /*
711 * Only enable the LED controller if we're running on a CN38XX, CN58XX,
712 * or CN56XX. The CN30XX and CN31XX don't have an LED controller.
713 */
714 if (!octeon_is_simulation() &&
715 octeon_has_feature(OCTEON_FEATURE_LED_CONTROLLER)) {
716 cvmx_write_csr(CVMX_LED_EN, 0);
717 cvmx_write_csr(CVMX_LED_PRT, 0);
718 cvmx_write_csr(CVMX_LED_DBG, 0);
719 cvmx_write_csr(CVMX_LED_PRT_FMT, 0);
720 cvmx_write_csr(CVMX_LED_UDD_CNTX(0), 32);
721 cvmx_write_csr(CVMX_LED_UDD_CNTX(1), 32);
722 cvmx_write_csr(CVMX_LED_UDD_DATX(0), 0);
723 cvmx_write_csr(CVMX_LED_UDD_DATX(1), 0);
724 cvmx_write_csr(CVMX_LED_EN, 1);
725 }
726#ifdef CONFIG_CAVIUM_RESERVE32
727 /*
728 * We need to temporarily allocate all memory in the reserve32
729 * region. This makes sure the kernel doesn't allocate this
730 * memory when it is getting memory from the
731 * bootloader. Later, after the memory allocations are
732 * complete, the reserve32 will be freed.
David Daney1ef28872010-03-03 11:07:07 -0800733 *
David Daney5b3b1682009-01-08 16:46:40 -0800734 * Allocate memory for RESERVED32 aligned on 2MB boundary. This
735 * is in case we later use hugetlb entries with it.
736 */
737 addr = cvmx_bootmem_phy_named_block_alloc(CONFIG_CAVIUM_RESERVE32 << 20,
738 0, 0, 2 << 20,
739 "CAVIUM_RESERVE32", 0);
David Daney5b3b1682009-01-08 16:46:40 -0800740 if (addr < 0)
741 pr_err("Failed to allocate CAVIUM_RESERVE32 memory area\n");
742 else
743 octeon_reserve32_memory = addr;
744#endif
745
746#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2
747 if (cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34)) {
748 pr_info("Skipping L2 locking due to reduced L2 cache size\n");
749 } else {
Ralf Baechle39205752013-06-13 01:29:24 +0200750 uint32_t __maybe_unused ebase = read_c0_ebase() & 0x3ffff000;
David Daney5b3b1682009-01-08 16:46:40 -0800751#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB
752 /* TLB refill */
753 cvmx_l2c_lock_mem_region(ebase, 0x100);
754#endif
755#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION
756 /* General exception */
757 cvmx_l2c_lock_mem_region(ebase + 0x180, 0x80);
758#endif
759#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT
760 /* Interrupt handler */
761 cvmx_l2c_lock_mem_region(ebase + 0x200, 0x80);
762#endif
763#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT
764 cvmx_l2c_lock_mem_region(__pa_symbol(handle_int), 0x100);
765 cvmx_l2c_lock_mem_region(__pa_symbol(plat_irq_dispatch), 0x80);
766#endif
767#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY
768 cvmx_l2c_lock_mem_region(__pa_symbol(memcpy), 0x480);
769#endif
770 }
771#endif
772
David Daney5b3b1682009-01-08 16:46:40 -0800773 octeon_check_cpu_bist();
774
775 octeon_uart = octeon_get_boot_uart();
776
David Daney5b3b1682009-01-08 16:46:40 -0800777#ifdef CONFIG_SMP
778 octeon_write_lcd("LinuxSMP");
779#else
780 octeon_write_lcd("Linux");
781#endif
782
David Daney70a26a22012-08-21 11:45:05 -0700783 octeon_setup_delays();
784
David Daney5b3b1682009-01-08 16:46:40 -0800785 /*
786 * BIST should always be enabled when doing a soft reset. L2
787 * Cache locking for instance is not cleared unless BIST is
788 * enabled. Unfortunately due to a chip errata G-200 for
789 * Cn38XX and CN31XX, BIST msut be disabled on these parts.
790 */
791 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) ||
792 OCTEON_IS_MODEL(OCTEON_CN31XX))
793 cvmx_write_csr(CVMX_CIU_SOFT_BIST, 0);
794 else
795 cvmx_write_csr(CVMX_CIU_SOFT_BIST, 1);
796
797 /* Default to 64MB in the simulator to speed things up */
798 if (octeon_is_simulation())
799 MAX_MEMORY = 64ull << 20;
800
Ralf Baechleabe77f92012-10-25 16:23:31 +0200801 arg = strstr(arcs_cmdline, "mem=");
802 if (arg) {
803 MAX_MEMORY = memparse(arg + 4, &p);
804 if (MAX_MEMORY == 0)
805 MAX_MEMORY = 32ull << 30;
806 if (*p == '@')
807 RESERVE_LOW_MEM = memparse(p + 1, &p);
808 }
809
David Daney5b3b1682009-01-08 16:46:40 -0800810 arcs_cmdline[0] = 0;
811 argc = octeon_boot_desc_ptr->argc;
812 for (i = 0; i < argc; i++) {
813 const char *arg =
814 cvmx_phys_to_ptr(octeon_boot_desc_ptr->argv[i]);
815 if ((strncmp(arg, "MEM=", 4) == 0) ||
816 (strncmp(arg, "mem=", 4) == 0)) {
Ralf Baechleabe77f92012-10-25 16:23:31 +0200817 MAX_MEMORY = memparse(arg + 4, &p);
David Daney5b3b1682009-01-08 16:46:40 -0800818 if (MAX_MEMORY == 0)
819 MAX_MEMORY = 32ull << 30;
Ralf Baechleabe77f92012-10-25 16:23:31 +0200820 if (*p == '@')
821 RESERVE_LOW_MEM = memparse(p + 1, &p);
Ralf Baechleabe77f92012-10-25 16:23:31 +0200822#ifdef CONFIG_KEXEC
823 } else if (strncmp(arg, "crashkernel=", 12) == 0) {
824 crashk_size = memparse(arg+12, &p);
825 if (*p == '@')
826 crashk_base = memparse(p+1, &p);
827 strcat(arcs_cmdline, " ");
828 strcat(arcs_cmdline, arg);
829 /*
830 * To do: switch parsing to new style, something like:
831 * parse_crashkernel(arg, sysinfo->system_dram_size,
Ralf Baechle70342282013-01-22 12:59:30 +0100832 * &crashk_size, &crashk_base);
Ralf Baechleabe77f92012-10-25 16:23:31 +0200833 */
834#endif
David Daney5b3b1682009-01-08 16:46:40 -0800835 } else if (strlen(arcs_cmdline) + strlen(arg) + 1 <
836 sizeof(arcs_cmdline) - 1) {
837 strcat(arcs_cmdline, " ");
838 strcat(arcs_cmdline, arg);
839 }
840 }
841
842 if (strstr(arcs_cmdline, "console=") == NULL) {
David Daney5b3b1682009-01-08 16:46:40 -0800843#ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
844 strcat(arcs_cmdline, " console=ttyS0,115200");
845#else
846 if (octeon_uart == 1)
847 strcat(arcs_cmdline, " console=ttyS1,115200");
848 else
849 strcat(arcs_cmdline, " console=ttyS0,115200");
850#endif
David Daney5b3b1682009-01-08 16:46:40 -0800851 }
852
David Daney5b3b1682009-01-08 16:46:40 -0800853 mips_hpt_frequency = octeon_get_clock_rate();
854
855 octeon_init_cvmcount();
856
857 _machine_restart = octeon_restart;
858 _machine_halt = octeon_halt;
859
Ralf Baechleabe77f92012-10-25 16:23:31 +0200860#ifdef CONFIG_KEXEC
861 _machine_kexec_shutdown = octeon_shutdown;
862 _machine_crash_shutdown = octeon_crash_shutdown;
863 _machine_kexec_prepare = octeon_kexec_prepare;
864#endif
865
David Daney5b3b1682009-01-08 16:46:40 -0800866 octeon_user_io_init();
867 register_smp_ops(&octeon_smp_ops);
868}
869
David Daney2b5987a2010-08-04 14:53:57 -0700870/* Exclude a single page from the regions obtained in plat_mem_setup. */
Ralf Baechleabe77f92012-10-25 16:23:31 +0200871#ifndef CONFIG_CRASH_DUMP
David Daney2b5987a2010-08-04 14:53:57 -0700872static __init void memory_exclude_page(u64 addr, u64 *mem, u64 *size)
873{
874 if (addr > *mem && addr < *mem + *size) {
875 u64 inc = addr - *mem;
876 add_memory_region(*mem, inc, BOOT_MEM_RAM);
877 *mem += inc;
878 *size -= inc;
879 }
880
881 if (addr == *mem && *size > PAGE_SIZE) {
882 *mem += PAGE_SIZE;
883 *size -= PAGE_SIZE;
884 }
885}
Ralf Baechleabe77f92012-10-25 16:23:31 +0200886#endif /* CONFIG_CRASH_DUMP */
David Daney2b5987a2010-08-04 14:53:57 -0700887
David Daney5b3b1682009-01-08 16:46:40 -0800888void __init plat_mem_setup(void)
889{
890 uint64_t mem_alloc_size;
891 uint64_t total;
Ralf Baechleabe77f92012-10-25 16:23:31 +0200892 uint64_t crashk_end;
893#ifndef CONFIG_CRASH_DUMP
David Daney5b3b1682009-01-08 16:46:40 -0800894 int64_t memory;
Ralf Baechleabe77f92012-10-25 16:23:31 +0200895 uint64_t kernel_start;
896 uint64_t kernel_size;
897#endif
David Daney5b3b1682009-01-08 16:46:40 -0800898
899 total = 0;
Ralf Baechleabe77f92012-10-25 16:23:31 +0200900 crashk_end = 0;
David Daney5b3b1682009-01-08 16:46:40 -0800901
David Daney5b3b1682009-01-08 16:46:40 -0800902 /*
903 * The Mips memory init uses the first memory location for
904 * some memory vectors. When SPARSEMEM is in use, it doesn't
905 * verify that the size is big enough for the final
906 * vectors. Making the smallest chuck 4MB seems to be enough
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300907 * to consistently work.
David Daney5b3b1682009-01-08 16:46:40 -0800908 */
909 mem_alloc_size = 4 << 20;
910 if (mem_alloc_size > MAX_MEMORY)
911 mem_alloc_size = MAX_MEMORY;
912
Ralf Baechleabe77f92012-10-25 16:23:31 +0200913/* Crashkernel ignores bootmem list. It relies on mem=X@Y option */
914#ifdef CONFIG_CRASH_DUMP
915 add_memory_region(RESERVE_LOW_MEM, MAX_MEMORY, BOOT_MEM_RAM);
916 total += MAX_MEMORY;
917#else
918#ifdef CONFIG_KEXEC
919 if (crashk_size > 0) {
920 add_memory_region(crashk_base, crashk_size, BOOT_MEM_RAM);
921 crashk_end = crashk_base + crashk_size;
922 }
923#endif
David Daney5b3b1682009-01-08 16:46:40 -0800924 /*
925 * When allocating memory, we want incrementing addresses from
926 * bootmem_alloc so the code in add_memory_region can merge
927 * regions next to each other.
928 */
929 cvmx_bootmem_lock();
930 while ((boot_mem_map.nr_map < BOOT_MEM_MAP_MAX)
931 && (total < MAX_MEMORY)) {
David Daney5b3b1682009-01-08 16:46:40 -0800932 memory = cvmx_bootmem_phy_alloc(mem_alloc_size,
933 __pa_symbol(&__init_end), -1,
934 0x100000,
935 CVMX_BOOTMEM_FLAG_NO_LOCKING);
David Daney5b3b1682009-01-08 16:46:40 -0800936 if (memory >= 0) {
David Daney2b5987a2010-08-04 14:53:57 -0700937 u64 size = mem_alloc_size;
Ralf Baechleabe77f92012-10-25 16:23:31 +0200938#ifdef CONFIG_KEXEC
939 uint64_t end;
940#endif
David Daney2b5987a2010-08-04 14:53:57 -0700941
942 /*
943 * exclude a page at the beginning and end of
944 * the 256MB PCIe 'hole' so the kernel will not
945 * try to allocate multi-page buffers that
946 * span the discontinuity.
947 */
948 memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE,
949 &memory, &size);
950 memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE +
951 CVMX_PCIE_BAR1_PHYS_SIZE,
952 &memory, &size);
Ralf Baechleabe77f92012-10-25 16:23:31 +0200953#ifdef CONFIG_KEXEC
954 end = memory + mem_alloc_size;
David Daney2b5987a2010-08-04 14:53:57 -0700955
David Daney5b3b1682009-01-08 16:46:40 -0800956 /*
Ralf Baechleabe77f92012-10-25 16:23:31 +0200957 * This function automatically merges address regions
958 * next to each other if they are received in
959 * incrementing order
David Daney5b3b1682009-01-08 16:46:40 -0800960 */
Ralf Baechleabe77f92012-10-25 16:23:31 +0200961 if (memory < crashk_base && end > crashk_end) {
962 /* region is fully in */
963 add_memory_region(memory,
964 crashk_base - memory,
965 BOOT_MEM_RAM);
966 total += crashk_base - memory;
967 add_memory_region(crashk_end,
968 end - crashk_end,
969 BOOT_MEM_RAM);
970 total += end - crashk_end;
971 continue;
972 }
973
974 if (memory >= crashk_base && end <= crashk_end)
975 /*
976 * Entire memory region is within the new
977 * kernel's memory, ignore it.
978 */
979 continue;
980
981 if (memory > crashk_base && memory < crashk_end &&
982 end > crashk_end) {
983 /*
984 * Overlap with the beginning of the region,
985 * reserve the beginning.
986 */
987 mem_alloc_size -= crashk_end - memory;
988 memory = crashk_end;
989 } else if (memory < crashk_base && end > crashk_base &&
990 end < crashk_end)
991 /*
992 * Overlap with the beginning of the region,
993 * chop of end.
994 */
995 mem_alloc_size -= end - crashk_base;
996#endif
997 add_memory_region(memory, mem_alloc_size, BOOT_MEM_RAM);
David Daney5b3b1682009-01-08 16:46:40 -0800998 total += mem_alloc_size;
Ralf Baechleabe77f92012-10-25 16:23:31 +0200999 /* Recovering mem_alloc_size */
1000 mem_alloc_size = 4 << 20;
David Daney5b3b1682009-01-08 16:46:40 -08001001 } else {
1002 break;
1003 }
1004 }
1005 cvmx_bootmem_unlock();
Ralf Baechleabe77f92012-10-25 16:23:31 +02001006 /* Add the memory region for the kernel. */
1007 kernel_start = (unsigned long) _text;
David Daneyd949b4f2013-06-12 17:28:33 +00001008 kernel_size = _end - _text;
Ralf Baechleabe77f92012-10-25 16:23:31 +02001009
1010 /* Adjust for physical offset. */
1011 kernel_start &= ~0xffffffff80000000ULL;
1012 add_memory_region(kernel_start, kernel_size, BOOT_MEM_RAM);
1013#endif /* CONFIG_CRASH_DUMP */
David Daney5b3b1682009-01-08 16:46:40 -08001014
1015#ifdef CONFIG_CAVIUM_RESERVE32
1016 /*
1017 * Now that we've allocated the kernel memory it is safe to
1018 * free the reserved region. We free it here so that builtin
1019 * drivers can use the memory.
1020 */
1021 if (octeon_reserve32_memory)
1022 cvmx_bootmem_free_named("CAVIUM_RESERVE32");
1023#endif /* CONFIG_CAVIUM_RESERVE32 */
1024
1025 if (total == 0)
1026 panic("Unable to allocate memory from "
Ralf Baechlef7777dc2013-09-18 16:05:26 +02001027 "cvmx_bootmem_phy_alloc");
David Daney5b3b1682009-01-08 16:46:40 -08001028}
1029
David Daneyea4354642010-07-23 18:41:44 -07001030/*
Ralf Baechle70342282013-01-22 12:59:30 +01001031 * Emit one character to the boot UART. Exported for use by the
David Daneyea4354642010-07-23 18:41:44 -07001032 * watchdog timer.
1033 */
David Daney5b3b1682009-01-08 16:46:40 -08001034int prom_putchar(char c)
1035{
1036 uint64_t lsrval;
1037
1038 /* Spin until there is room */
1039 do {
1040 lsrval = cvmx_read_csr(CVMX_MIO_UARTX_LSR(octeon_uart));
1041 } while ((lsrval & 0x20) == 0);
1042
1043 /* Write the byte */
David Daney606c9582010-05-19 14:16:32 -07001044 cvmx_write_csr(CVMX_MIO_UARTX_THR(octeon_uart), c & 0xffull);
David Daney5b3b1682009-01-08 16:46:40 -08001045 return 1;
1046}
David Daneyea4354642010-07-23 18:41:44 -07001047EXPORT_SYMBOL(prom_putchar);
David Daney5b3b1682009-01-08 16:46:40 -08001048
1049void prom_free_prom_memory(void)
1050{
David Daneye3d0ead2015-01-15 16:11:13 +03001051 if (CAVIUM_OCTEON_DCACHE_PREFETCH_WAR) {
David Daneyc9941152010-10-07 16:03:53 -07001052 /* Check for presence of Core-14449 fix. */
1053 u32 insn;
1054 u32 *foo;
1055
1056 foo = &insn;
1057
1058 asm volatile("# before" : : : "memory");
1059 prefetch(foo);
1060 asm volatile(
1061 ".set push\n\t"
1062 ".set noreorder\n\t"
1063 "bal 1f\n\t"
1064 "nop\n"
1065 "1:\tlw %0,-12($31)\n\t"
1066 ".set pop\n\t"
1067 : "=r" (insn) : : "$31", "memory");
1068
1069 if ((insn >> 26) != 0x33)
Ralf Baechleab75dc02011-11-17 15:07:31 +00001070 panic("No PREF instruction at Core-14449 probe point.");
David Daneyc9941152010-10-07 16:03:53 -07001071
1072 if (((insn >> 16) & 0x1f) != 28)
David Daneye3d0ead2015-01-15 16:11:13 +03001073 panic("OCTEON II DCache prefetch workaround not in place (%04x).\n"
1074 "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).",
1075 insn);
David Daneyc9941152010-10-07 16:03:53 -07001076 }
David Daney5b3b1682009-01-08 16:46:40 -08001077}
David Daney7ed18152012-07-05 18:12:38 +02001078
1079int octeon_prune_device_tree(void);
1080
1081extern const char __dtb_octeon_3xxx_begin;
David Daney7ed18152012-07-05 18:12:38 +02001082extern const char __dtb_octeon_68xx_begin;
David Daney7ed18152012-07-05 18:12:38 +02001083void __init device_tree_init(void)
1084{
Rob Herring8c97cec2014-04-02 17:45:06 -05001085 const void *fdt;
David Daney7ed18152012-07-05 18:12:38 +02001086 bool do_prune;
1087
1088 if (octeon_bootinfo->minor_version >= 3 && octeon_bootinfo->fdt_addr) {
1089 fdt = phys_to_virt(octeon_bootinfo->fdt_addr);
1090 if (fdt_check_header(fdt))
1091 panic("Corrupt Device Tree passed to kernel.");
David Daney7ed18152012-07-05 18:12:38 +02001092 do_prune = false;
1093 } else if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
Rob Herring8c97cec2014-04-02 17:45:06 -05001094 fdt = &__dtb_octeon_68xx_begin;
David Daney7ed18152012-07-05 18:12:38 +02001095 do_prune = true;
1096 } else {
Rob Herring8c97cec2014-04-02 17:45:06 -05001097 fdt = &__dtb_octeon_3xxx_begin;
David Daney7ed18152012-07-05 18:12:38 +02001098 do_prune = true;
1099 }
1100
Rob Herring8c97cec2014-04-02 17:45:06 -05001101 initial_boot_params = (void *)fdt;
David Daney7ed18152012-07-05 18:12:38 +02001102
1103 if (do_prune) {
1104 octeon_prune_device_tree();
1105 pr_info("Using internal Device Tree.\n");
1106 } else {
1107 pr_info("Using passed Device Tree.\n");
1108 }
Rob Herring8c97cec2014-04-02 17:45:06 -05001109 unflatten_and_copy_device_tree();
David Daney7ed18152012-07-05 18:12:38 +02001110}
Ralf Baechlef65aad42012-10-17 00:39:09 +02001111
David Daneye1ced092012-11-15 13:58:59 -08001112static int __initdata disable_octeon_edac_p;
1113
1114static int __init disable_octeon_edac(char *str)
1115{
1116 disable_octeon_edac_p = 1;
1117 return 0;
1118}
1119early_param("disable_octeon_edac", disable_octeon_edac);
1120
Ralf Baechlef65aad42012-10-17 00:39:09 +02001121static char *edac_device_names[] = {
David Daneye1ced092012-11-15 13:58:59 -08001122 "octeon_l2c_edac",
1123 "octeon_pc_edac",
Ralf Baechlef65aad42012-10-17 00:39:09 +02001124};
1125
1126static int __init edac_devinit(void)
1127{
1128 struct platform_device *dev;
1129 int i, err = 0;
David Daneye1ced092012-11-15 13:58:59 -08001130 int num_lmc;
Ralf Baechlef65aad42012-10-17 00:39:09 +02001131 char *name;
1132
David Daneye1ced092012-11-15 13:58:59 -08001133 if (disable_octeon_edac_p)
1134 return 0;
1135
Ralf Baechlef65aad42012-10-17 00:39:09 +02001136 for (i = 0; i < ARRAY_SIZE(edac_device_names); i++) {
1137 name = edac_device_names[i];
1138 dev = platform_device_register_simple(name, -1, NULL, 0);
1139 if (IS_ERR(dev)) {
Masanari Iida6774def2014-11-05 22:26:48 +09001140 pr_err("Registration of %s failed!\n", name);
Ralf Baechlef65aad42012-10-17 00:39:09 +02001141 err = PTR_ERR(dev);
1142 }
1143 }
1144
David Daneye1ced092012-11-15 13:58:59 -08001145 num_lmc = OCTEON_IS_MODEL(OCTEON_CN68XX) ? 4 :
1146 (OCTEON_IS_MODEL(OCTEON_CN56XX) ? 2 : 1);
1147 for (i = 0; i < num_lmc; i++) {
1148 dev = platform_device_register_simple("octeon_lmc_edac",
1149 i, NULL, 0);
1150 if (IS_ERR(dev)) {
Masanari Iida6774def2014-11-05 22:26:48 +09001151 pr_err("Registration of octeon_lmc_edac %d failed!\n", i);
David Daneye1ced092012-11-15 13:58:59 -08001152 err = PTR_ERR(dev);
1153 }
1154 }
1155
Ralf Baechlef65aad42012-10-17 00:39:09 +02001156 return err;
1157}
Ralf Baechlef65aad42012-10-17 00:39:09 +02001158device_initcall(edac_devinit);
Aaro Koskinend8b74272013-07-25 20:26:48 +03001159
1160static void __initdata *octeon_dummy_iospace;
1161
1162static int __init octeon_no_pci_init(void)
1163{
1164 /*
1165 * Initially assume there is no PCI. The PCI/PCIe platform code will
1166 * later re-initialize these to correct values if they are present.
1167 */
1168 octeon_dummy_iospace = vzalloc(IO_SPACE_LIMIT);
1169 set_io_port_base((unsigned long)octeon_dummy_iospace);
1170 ioport_resource.start = MAX_RESOURCE;
1171 ioport_resource.end = 0;
1172 return 0;
1173}
1174core_initcall(octeon_no_pci_init);
1175
1176static int __init octeon_no_pci_release(void)
1177{
1178 /*
1179 * Release the allocated memory if a real IO space is there.
1180 */
1181 if ((unsigned long)octeon_dummy_iospace != mips_io_port_base)
1182 vfree(octeon_dummy_iospace);
1183 return 0;
1184}
1185late_initcall(octeon_no_pci_release);