blob: eea9d3a9d43c172fc3a078c2315b82e28738c3f4 [file] [log] [blame]
Gabor Juhos6baff7f2009-01-14 20:17:06 +01001/*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/nl80211.h>
18#include <linux/pci.h>
Sujith394cf0a2009-02-09 13:26:54 +053019#include "ath9k.h"
Gabor Juhos6baff7f2009-01-14 20:17:06 +010020
21static struct pci_device_id ath_pci_id_table[] __devinitdata = {
22 { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
23 { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
24 { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
25 { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
26 { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
27 { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
28 { 0 }
29};
30
31/* return bus cachesize in 4B word units */
32static void ath_pci_read_cachesize(struct ath_softc *sc, int *csz)
33{
34 u8 u8tmp;
35
36 pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE,
37 (u8 *)&u8tmp);
38 *csz = (int)u8tmp;
39
40 /*
41 * This check was put in to avoid "unplesant" consequences if
42 * the bootrom has not fully initialized all PCI devices.
43 * Sometimes the cache line size register is not set
44 */
45
46 if (*csz == 0)
47 *csz = DEFAULT_CACHELINE >> 2; /* Use the default size */
48}
49
50static void ath_pci_cleanup(struct ath_softc *sc)
51{
52 struct pci_dev *pdev = to_pci_dev(sc->dev);
53
54 pci_iounmap(pdev, sc->mem);
Gabor Juhos6baff7f2009-01-14 20:17:06 +010055 pci_disable_device(pdev);
Sujithdb0f41f2009-02-20 15:13:26 +053056 pci_release_region(pdev, 0);
Gabor Juhos6baff7f2009-01-14 20:17:06 +010057}
58
Sujithcbe61d82009-02-09 13:27:12 +053059static bool ath_pci_eeprom_read(struct ath_hw *ah, u32 off, u16 *data)
Gabor Juhos9dbeb912009-01-14 20:17:08 +010060{
61 (void)REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
62
63 if (!ath9k_hw_wait(ah,
64 AR_EEPROM_STATUS_DATA,
65 AR_EEPROM_STATUS_DATA_BUSY |
Sujith0caa7b12009-02-16 13:23:20 +053066 AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
67 AH_WAIT_TIMEOUT)) {
Gabor Juhos9dbeb912009-01-14 20:17:08 +010068 return false;
69 }
70
71 *data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA),
72 AR_EEPROM_STATUS_DATA_VAL);
73
74 return true;
75}
76
Gabor Juhos6baff7f2009-01-14 20:17:06 +010077static struct ath_bus_ops ath_pci_bus_ops = {
78 .read_cachesize = ath_pci_read_cachesize,
79 .cleanup = ath_pci_cleanup,
Gabor Juhos9dbeb912009-01-14 20:17:08 +010080 .eeprom_read = ath_pci_eeprom_read,
Gabor Juhos6baff7f2009-01-14 20:17:06 +010081};
82
83static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
84{
85 void __iomem *mem;
86 struct ath_softc *sc;
87 struct ieee80211_hw *hw;
88 u8 csz;
89 u32 val;
90 int ret = 0;
Sujithcbe61d82009-02-09 13:27:12 +053091 struct ath_hw *ah;
Gabor Juhos6baff7f2009-01-14 20:17:06 +010092
93 if (pci_enable_device(pdev))
94 return -EIO;
95
96 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
97
98 if (ret) {
99 printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
100 goto bad;
101 }
102
103 ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
104
105 if (ret) {
106 printk(KERN_ERR "ath9k: 32-bit DMA consistent "
107 "DMA enable failed\n");
108 goto bad;
109 }
110
111 /*
112 * Cache line size is used to size and align various
113 * structures used to communicate with the hardware.
114 */
115 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
116 if (csz == 0) {
117 /*
118 * Linux 2.4.18 (at least) writes the cache line size
119 * register as a 16-bit wide register which is wrong.
120 * We must have this setup properly for rx buffer
121 * DMA to work so force a reasonable value here if it
122 * comes up zero.
123 */
124 csz = L1_CACHE_BYTES / sizeof(u32);
125 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
126 }
127 /*
128 * The default setting of latency timer yields poor results,
129 * set it to the value used by other systems. It may be worth
130 * tweaking this setting more.
131 */
132 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
133
134 pci_set_master(pdev);
135
136 /*
137 * Disable the RETRY_TIMEOUT register (0x41) to keep
138 * PCI Tx retries from interfering with C3 CPU state.
139 */
140 pci_read_config_dword(pdev, 0x40, &val);
141 if ((val & 0x0000ff00) != 0)
142 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
143
144 ret = pci_request_region(pdev, 0, "ath9k");
145 if (ret) {
146 dev_err(&pdev->dev, "PCI memory region reserve error\n");
147 ret = -ENODEV;
148 goto bad;
149 }
150
151 mem = pci_iomap(pdev, 0, 0);
152 if (!mem) {
153 printk(KERN_ERR "PCI memory map error\n") ;
154 ret = -EIO;
155 goto bad1;
156 }
157
158 hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
159 if (hw == NULL) {
160 printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n");
161 goto bad2;
162 }
163
164 SET_IEEE80211_DEV(hw, &pdev->dev);
165 pci_set_drvdata(pdev, hw);
166
167 sc = hw->priv;
168 sc->hw = hw;
169 sc->dev = &pdev->dev;
170 sc->mem = mem;
171 sc->bus_ops = &ath_pci_bus_ops;
172
173 if (ath_attach(id->device, sc) != 0) {
174 ret = -ENODEV;
175 goto bad3;
176 }
177
178 /* setup interrupt service routine */
179
180 if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) {
181 printk(KERN_ERR "%s: request_irq failed\n",
182 wiphy_name(hw->wiphy));
183 ret = -EIO;
184 goto bad4;
185 }
186
187 sc->irq = pdev->irq;
188
189 ah = sc->sc_ah;
190 printk(KERN_INFO
191 "%s: Atheros AR%s MAC/BB Rev:%x "
192 "AR%s RF Rev:%x: mem=0x%lx, irq=%d\n",
193 wiphy_name(hw->wiphy),
Sujithd535a422009-02-09 13:27:06 +0530194 ath_mac_bb_name(ah->hw_version.macVersion),
195 ah->hw_version.macRev,
196 ath_rf_name((ah->hw_version.analog5GhzRev & AR_RADIO_SREV_MAJOR)),
197 ah->hw_version.phyRev,
Gabor Juhos6baff7f2009-01-14 20:17:06 +0100198 (unsigned long)mem, pdev->irq);
199
200 return 0;
201bad4:
202 ath_detach(sc);
203bad3:
204 ieee80211_free_hw(hw);
205bad2:
206 pci_iounmap(pdev, mem);
207bad1:
208 pci_release_region(pdev, 0);
209bad:
210 pci_disable_device(pdev);
211 return ret;
212}
213
214static void ath_pci_remove(struct pci_dev *pdev)
215{
216 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
217 struct ath_softc *sc = hw->priv;
218
219 ath_cleanup(sc);
220}
221
222#ifdef CONFIG_PM
223
224static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
225{
226 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
227 struct ath_softc *sc = hw->priv;
228
229 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
230
231#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
Sujith2660b812009-02-09 13:27:26 +0530232 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
Gabor Juhos6baff7f2009-01-14 20:17:06 +0100233 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
234#endif
235
236 pci_save_state(pdev);
237 pci_disable_device(pdev);
238 pci_set_power_state(pdev, PCI_D3hot);
239
240 return 0;
241}
242
243static int ath_pci_resume(struct pci_dev *pdev)
244{
245 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
246 struct ath_softc *sc = hw->priv;
247 u32 val;
248 int err;
249
250 err = pci_enable_device(pdev);
251 if (err)
252 return err;
253 pci_restore_state(pdev);
254 /*
255 * Suspend/Resume resets the PCI configuration space, so we have to
256 * re-disable the RETRY_TIMEOUT register (0x41) to keep
257 * PCI Tx retries from interfering with C3 CPU state
258 */
259 pci_read_config_dword(pdev, 0x40, &val);
260 if ((val & 0x0000ff00) != 0)
261 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
262
263 /* Enable LED */
264 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
265 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
266 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
267
268#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
269 /*
270 * check the h/w rfkill state on resume
271 * and start the rfkill poll timer
272 */
Sujith2660b812009-02-09 13:27:26 +0530273 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
Gabor Juhos6baff7f2009-01-14 20:17:06 +0100274 queue_delayed_work(sc->hw->workqueue,
275 &sc->rf_kill.rfkill_poll, 0);
276#endif
277
278 return 0;
279}
280
281#endif /* CONFIG_PM */
282
283MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
284
285static struct pci_driver ath_pci_driver = {
286 .name = "ath9k",
287 .id_table = ath_pci_id_table,
288 .probe = ath_pci_probe,
289 .remove = ath_pci_remove,
290#ifdef CONFIG_PM
291 .suspend = ath_pci_suspend,
292 .resume = ath_pci_resume,
293#endif /* CONFIG_PM */
294};
295
Sujithdb0f41f2009-02-20 15:13:26 +0530296int ath_pci_init(void)
Gabor Juhos6baff7f2009-01-14 20:17:06 +0100297{
298 return pci_register_driver(&ath_pci_driver);
299}
300
301void ath_pci_exit(void)
302{
303 pci_unregister_driver(&ath_pci_driver);
304}