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Abhilash Kesavanccf55112014-05-16 04:26:30 +09001/*
2 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * arch/arm/mach-exynos/mcpm-exynos.c
6 *
7 * Based on arch/arm/mach-vexpress/dcscb.c
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/arm-cci.h>
15#include <linux/delay.h>
16#include <linux/io.h>
17#include <linux/of_address.h>
Abhilash Kesavanadc548d2014-11-07 09:20:16 +090018#include <linux/syscore_ops.h>
Pankaj Dubey2262d6e2015-12-18 09:02:11 +053019#include <linux/soc/samsung/exynos-regs-pmu.h>
Abhilash Kesavanccf55112014-05-16 04:26:30 +090020
21#include <asm/cputype.h>
22#include <asm/cp15.h>
23#include <asm/mcpm.h>
Chanho Park833b5792015-09-01 23:17:03 +090024#include <asm/smp_plat.h>
Abhilash Kesavanccf55112014-05-16 04:26:30 +090025
Abhilash Kesavanccf55112014-05-16 04:26:30 +090026#include "common.h"
27
28#define EXYNOS5420_CPUS_PER_CLUSTER 4
29#define EXYNOS5420_NR_CLUSTERS 2
Abhilash Kesavanccf55112014-05-16 04:26:30 +090030
Abhilash Kesavan20fe6f92014-07-05 05:50:58 +090031#define EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN BIT(9)
32#define EXYNOS5420_USE_ARM_CORE_DOWN_STATE BIT(29)
33#define EXYNOS5420_USE_L2_COMMON_UP_STATE BIT(30)
34
Krzysztof Kozlowski731d97c2016-12-10 15:47:33 +020035static void __iomem *ns_sram_base_addr __ro_after_init;
Abhilash Kesavanadc548d2014-11-07 09:20:16 +090036
Abhilash Kesavanccf55112014-05-16 04:26:30 +090037/*
38 * The common v7_exit_coherency_flush API could not be used because of the
39 * Erratum 799270 workaround. This macro is the same as the common one (in
40 * arch/arm/include/asm/cacheflush.h) except for the erratum handling.
41 */
42#define exynos_v7_exit_coherency_flush(level) \
43 asm volatile( \
44 "stmfd sp!, {fp, ip}\n\t"\
45 "mrc p15, 0, r0, c1, c0, 0 @ get SCTLR\n\t" \
46 "bic r0, r0, #"__stringify(CR_C)"\n\t" \
47 "mcr p15, 0, r0, c1, c0, 0 @ set SCTLR\n\t" \
48 "isb\n\t"\
49 "bl v7_flush_dcache_"__stringify(level)"\n\t" \
Abhilash Kesavanccf55112014-05-16 04:26:30 +090050 "mrc p15, 0, r0, c1, c0, 1 @ get ACTLR\n\t" \
51 "bic r0, r0, #(1 << 6) @ disable local coherency\n\t" \
52 /* Dummy Load of a device register to avoid Erratum 799270 */ \
53 "ldr r4, [%0]\n\t" \
54 "and r4, r4, #0\n\t" \
55 "orr r0, r0, r4\n\t" \
56 "mcr p15, 0, r0, c1, c0, 1 @ set ACTLR\n\t" \
57 "isb\n\t" \
58 "dsb\n\t" \
59 "ldmfd sp!, {fp, ip}" \
60 : \
Pankaj Dubey2e94ac42014-07-19 03:43:22 +090061 : "Ir" (pmu_base_addr + S5P_INFORM0) \
Abhilash Kesavanccf55112014-05-16 04:26:30 +090062 : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
63 "r9", "r10", "lr", "memory")
64
Nicolas Pitre5f493ac2015-03-16 17:16:07 -040065static int exynos_cpu_powerup(unsigned int cpu, unsigned int cluster)
Abhilash Kesavanccf55112014-05-16 04:26:30 +090066{
67 unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
Abhilash Kesavanccf55112014-05-16 04:26:30 +090068
69 pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
70 if (cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
71 cluster >= EXYNOS5420_NR_CLUSTERS)
72 return -EINVAL;
73
Chanho Park833b5792015-09-01 23:17:03 +090074 if (!exynos_cpu_power_state(cpunr)) {
75 exynos_cpu_power_up(cpunr);
76
77 /*
78 * This assumes the cluster number of the big cores(Cortex A15)
79 * is 0 and the Little cores(Cortex A7) is 1.
80 * When the system was booted from the Little core,
81 * they should be reset during power up cpu.
82 */
83 if (cluster &&
84 cluster == MPIDR_AFFINITY_LEVEL(cpu_logical_map(0), 1)) {
85 /*
86 * Before we reset the Little cores, we should wait
87 * the SPARE2 register is set to 1 because the init
88 * codes of the iROM will set the register after
89 * initialization.
90 */
91 while (!pmu_raw_readl(S5P_PMU_SPARE2))
92 udelay(10);
93
94 pmu_raw_writel(EXYNOS5420_KFC_CORE_RESET(cpu),
95 EXYNOS_SWRESET);
96 }
97 }
98
Abhilash Kesavan20fe6f92014-07-05 05:50:58 +090099 return 0;
Abhilash Kesavanccf55112014-05-16 04:26:30 +0900100}
101
Nicolas Pitre5f493ac2015-03-16 17:16:07 -0400102static int exynos_cluster_powerup(unsigned int cluster)
Abhilash Kesavanccf55112014-05-16 04:26:30 +0900103{
Nicolas Pitre5f493ac2015-03-16 17:16:07 -0400104 pr_debug("%s: cluster %u\n", __func__, cluster);
105 if (cluster >= EXYNOS5420_NR_CLUSTERS)
106 return -EINVAL;
Abhilash Kesavanccf55112014-05-16 04:26:30 +0900107
Nicolas Pitre5f493ac2015-03-16 17:16:07 -0400108 exynos_cluster_power_up(cluster);
109 return 0;
110}
111
112static void exynos_cpu_powerdown_prepare(unsigned int cpu, unsigned int cluster)
113{
114 unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
Abhilash Kesavanccf55112014-05-16 04:26:30 +0900115
116 pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
117 BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
118 cluster >= EXYNOS5420_NR_CLUSTERS);
Nicolas Pitre5f493ac2015-03-16 17:16:07 -0400119 exynos_cpu_power_down(cpunr);
120}
Abhilash Kesavanccf55112014-05-16 04:26:30 +0900121
Nicolas Pitre5f493ac2015-03-16 17:16:07 -0400122static void exynos_cluster_powerdown_prepare(unsigned int cluster)
123{
124 pr_debug("%s: cluster %u\n", __func__, cluster);
125 BUG_ON(cluster >= EXYNOS5420_NR_CLUSTERS);
126 exynos_cluster_power_down(cluster);
127}
Abhilash Kesavanccf55112014-05-16 04:26:30 +0900128
Nicolas Pitre5f493ac2015-03-16 17:16:07 -0400129static void exynos_cpu_cache_disable(void)
130{
131 /* Disable and flush the local CPU cache. */
132 exynos_v7_exit_coherency_flush(louis);
133}
Abhilash Kesavanccf55112014-05-16 04:26:30 +0900134
Nicolas Pitre5f493ac2015-03-16 17:16:07 -0400135static void exynos_cluster_cache_disable(void)
136{
137 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A15) {
Abhilash Kesavanccf55112014-05-16 04:26:30 +0900138 /*
Nicolas Pitre5f493ac2015-03-16 17:16:07 -0400139 * On the Cortex-A15 we need to disable
140 * L2 prefetching before flushing the cache.
Abhilash Kesavanccf55112014-05-16 04:26:30 +0900141 */
Nicolas Pitre5f493ac2015-03-16 17:16:07 -0400142 asm volatile(
143 "mcr p15, 1, %0, c15, c0, 3\n\t"
144 "isb\n\t"
145 "dsb"
146 : : "r" (0x400));
Abhilash Kesavanccf55112014-05-16 04:26:30 +0900147 }
148
Nicolas Pitre5f493ac2015-03-16 17:16:07 -0400149 /* Flush all cache levels for this cluster. */
150 exynos_v7_exit_coherency_flush(all);
Abhilash Kesavanccf55112014-05-16 04:26:30 +0900151
Nicolas Pitre5f493ac2015-03-16 17:16:07 -0400152 /*
153 * Disable cluster-level coherency by masking
154 * incoming snoops and DVM messages:
155 */
156 cci_disable_port_by_cpu(read_cpuid_mpidr());
Abhilash Kesavanccf55112014-05-16 04:26:30 +0900157}
158
Kukjin Kim7c5688e2014-05-28 00:04:34 +0900159static int exynos_wait_for_powerdown(unsigned int cpu, unsigned int cluster)
Abhilash Kesavanccf55112014-05-16 04:26:30 +0900160{
161 unsigned int tries = 100;
162 unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
163
164 pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
165 BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
166 cluster >= EXYNOS5420_NR_CLUSTERS);
167
168 /* Wait for the core state to be OFF */
169 while (tries--) {
Nicolas Pitre5f493ac2015-03-16 17:16:07 -0400170 if ((exynos_cpu_power_state(cpunr) == 0))
171 return 0; /* success: the CPU is halted */
Abhilash Kesavanccf55112014-05-16 04:26:30 +0900172
173 /* Otherwise, wait and retry: */
174 msleep(1);
175 }
176
177 return -ETIMEDOUT; /* timeout */
178}
179
Nicolas Pitre5f493ac2015-03-16 17:16:07 -0400180static void exynos_cpu_is_up(unsigned int cpu, unsigned int cluster)
Chander Kashyapfc2cac42014-07-05 06:24:35 +0900181{
Nicolas Pitre5f493ac2015-03-16 17:16:07 -0400182 /* especially when resuming: make sure power control is set */
183 exynos_cpu_powerup(cpu, cluster);
Chander Kashyapfc2cac42014-07-05 06:24:35 +0900184}
185
Abhilash Kesavanccf55112014-05-16 04:26:30 +0900186static const struct mcpm_platform_ops exynos_power_ops = {
Nicolas Pitre5f493ac2015-03-16 17:16:07 -0400187 .cpu_powerup = exynos_cpu_powerup,
188 .cluster_powerup = exynos_cluster_powerup,
189 .cpu_powerdown_prepare = exynos_cpu_powerdown_prepare,
190 .cluster_powerdown_prepare = exynos_cluster_powerdown_prepare,
191 .cpu_cache_disable = exynos_cpu_cache_disable,
192 .cluster_cache_disable = exynos_cluster_cache_disable,
Kukjin Kim7c5688e2014-05-28 00:04:34 +0900193 .wait_for_powerdown = exynos_wait_for_powerdown,
Nicolas Pitre5f493ac2015-03-16 17:16:07 -0400194 .cpu_is_up = exynos_cpu_is_up,
Abhilash Kesavanccf55112014-05-16 04:26:30 +0900195};
196
Abhilash Kesavanccf55112014-05-16 04:26:30 +0900197/*
198 * Enable cluster-level coherency, in preparation for turning on the MMU.
199 */
200static void __naked exynos_pm_power_up_setup(unsigned int affinity_level)
201{
202 asm volatile ("\n"
203 "cmp r0, #1\n"
204 "bxne lr\n"
205 "b cci_enable_port_for_self");
206}
207
Abhilash Kesavanf99acff2014-05-28 01:19:35 +0900208static const struct of_device_id exynos_dt_mcpm_match[] = {
209 { .compatible = "samsung,exynos5420" },
210 { .compatible = "samsung,exynos5800" },
211 {},
212};
213
Abhilash Kesavanadc548d2014-11-07 09:20:16 +0900214static void exynos_mcpm_setup_entry_point(void)
215{
216 /*
217 * U-Boot SPL is hardcoded to jump to the start of ns_sram_base_addr
218 * as part of secondary_cpu_start(). Let's redirect it to the
219 * mcpm_entry_point(). This is done during both secondary boot-up as
220 * well as system resume.
221 */
222 __raw_writel(0xe59f0000, ns_sram_base_addr); /* ldr r0, [pc, #0] */
223 __raw_writel(0xe12fff10, ns_sram_base_addr + 4); /* bx r0 */
Florian Fainelli64fc2a92017-01-15 03:59:29 +0100224 __raw_writel(__pa_symbol(mcpm_entry_point), ns_sram_base_addr + 8);
Abhilash Kesavanadc548d2014-11-07 09:20:16 +0900225}
226
227static struct syscore_ops exynos_mcpm_syscore_ops = {
228 .resume = exynos_mcpm_setup_entry_point,
229};
230
Abhilash Kesavanccf55112014-05-16 04:26:30 +0900231static int __init exynos_mcpm_init(void)
232{
233 struct device_node *node;
Abhilash Kesavan20fe6f92014-07-05 05:50:58 +0900234 unsigned int value, i;
Abhilash Kesavanccf55112014-05-16 04:26:30 +0900235 int ret;
236
Abhilash Kesavanf99acff2014-05-28 01:19:35 +0900237 node = of_find_matching_node(NULL, exynos_dt_mcpm_match);
Abhilash Kesavanccf55112014-05-16 04:26:30 +0900238 if (!node)
239 return -ENODEV;
240 of_node_put(node);
241
242 if (!cci_probed())
243 return -ENODEV;
244
245 node = of_find_compatible_node(NULL, NULL,
246 "samsung,exynos4210-sysram-ns");
247 if (!node)
248 return -ENODEV;
249
250 ns_sram_base_addr = of_iomap(node, 0);
251 of_node_put(node);
252 if (!ns_sram_base_addr) {
253 pr_err("failed to map non-secure iRAM base address\n");
254 return -ENOMEM;
255 }
256
257 /*
258 * To increase the stability of KFC reset we need to program
259 * the PMU SPARE3 register
260 */
Pankaj Dubey2e94ac42014-07-19 03:43:22 +0900261 pmu_raw_writel(EXYNOS5420_SWRESET_KFC_SEL, S5P_PMU_SPARE3);
Abhilash Kesavanccf55112014-05-16 04:26:30 +0900262
Abhilash Kesavanccf55112014-05-16 04:26:30 +0900263 ret = mcpm_platform_register(&exynos_power_ops);
264 if (!ret)
265 ret = mcpm_sync_init(exynos_pm_power_up_setup);
Nicolas Pitrefbb04992014-06-24 18:36:32 +0100266 if (!ret)
Nicolas Pitre5f493ac2015-03-16 17:16:07 -0400267 ret = mcpm_loopback(exynos_cluster_cache_disable); /* turn on the CCI */
Abhilash Kesavanccf55112014-05-16 04:26:30 +0900268 if (ret) {
269 iounmap(ns_sram_base_addr);
270 return ret;
271 }
272
273 mcpm_smp_set_ops();
274
275 pr_info("Exynos MCPM support installed\n");
276
277 /*
Abhilash Kesavan20fe6f92014-07-05 05:50:58 +0900278 * On Exynos5420/5800 for the A15 and A7 clusters:
279 *
280 * EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN ensures that all the cores
281 * in a cluster are turned off before turning off the cluster L2.
282 *
283 * EXYNOS5420_USE_ARM_CORE_DOWN_STATE ensures that a cores is powered
284 * off before waking it up.
285 *
286 * EXYNOS5420_USE_L2_COMMON_UP_STATE ensures that cluster L2 will be
287 * turned on before the first man is powered up.
288 */
289 for (i = 0; i < EXYNOS5420_NR_CLUSTERS; i++) {
Pankaj Dubey2e94ac42014-07-19 03:43:22 +0900290 value = pmu_raw_readl(EXYNOS_COMMON_OPTION(i));
Abhilash Kesavan20fe6f92014-07-05 05:50:58 +0900291 value |= EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN |
292 EXYNOS5420_USE_ARM_CORE_DOWN_STATE |
293 EXYNOS5420_USE_L2_COMMON_UP_STATE;
Pankaj Dubey2e94ac42014-07-19 03:43:22 +0900294 pmu_raw_writel(value, EXYNOS_COMMON_OPTION(i));
Abhilash Kesavan20fe6f92014-07-05 05:50:58 +0900295 }
296
Abhilash Kesavanadc548d2014-11-07 09:20:16 +0900297 exynos_mcpm_setup_entry_point();
Abhilash Kesavanccf55112014-05-16 04:26:30 +0900298
Abhilash Kesavanadc548d2014-11-07 09:20:16 +0900299 register_syscore_ops(&exynos_mcpm_syscore_ops);
Abhilash Kesavanccf55112014-05-16 04:26:30 +0900300
301 return ret;
302}
303
304early_initcall(exynos_mcpm_init);