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Paul Mundtcad82442006-01-16 22:14:19 -08001menu "Memory management options"
2
Paul Mundt5f8c9902007-05-08 11:55:21 +09003config QUICKLIST
4 def_bool y
5
Paul Mundtcad82442006-01-16 22:14:19 -08006config MMU
7 bool "Support for memory management hardware"
8 depends on !CPU_SH2
9 default y
10 help
11 Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
12 boot on these systems, this option must not be set.
13
14 On other systems (such as the SH-3 and 4) where an MMU exists,
15 turning this off will boot the kernel on these machines with the
16 MMU implicitly switched off.
17
Paul Mundte7f93a32006-09-27 17:19:13 +090018config PAGE_OFFSET
19 hex
Paul Mundt36763b22007-11-21 15:34:33 +090020 default "0x80000000" if MMU && SUPERH32
21 default "0x20000000" if MMU && SUPERH64
Paul Mundte7f93a32006-09-27 17:19:13 +090022 default "0x00000000"
23
Paul Mundtad3256e2009-05-14 17:40:08 +090024config FORCE_MAX_ZONEORDER
25 int "Maximum zone order"
26 range 9 64 if PAGE_SIZE_16KB
27 default "9" if PAGE_SIZE_16KB
28 range 7 64 if PAGE_SIZE_64KB
29 default "7" if PAGE_SIZE_64KB
30 range 11 64
31 default "14" if !MMU
32 default "11"
33 help
34 The kernel memory allocator divides physically contiguous memory
35 blocks into "zones", where each zone is a power of two number of
36 pages. This option selects the largest power of two that the kernel
37 keeps in the memory allocator. If you need to allocate very large
38 blocks of physically contiguous memory, then you may need to
39 increase this value.
40
41 This config option is actually maximum order plus one. For example,
42 a value of 11 means that the largest free memory block is 2^10 pages.
43
44 The page size is not necessarily 4KB. Keep this in mind when
45 choosing a value for this option.
46
Paul Mundte7f93a32006-09-27 17:19:13 +090047config MEMORY_START
48 hex "Physical memory start address"
49 default "0x08000000"
50 ---help---
51 Computers built with Hitachi SuperH processors always
52 map the ROM starting at address zero. But the processor
53 does not specify the range that RAM takes.
54
55 The physical memory (RAM) start address will be automatically
56 set to 08000000. Other platforms, such as the Solution Engine
57 boards typically map RAM at 0C000000.
58
59 Tweak this only when porting to a new machine which does not
60 already have a defconfig. Changing it from the known correct
61 value on any of the known systems will only lead to disaster.
62
63config MEMORY_SIZE
64 hex "Physical memory size"
Paul Mundt711fe432007-11-21 15:46:07 +090065 default "0x04000000"
Paul Mundte7f93a32006-09-27 17:19:13 +090066 help
67 This sets the default memory size assumed by your SH kernel. It can
68 be overridden as normal by the 'mem=' argument on the kernel command
69 line. If unsure, consult your board specifications or just leave it
Paul Mundt711fe432007-11-21 15:46:07 +090070 as 0x04000000 which was the default value before this became
Paul Mundte7f93a32006-09-27 17:19:13 +090071 configurable.
72
Paul Mundt36bcd392007-11-10 19:16:55 +090073# Physical addressing modes
74
75config 29BIT
76 def_bool !32BIT
77 depends on SUPERH32
78
Paul Mundtcad82442006-01-16 22:14:19 -080079config 32BIT
Paul Mundt36bcd392007-11-10 19:16:55 +090080 bool
81 default y if CPU_SH5
82
Yoshihiro Shimoda2f47f442009-03-10 15:49:54 +090083config PMB_ENABLE
Paul Mundtcad82442006-01-16 22:14:19 -080084 bool "Support 32-bit physical addressing through PMB"
Yoshihiro Shimodac01f0f12009-08-21 16:30:28 +090085 depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7757 || CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785)
Paul Mundt36bcd392007-11-10 19:16:55 +090086 select 32BIT
Paul Mundtcad82442006-01-16 22:14:19 -080087 default y
88 help
89 If you say Y here, physical addressing will be extended to
90 32-bits through the SH-4A PMB. If this is not set, legacy
91 29-bit physical addressing will be used.
92
Yoshihiro Shimoda2f47f442009-03-10 15:49:54 +090093choice
94 prompt "PMB handling type"
95 depends on PMB_ENABLE
96 default PMB_FIXED
97
98config PMB
99 bool "PMB"
Yoshihiro Shimodac01f0f12009-08-21 16:30:28 +0900100 depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7757 || CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785)
Yoshihiro Shimoda2f47f442009-03-10 15:49:54 +0900101 select 32BIT
102 help
103 If you say Y here, physical addressing will be extended to
104 32-bits through the SH-4A PMB. If this is not set, legacy
105 29-bit physical addressing will be used.
106
107config PMB_FIXED
108 bool "fixed PMB"
Yoshihiro Shimodac01f0f12009-08-21 16:30:28 +0900109 depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7757 || \
110 CPU_SUBTYPE_SH7780 || \
Yoshihiro Shimoda2f47f442009-03-10 15:49:54 +0900111 CPU_SUBTYPE_SH7785)
112 select 32BIT
113 help
114 If this option is enabled, fixed PMB mappings are inherited
115 from the boot loader, and the kernel does not attempt dynamic
116 management. This is the closest to legacy 29-bit physical mode,
117 and allows systems to support up to 512MiB of system memory.
118
119endchoice
120
Paul Mundt21440cf2006-11-20 14:30:26 +0900121config X2TLB
122 bool "Enable extended TLB mode"
Paul Mundtc3af3972007-09-27 18:08:46 +0900123 depends on (CPU_SHX2 || CPU_SHX3) && MMU && EXPERIMENTAL
Paul Mundt21440cf2006-11-20 14:30:26 +0900124 help
125 Selecting this option will enable the extended mode of the SH-X2
126 TLB. For legacy SH-X behaviour and interoperability, say N. For
127 all of the fun new features and a willingless to submit bug reports,
128 say Y.
129
Paul Mundt19f9a342006-09-27 18:33:49 +0900130config VSYSCALL
131 bool "Support vsyscall page"
Paul Mundta09063d2007-11-08 18:54:16 +0900132 depends on MMU && (CPU_SH3 || CPU_SH4)
Paul Mundt19f9a342006-09-27 18:33:49 +0900133 default y
134 help
135 This will enable support for the kernel mapping a vDSO page
136 in process space, and subsequently handing down the entry point
137 to the libc through the ELF auxiliary vector.
138
139 From the kernel side this is used for the signal trampoline.
140 For systems with an MMU that can afford to give up a page,
141 (the default value) say Y.
142
Paul Mundtb241cb02007-06-06 17:52:19 +0900143config NUMA
144 bool "Non Uniform Memory Access (NUMA) Support"
Paul Mundt357d5942007-06-11 15:32:07 +0900145 depends on MMU && SYS_SUPPORTS_NUMA && EXPERIMENTAL
Paul Mundtb241cb02007-06-06 17:52:19 +0900146 default n
147 help
148 Some SH systems have many various memories scattered around
149 the address space, each with varying latencies. This enables
150 support for these blocks by binding them to nodes and allowing
151 memory policies to be used for prioritizing and controlling
152 allocation behaviour.
153
Paul Mundt01066622007-03-28 16:38:13 +0900154config NODES_SHIFT
155 int
Paul Mundt99044942007-08-08 16:45:07 +0900156 default "3" if CPU_SUBTYPE_SHX3
Paul Mundt01066622007-03-28 16:38:13 +0900157 default "1"
158 depends on NEED_MULTIPLE_NODES
159
160config ARCH_FLATMEM_ENABLE
161 def_bool y
Paul Mundt357d5942007-06-11 15:32:07 +0900162 depends on !NUMA
Paul Mundt01066622007-03-28 16:38:13 +0900163
Paul Mundtdfbb9042007-05-23 17:48:36 +0900164config ARCH_SPARSEMEM_ENABLE
165 def_bool y
166 select SPARSEMEM_STATIC
167
168config ARCH_SPARSEMEM_DEFAULT
169 def_bool y
170
Paul Mundt1ce7ddd2007-05-09 13:20:52 +0900171config MAX_ACTIVE_REGIONS
172 int
Paul Mundt7da3b8e2007-08-01 17:52:47 +0900173 default "6" if (CPU_SUBTYPE_SHX3 && SPARSEMEM)
Paul Mundtdc47e9d2007-09-27 16:48:00 +0900174 default "2" if SPARSEMEM && (CPU_SUBTYPE_SH7722 || \
175 CPU_SUBTYPE_SH7785)
Paul Mundt1ce7ddd2007-05-09 13:20:52 +0900176 default "1"
177
Paul Mundt01066622007-03-28 16:38:13 +0900178config ARCH_POPULATES_NODE_MAP
179 def_bool y
180
Paul Mundtdfbb9042007-05-23 17:48:36 +0900181config ARCH_SELECT_MEMORY_MODEL
182 def_bool y
183
Paul Mundt33d63bd2007-06-07 11:32:52 +0900184config ARCH_ENABLE_MEMORY_HOTPLUG
185 def_bool y
Paul Mundtb85641b2008-09-17 23:13:27 +0900186 depends on SPARSEMEM && MMU
Paul Mundt33d63bd2007-06-07 11:32:52 +0900187
Paul Mundt3159e7d2008-09-05 15:39:12 +0900188config ARCH_ENABLE_MEMORY_HOTREMOVE
189 def_bool y
Paul Mundtb85641b2008-09-17 23:13:27 +0900190 depends on SPARSEMEM && MMU
Paul Mundt3159e7d2008-09-05 15:39:12 +0900191
Paul Mundt33d63bd2007-06-07 11:32:52 +0900192config ARCH_MEMORY_PROBE
193 def_bool y
194 depends on MEMORY_HOTPLUG
195
Paul Mundtcad82442006-01-16 22:14:19 -0800196choice
Paul Mundt21440cf2006-11-20 14:30:26 +0900197 prompt "Kernel page size"
Paul Mundt4d2cab72007-09-27 10:47:00 +0900198 default PAGE_SIZE_8KB if X2TLB
Paul Mundt21440cf2006-11-20 14:30:26 +0900199 default PAGE_SIZE_4KB
200
201config PAGE_SIZE_4KB
202 bool "4kB"
Paul Mundt74fcc772008-06-03 18:52:11 +0900203 depends on !MMU || !X2TLB
Paul Mundt21440cf2006-11-20 14:30:26 +0900204 help
205 This is the default page size used by all SuperH CPUs.
206
207config PAGE_SIZE_8KB
208 bool "8kB"
Paul Mundt74fcc772008-06-03 18:52:11 +0900209 depends on !MMU || X2TLB
Paul Mundt21440cf2006-11-20 14:30:26 +0900210 help
211 This enables 8kB pages as supported by SH-X2 and later MMUs.
212
Paul Mundt66dfe182008-06-03 18:54:02 +0900213config PAGE_SIZE_16KB
214 bool "16kB"
215 depends on !MMU
216 help
217 This enables 16kB pages on MMU-less SH systems.
218
Paul Mundt21440cf2006-11-20 14:30:26 +0900219config PAGE_SIZE_64KB
220 bool "64kB"
Paul Mundt74fcc772008-06-03 18:52:11 +0900221 depends on !MMU || CPU_SH4 || CPU_SH5
Paul Mundt21440cf2006-11-20 14:30:26 +0900222 help
223 This enables support for 64kB pages, possible on all SH-4
Paul Mundt4d2cab72007-09-27 10:47:00 +0900224 CPUs and later.
Paul Mundt21440cf2006-11-20 14:30:26 +0900225
226endchoice
227
228choice
Paul Mundtcad82442006-01-16 22:14:19 -0800229 prompt "HugeTLB page size"
Paul Mundtffb4a732009-10-27 07:22:37 +0900230 depends on HUGETLB_PAGE
Paul Mundt68b7c242008-08-06 15:10:49 +0900231 default HUGETLB_PAGE_SIZE_1MB if PAGE_SIZE_64KB
Paul Mundtcad82442006-01-16 22:14:19 -0800232 default HUGETLB_PAGE_SIZE_64K
233
234config HUGETLB_PAGE_SIZE_64K
Paul Mundt21440cf2006-11-20 14:30:26 +0900235 bool "64kB"
Paul Mundt68b7c242008-08-06 15:10:49 +0900236 depends on !PAGE_SIZE_64KB
Paul Mundt21440cf2006-11-20 14:30:26 +0900237
238config HUGETLB_PAGE_SIZE_256K
239 bool "256kB"
240 depends on X2TLB
Paul Mundtcad82442006-01-16 22:14:19 -0800241
242config HUGETLB_PAGE_SIZE_1MB
243 bool "1MB"
244
Paul Mundt21440cf2006-11-20 14:30:26 +0900245config HUGETLB_PAGE_SIZE_4MB
246 bool "4MB"
247 depends on X2TLB
248
249config HUGETLB_PAGE_SIZE_64MB
250 bool "64MB"
251 depends on X2TLB
252
Paul Mundta09063d2007-11-08 18:54:16 +0900253config HUGETLB_PAGE_SIZE_512MB
254 bool "512MB"
255 depends on CPU_SH5
256
Paul Mundtcad82442006-01-16 22:14:19 -0800257endchoice
258
259source "mm/Kconfig"
260
261endmenu
262
263menu "Cache configuration"
264
265config SH7705_CACHE_32KB
266 bool "Enable 32KB cache size for SH7705"
267 depends on CPU_SUBTYPE_SH7705
268 default y
269
Paul Mundte7bd34a2007-07-31 17:07:28 +0900270choice
271 prompt "Cache mode"
Paul Mundta09063d2007-11-08 18:54:16 +0900272 default CACHE_WRITEBACK if CPU_SH2A || CPU_SH3 || CPU_SH4 || CPU_SH5
Paul Mundte7bd34a2007-07-31 17:07:28 +0900273 default CACHE_WRITETHROUGH if (CPU_SH2 && !CPU_SH2A)
274
275config CACHE_WRITEBACK
276 bool "Write-back"
Paul Mundte7bd34a2007-07-31 17:07:28 +0900277
278config CACHE_WRITETHROUGH
279 bool "Write-through"
Paul Mundtcad82442006-01-16 22:14:19 -0800280 help
281 Selecting this option will configure the caches in write-through
282 mode, as opposed to the default write-back configuration.
283
284 Since there's sill some aliasing issues on SH-4, this option will
285 unfortunately still require the majority of flushing functions to
286 be implemented to deal with aliasing.
287
288 If unsure, say N.
289
Paul Mundte7bd34a2007-07-31 17:07:28 +0900290config CACHE_OFF
291 bool "Off"
292
293endchoice
294
Paul Mundtcad82442006-01-16 22:14:19 -0800295endmenu