Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 1 | menu "Memory management options" |
| 2 | |
Paul Mundt | 5f8c990 | 2007-05-08 11:55:21 +0900 | [diff] [blame] | 3 | config QUICKLIST |
| 4 | def_bool y |
| 5 | |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 6 | config MMU |
| 7 | bool "Support for memory management hardware" |
| 8 | depends on !CPU_SH2 |
| 9 | default y |
| 10 | help |
| 11 | Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to |
| 12 | boot on these systems, this option must not be set. |
| 13 | |
| 14 | On other systems (such as the SH-3 and 4) where an MMU exists, |
| 15 | turning this off will boot the kernel on these machines with the |
| 16 | MMU implicitly switched off. |
| 17 | |
Paul Mundt | e7f93a3 | 2006-09-27 17:19:13 +0900 | [diff] [blame] | 18 | config PAGE_OFFSET |
| 19 | hex |
Paul Mundt | 36763b2 | 2007-11-21 15:34:33 +0900 | [diff] [blame] | 20 | default "0x80000000" if MMU && SUPERH32 |
| 21 | default "0x20000000" if MMU && SUPERH64 |
Paul Mundt | e7f93a3 | 2006-09-27 17:19:13 +0900 | [diff] [blame] | 22 | default "0x00000000" |
| 23 | |
Paul Mundt | ad3256e | 2009-05-14 17:40:08 +0900 | [diff] [blame] | 24 | config FORCE_MAX_ZONEORDER |
| 25 | int "Maximum zone order" |
| 26 | range 9 64 if PAGE_SIZE_16KB |
| 27 | default "9" if PAGE_SIZE_16KB |
| 28 | range 7 64 if PAGE_SIZE_64KB |
| 29 | default "7" if PAGE_SIZE_64KB |
| 30 | range 11 64 |
| 31 | default "14" if !MMU |
| 32 | default "11" |
| 33 | help |
| 34 | The kernel memory allocator divides physically contiguous memory |
| 35 | blocks into "zones", where each zone is a power of two number of |
| 36 | pages. This option selects the largest power of two that the kernel |
| 37 | keeps in the memory allocator. If you need to allocate very large |
| 38 | blocks of physically contiguous memory, then you may need to |
| 39 | increase this value. |
| 40 | |
| 41 | This config option is actually maximum order plus one. For example, |
| 42 | a value of 11 means that the largest free memory block is 2^10 pages. |
| 43 | |
| 44 | The page size is not necessarily 4KB. Keep this in mind when |
| 45 | choosing a value for this option. |
| 46 | |
Paul Mundt | e7f93a3 | 2006-09-27 17:19:13 +0900 | [diff] [blame] | 47 | config MEMORY_START |
| 48 | hex "Physical memory start address" |
| 49 | default "0x08000000" |
| 50 | ---help--- |
| 51 | Computers built with Hitachi SuperH processors always |
| 52 | map the ROM starting at address zero. But the processor |
| 53 | does not specify the range that RAM takes. |
| 54 | |
| 55 | The physical memory (RAM) start address will be automatically |
| 56 | set to 08000000. Other platforms, such as the Solution Engine |
| 57 | boards typically map RAM at 0C000000. |
| 58 | |
| 59 | Tweak this only when porting to a new machine which does not |
| 60 | already have a defconfig. Changing it from the known correct |
| 61 | value on any of the known systems will only lead to disaster. |
| 62 | |
| 63 | config MEMORY_SIZE |
| 64 | hex "Physical memory size" |
Paul Mundt | 711fe43 | 2007-11-21 15:46:07 +0900 | [diff] [blame] | 65 | default "0x04000000" |
Paul Mundt | e7f93a3 | 2006-09-27 17:19:13 +0900 | [diff] [blame] | 66 | help |
| 67 | This sets the default memory size assumed by your SH kernel. It can |
| 68 | be overridden as normal by the 'mem=' argument on the kernel command |
| 69 | line. If unsure, consult your board specifications or just leave it |
Paul Mundt | 711fe43 | 2007-11-21 15:46:07 +0900 | [diff] [blame] | 70 | as 0x04000000 which was the default value before this became |
Paul Mundt | e7f93a3 | 2006-09-27 17:19:13 +0900 | [diff] [blame] | 71 | configurable. |
| 72 | |
Paul Mundt | 36bcd39 | 2007-11-10 19:16:55 +0900 | [diff] [blame] | 73 | # Physical addressing modes |
| 74 | |
| 75 | config 29BIT |
| 76 | def_bool !32BIT |
| 77 | depends on SUPERH32 |
| 78 | |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 79 | config 32BIT |
Paul Mundt | 36bcd39 | 2007-11-10 19:16:55 +0900 | [diff] [blame] | 80 | bool |
| 81 | default y if CPU_SH5 |
| 82 | |
Yoshihiro Shimoda | 2f47f44 | 2009-03-10 15:49:54 +0900 | [diff] [blame] | 83 | config PMB_ENABLE |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 84 | bool "Support 32-bit physical addressing through PMB" |
Yoshihiro Shimoda | c01f0f1 | 2009-08-21 16:30:28 +0900 | [diff] [blame] | 85 | depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7757 || CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785) |
Paul Mundt | 36bcd39 | 2007-11-10 19:16:55 +0900 | [diff] [blame] | 86 | select 32BIT |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 87 | default y |
| 88 | help |
| 89 | If you say Y here, physical addressing will be extended to |
| 90 | 32-bits through the SH-4A PMB. If this is not set, legacy |
| 91 | 29-bit physical addressing will be used. |
| 92 | |
Yoshihiro Shimoda | 2f47f44 | 2009-03-10 15:49:54 +0900 | [diff] [blame] | 93 | choice |
| 94 | prompt "PMB handling type" |
| 95 | depends on PMB_ENABLE |
| 96 | default PMB_FIXED |
| 97 | |
| 98 | config PMB |
| 99 | bool "PMB" |
Yoshihiro Shimoda | c01f0f1 | 2009-08-21 16:30:28 +0900 | [diff] [blame] | 100 | depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7757 || CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785) |
Yoshihiro Shimoda | 2f47f44 | 2009-03-10 15:49:54 +0900 | [diff] [blame] | 101 | select 32BIT |
| 102 | help |
| 103 | If you say Y here, physical addressing will be extended to |
| 104 | 32-bits through the SH-4A PMB. If this is not set, legacy |
| 105 | 29-bit physical addressing will be used. |
| 106 | |
| 107 | config PMB_FIXED |
| 108 | bool "fixed PMB" |
Yoshihiro Shimoda | c01f0f1 | 2009-08-21 16:30:28 +0900 | [diff] [blame] | 109 | depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7757 || \ |
| 110 | CPU_SUBTYPE_SH7780 || \ |
Yoshihiro Shimoda | 2f47f44 | 2009-03-10 15:49:54 +0900 | [diff] [blame] | 111 | CPU_SUBTYPE_SH7785) |
| 112 | select 32BIT |
| 113 | help |
| 114 | If this option is enabled, fixed PMB mappings are inherited |
| 115 | from the boot loader, and the kernel does not attempt dynamic |
| 116 | management. This is the closest to legacy 29-bit physical mode, |
| 117 | and allows systems to support up to 512MiB of system memory. |
| 118 | |
| 119 | endchoice |
| 120 | |
Paul Mundt | 21440cf | 2006-11-20 14:30:26 +0900 | [diff] [blame] | 121 | config X2TLB |
| 122 | bool "Enable extended TLB mode" |
Paul Mundt | c3af397 | 2007-09-27 18:08:46 +0900 | [diff] [blame] | 123 | depends on (CPU_SHX2 || CPU_SHX3) && MMU && EXPERIMENTAL |
Paul Mundt | 21440cf | 2006-11-20 14:30:26 +0900 | [diff] [blame] | 124 | help |
| 125 | Selecting this option will enable the extended mode of the SH-X2 |
| 126 | TLB. For legacy SH-X behaviour and interoperability, say N. For |
| 127 | all of the fun new features and a willingless to submit bug reports, |
| 128 | say Y. |
| 129 | |
Paul Mundt | 19f9a34 | 2006-09-27 18:33:49 +0900 | [diff] [blame] | 130 | config VSYSCALL |
| 131 | bool "Support vsyscall page" |
Paul Mundt | a09063d | 2007-11-08 18:54:16 +0900 | [diff] [blame] | 132 | depends on MMU && (CPU_SH3 || CPU_SH4) |
Paul Mundt | 19f9a34 | 2006-09-27 18:33:49 +0900 | [diff] [blame] | 133 | default y |
| 134 | help |
| 135 | This will enable support for the kernel mapping a vDSO page |
| 136 | in process space, and subsequently handing down the entry point |
| 137 | to the libc through the ELF auxiliary vector. |
| 138 | |
| 139 | From the kernel side this is used for the signal trampoline. |
| 140 | For systems with an MMU that can afford to give up a page, |
| 141 | (the default value) say Y. |
| 142 | |
Paul Mundt | b241cb0 | 2007-06-06 17:52:19 +0900 | [diff] [blame] | 143 | config NUMA |
| 144 | bool "Non Uniform Memory Access (NUMA) Support" |
Paul Mundt | 357d594 | 2007-06-11 15:32:07 +0900 | [diff] [blame] | 145 | depends on MMU && SYS_SUPPORTS_NUMA && EXPERIMENTAL |
Paul Mundt | b241cb0 | 2007-06-06 17:52:19 +0900 | [diff] [blame] | 146 | default n |
| 147 | help |
| 148 | Some SH systems have many various memories scattered around |
| 149 | the address space, each with varying latencies. This enables |
| 150 | support for these blocks by binding them to nodes and allowing |
| 151 | memory policies to be used for prioritizing and controlling |
| 152 | allocation behaviour. |
| 153 | |
Paul Mundt | 0106662 | 2007-03-28 16:38:13 +0900 | [diff] [blame] | 154 | config NODES_SHIFT |
| 155 | int |
Paul Mundt | 9904494 | 2007-08-08 16:45:07 +0900 | [diff] [blame] | 156 | default "3" if CPU_SUBTYPE_SHX3 |
Paul Mundt | 0106662 | 2007-03-28 16:38:13 +0900 | [diff] [blame] | 157 | default "1" |
| 158 | depends on NEED_MULTIPLE_NODES |
| 159 | |
| 160 | config ARCH_FLATMEM_ENABLE |
| 161 | def_bool y |
Paul Mundt | 357d594 | 2007-06-11 15:32:07 +0900 | [diff] [blame] | 162 | depends on !NUMA |
Paul Mundt | 0106662 | 2007-03-28 16:38:13 +0900 | [diff] [blame] | 163 | |
Paul Mundt | dfbb904 | 2007-05-23 17:48:36 +0900 | [diff] [blame] | 164 | config ARCH_SPARSEMEM_ENABLE |
| 165 | def_bool y |
| 166 | select SPARSEMEM_STATIC |
| 167 | |
| 168 | config ARCH_SPARSEMEM_DEFAULT |
| 169 | def_bool y |
| 170 | |
Paul Mundt | 1ce7ddd | 2007-05-09 13:20:52 +0900 | [diff] [blame] | 171 | config MAX_ACTIVE_REGIONS |
| 172 | int |
Paul Mundt | 7da3b8e | 2007-08-01 17:52:47 +0900 | [diff] [blame] | 173 | default "6" if (CPU_SUBTYPE_SHX3 && SPARSEMEM) |
Paul Mundt | dc47e9d | 2007-09-27 16:48:00 +0900 | [diff] [blame] | 174 | default "2" if SPARSEMEM && (CPU_SUBTYPE_SH7722 || \ |
| 175 | CPU_SUBTYPE_SH7785) |
Paul Mundt | 1ce7ddd | 2007-05-09 13:20:52 +0900 | [diff] [blame] | 176 | default "1" |
| 177 | |
Paul Mundt | 0106662 | 2007-03-28 16:38:13 +0900 | [diff] [blame] | 178 | config ARCH_POPULATES_NODE_MAP |
| 179 | def_bool y |
| 180 | |
Paul Mundt | dfbb904 | 2007-05-23 17:48:36 +0900 | [diff] [blame] | 181 | config ARCH_SELECT_MEMORY_MODEL |
| 182 | def_bool y |
| 183 | |
Paul Mundt | 33d63bd | 2007-06-07 11:32:52 +0900 | [diff] [blame] | 184 | config ARCH_ENABLE_MEMORY_HOTPLUG |
| 185 | def_bool y |
Paul Mundt | b85641b | 2008-09-17 23:13:27 +0900 | [diff] [blame] | 186 | depends on SPARSEMEM && MMU |
Paul Mundt | 33d63bd | 2007-06-07 11:32:52 +0900 | [diff] [blame] | 187 | |
Paul Mundt | 3159e7d | 2008-09-05 15:39:12 +0900 | [diff] [blame] | 188 | config ARCH_ENABLE_MEMORY_HOTREMOVE |
| 189 | def_bool y |
Paul Mundt | b85641b | 2008-09-17 23:13:27 +0900 | [diff] [blame] | 190 | depends on SPARSEMEM && MMU |
Paul Mundt | 3159e7d | 2008-09-05 15:39:12 +0900 | [diff] [blame] | 191 | |
Paul Mundt | 33d63bd | 2007-06-07 11:32:52 +0900 | [diff] [blame] | 192 | config ARCH_MEMORY_PROBE |
| 193 | def_bool y |
| 194 | depends on MEMORY_HOTPLUG |
| 195 | |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 196 | choice |
Paul Mundt | 21440cf | 2006-11-20 14:30:26 +0900 | [diff] [blame] | 197 | prompt "Kernel page size" |
Paul Mundt | 4d2cab7 | 2007-09-27 10:47:00 +0900 | [diff] [blame] | 198 | default PAGE_SIZE_8KB if X2TLB |
Paul Mundt | 21440cf | 2006-11-20 14:30:26 +0900 | [diff] [blame] | 199 | default PAGE_SIZE_4KB |
| 200 | |
| 201 | config PAGE_SIZE_4KB |
| 202 | bool "4kB" |
Paul Mundt | 74fcc77 | 2008-06-03 18:52:11 +0900 | [diff] [blame] | 203 | depends on !MMU || !X2TLB |
Paul Mundt | 21440cf | 2006-11-20 14:30:26 +0900 | [diff] [blame] | 204 | help |
| 205 | This is the default page size used by all SuperH CPUs. |
| 206 | |
| 207 | config PAGE_SIZE_8KB |
| 208 | bool "8kB" |
Paul Mundt | 74fcc77 | 2008-06-03 18:52:11 +0900 | [diff] [blame] | 209 | depends on !MMU || X2TLB |
Paul Mundt | 21440cf | 2006-11-20 14:30:26 +0900 | [diff] [blame] | 210 | help |
| 211 | This enables 8kB pages as supported by SH-X2 and later MMUs. |
| 212 | |
Paul Mundt | 66dfe18 | 2008-06-03 18:54:02 +0900 | [diff] [blame] | 213 | config PAGE_SIZE_16KB |
| 214 | bool "16kB" |
| 215 | depends on !MMU |
| 216 | help |
| 217 | This enables 16kB pages on MMU-less SH systems. |
| 218 | |
Paul Mundt | 21440cf | 2006-11-20 14:30:26 +0900 | [diff] [blame] | 219 | config PAGE_SIZE_64KB |
| 220 | bool "64kB" |
Paul Mundt | 74fcc77 | 2008-06-03 18:52:11 +0900 | [diff] [blame] | 221 | depends on !MMU || CPU_SH4 || CPU_SH5 |
Paul Mundt | 21440cf | 2006-11-20 14:30:26 +0900 | [diff] [blame] | 222 | help |
| 223 | This enables support for 64kB pages, possible on all SH-4 |
Paul Mundt | 4d2cab7 | 2007-09-27 10:47:00 +0900 | [diff] [blame] | 224 | CPUs and later. |
Paul Mundt | 21440cf | 2006-11-20 14:30:26 +0900 | [diff] [blame] | 225 | |
| 226 | endchoice |
| 227 | |
| 228 | choice |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 229 | prompt "HugeTLB page size" |
Paul Mundt | ffb4a73 | 2009-10-27 07:22:37 +0900 | [diff] [blame^] | 230 | depends on HUGETLB_PAGE |
Paul Mundt | 68b7c24 | 2008-08-06 15:10:49 +0900 | [diff] [blame] | 231 | default HUGETLB_PAGE_SIZE_1MB if PAGE_SIZE_64KB |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 232 | default HUGETLB_PAGE_SIZE_64K |
| 233 | |
| 234 | config HUGETLB_PAGE_SIZE_64K |
Paul Mundt | 21440cf | 2006-11-20 14:30:26 +0900 | [diff] [blame] | 235 | bool "64kB" |
Paul Mundt | 68b7c24 | 2008-08-06 15:10:49 +0900 | [diff] [blame] | 236 | depends on !PAGE_SIZE_64KB |
Paul Mundt | 21440cf | 2006-11-20 14:30:26 +0900 | [diff] [blame] | 237 | |
| 238 | config HUGETLB_PAGE_SIZE_256K |
| 239 | bool "256kB" |
| 240 | depends on X2TLB |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 241 | |
| 242 | config HUGETLB_PAGE_SIZE_1MB |
| 243 | bool "1MB" |
| 244 | |
Paul Mundt | 21440cf | 2006-11-20 14:30:26 +0900 | [diff] [blame] | 245 | config HUGETLB_PAGE_SIZE_4MB |
| 246 | bool "4MB" |
| 247 | depends on X2TLB |
| 248 | |
| 249 | config HUGETLB_PAGE_SIZE_64MB |
| 250 | bool "64MB" |
| 251 | depends on X2TLB |
| 252 | |
Paul Mundt | a09063d | 2007-11-08 18:54:16 +0900 | [diff] [blame] | 253 | config HUGETLB_PAGE_SIZE_512MB |
| 254 | bool "512MB" |
| 255 | depends on CPU_SH5 |
| 256 | |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 257 | endchoice |
| 258 | |
| 259 | source "mm/Kconfig" |
| 260 | |
| 261 | endmenu |
| 262 | |
| 263 | menu "Cache configuration" |
| 264 | |
| 265 | config SH7705_CACHE_32KB |
| 266 | bool "Enable 32KB cache size for SH7705" |
| 267 | depends on CPU_SUBTYPE_SH7705 |
| 268 | default y |
| 269 | |
Paul Mundt | e7bd34a | 2007-07-31 17:07:28 +0900 | [diff] [blame] | 270 | choice |
| 271 | prompt "Cache mode" |
Paul Mundt | a09063d | 2007-11-08 18:54:16 +0900 | [diff] [blame] | 272 | default CACHE_WRITEBACK if CPU_SH2A || CPU_SH3 || CPU_SH4 || CPU_SH5 |
Paul Mundt | e7bd34a | 2007-07-31 17:07:28 +0900 | [diff] [blame] | 273 | default CACHE_WRITETHROUGH if (CPU_SH2 && !CPU_SH2A) |
| 274 | |
| 275 | config CACHE_WRITEBACK |
| 276 | bool "Write-back" |
Paul Mundt | e7bd34a | 2007-07-31 17:07:28 +0900 | [diff] [blame] | 277 | |
| 278 | config CACHE_WRITETHROUGH |
| 279 | bool "Write-through" |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 280 | help |
| 281 | Selecting this option will configure the caches in write-through |
| 282 | mode, as opposed to the default write-back configuration. |
| 283 | |
| 284 | Since there's sill some aliasing issues on SH-4, this option will |
| 285 | unfortunately still require the majority of flushing functions to |
| 286 | be implemented to deal with aliasing. |
| 287 | |
| 288 | If unsure, say N. |
| 289 | |
Paul Mundt | e7bd34a | 2007-07-31 17:07:28 +0900 | [diff] [blame] | 290 | config CACHE_OFF |
| 291 | bool "Off" |
| 292 | |
| 293 | endchoice |
| 294 | |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 295 | endmenu |