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gerrit-public.fairphone.software / kernel / msm-4.19 / 321a1b3026ea194dd084cf3bda1e235b2986b0af / drivers / gpu / drm
  1. 321a1b3 drm/i915: Only reprobe display on encoder which has received an HPD event (v2) by Egbert Eich · 12 years ago
  2. 142e239 drm/i915: Add bit field to record which pins have received HPD events (v3) by Egbert Eich · 12 years ago
  3. 259bd5d drm/i915: fix locking around punit access in cur_delayinfo for VLV by Jesse Barnes · 12 years ago
  4. 9119708 drm/i915: Split out Haswell code from gen6_pte_encode. by Kenneth Graunke · 12 years ago
  5. 93c34e7 drm/i915: Fix page table entries for Bay Trail. by Kenneth Graunke · 12 years ago
  6. 2d04bef drm/i915: Add PTE encoding function to the gtt/ppgtt vtables. by Kenneth Graunke · 12 years ago
  7. 80ad920 drm/i915: Make struct dpll == intel_clock_t by Ville Syrjälä · 12 years ago
  8. cece5d5 drm/i915: use vlv_dport_to_channel in vlv_signal_levels by Jesse Barnes · 12 years ago
  9. bf98a72 drm/i915: Remove mention of Haswell in DDI code by Damien Lespiau · 12 years ago
  10. 29a397b drm/i915: Move the CSC_MODE bits next to the register by Ville Syrjälä · 12 years ago
  11. f196e6b drm/i915: use cpu_transcoder for TRANS_DDI_FUNC_CTL by Paulo Zanoni · 12 years ago
  12. 2bfce95 drm/i915: check the power well inside haswell_get_pipe_config by Paulo Zanoni · 12 years ago
  13. de032bf drm/i915: print Gen5+ CPU/PCH poison interrupts by Paulo Zanoni · 12 years ago
  14. 8664281 drm/i915: report Gen5+ CPU and PCH FIFO underruns by Paulo Zanoni · 12 years ago
  15. 89b667f drm/i915: update VLV PLL and DPIO code v11 by Jesse Barnes · 12 years ago
  16. 78c9b7e drm/i915: drop init_dpio, shouldn't be needed by Jesse Barnes · 12 years ago
  17. e2fa6fb drm/i915/dp: program VSwing and Preemphasis control settings on VLV v2 by Pallavi G · 12 years ago
  18. 598fac6 drm/i915: magic VLV PLL registers in the dpio sideband by Daniel Vetter · 12 years ago
  19. 75e5398 drm/i915: fix VLV limits by Daniel Vetter · 12 years ago
  20. 0a073b8 drm/i915: turbo & RC6 support for VLV v7 by Jesse Barnes · 12 years ago
  21. 855ba3b drm/i915: VLV GPU frequency to opcode functions by Jesse Barnes · 12 years ago
  22. 06da8da drm/i915: Use alphabetical names for sprites by Ville Syrjälä · 12 years ago
  23. 4bb6f1f drm/i915: Use alphabetical names for transcoders too by Ville Syrjälä · 12 years ago
  24. 84f44ce drm/i915: Print plane, pipe, port names as alphabetical insted of decimal by Ville Syrjälä · 12 years ago
  25. cfc33bf drm/i915: Use port_name() in PCH port audio power change message by Ville Syrjälä · 12 years ago
  26. 2582a85 drm/i915: Use pipe_name() and port_name() where appropriate by Ville Syrjälä · 12 years ago
  27. e3641d3 drm/i915: move debug output back to the right place by Daniel Vetter · 12 years ago
  28. e29a18f drm/i915: add i9xx pfit pipe asserts by Daniel Vetter · 12 years ago
  29. 58c6eaa drm/i915: add pipe asserts for the crtc enable sequence by Daniel Vetter · 12 years ago
  30. 4667730 drm/i915: drop redundant vblank waits by Daniel Vetter · 12 years ago
  31. d59f9f4 drm/i915: don't enable the plane too early in i9xx_crtc_mode_set by Daniel Vetter · 12 years ago
  32. bd080ee drm/i915: fix bpc vs. bpp confusion in intel_crtc_compute_config by Daniel Vetter · 12 years ago
  33. 3b117c8 drm/i915: move cpu_transcoder to the pipe configuration by Daniel Vetter · 12 years ago
  34. dc4bd2d drm/i915: preserve the PBC bits of TRANS_CHICKEN2 by Paulo Zanoni · 12 years ago
  35. 3f704fa drm/i915: set CPT FDI RX polarity bits based on VBT by Paulo Zanoni · 12 years ago
  36. ac4c16c drm/i915: Add Reenable Timer to turn Hotplug Detection back on (v4) by Egbert Eich · 12 years ago
  37. cd569ae drm/i915: Disable HPD interrupt on pin when irq storm is detected (v3) by Egbert Eich · 12 years ago
  38. 995e6b3 drm/i915: Mask out the HPD irq bits before setting them individually. by Egbert Eich · 12 years ago
  39. 821450c drm/i915: (re)init HPD interrupt storm statistics by Egbert Eich · 12 years ago
  40. b543fb0 drm/i915: Add HPD IRQ storm detection (v5) by Egbert Eich · 12 years ago
  41. 08e1413 drm/i915: WARN when LPT-LP is not paired with ULT CPU by Paulo Zanoni · 12 years ago
  42. c40c0f5 drm/i915: don't intel_crt_init on any ULT machines by Paulo Zanoni · 12 years ago
  43. 6af79ae drm/i915: remove comment about IVB link training from intel_pm.c by Paulo Zanoni · 12 years ago
  44. 30ccd96 drm/i915: VLV doesn't have LLC by Ben Widawsky · 12 years ago
  45. 3ebecd0 drm/i915: Scale ring, rather than ia, frequency on Haswell by Chris Wilson · 12 years ago
  46. 3a3b4f9 drm/i915: shorten debugfs output simple attributes by Mika Kuoppala · 12 years ago
  47. 87476d6 drm/i915: Fixup pfit disabling for gen2/3 by Daniel Vetter · 12 years ago
  48. b6c5164 drm/i915: Fixup Oops in the pipe config computation by Daniel Vetter · 12 years ago
  49. dc652f9 drm/i915: ensure single initialization and cleanup of backlight device by Jani Nikula · 12 years ago
  50. f7708f7 drm/i915: don't touch the PF regs if the power well is down by Paulo Zanoni · 12 years ago
  51. 15d199e drm/i915: add intel_using_power_well by Paulo Zanoni · 12 years ago
  52. f30da18 drm/i915: don't check inconsistent modeset state when force-restoring by Daniel Vetter · 12 years ago
  53. 42b5aea drm/i915: IVB/HSW have 32 fence register by Ville Syrjälä · 12 years ago
  54. 182642b drm/i915: Return stored value from max freq sysfs entry by Mika Kuoppala · 12 years ago
  55. 6a99476 drm/i915: Remove stale code by Ben Widawsky · 12 years ago
  56. 3a06247 drm/i915: Increase max fence pitch limit to 256KB on IVB+ by Ville Syrjälä · 12 years ago
  57. fe48d8d drm/i915: Reject fence stride=0 on gen4+ by Ville Syrjälä · 12 years ago
  58. a6f429a drm/i915: Configure GAM_ECOCHK appropriatly for Gen7 by Ville Syrjälä · 12 years ago
  59. a65c2fc drm/i915: Set GAC_ECO_BITS register on Gen7+ by Ville Syrjälä · 12 years ago
  60. 3b9d788 drm/i915: Add ECOBITS_SNB_BIT by Ville Syrjälä · 12 years ago
  61. 10e0849 drm/i915: Don't default to overclock max by Ben Widawsky · 12 years ago
  62. 31c7738 drm/i915: Better overclock support by Ben Widawsky · 12 years ago
  63. 2c55c33 drm/i915: use lower aux clock divider on non-ULT HSW by Jani Nikula · 12 years ago
  64. b7c36d2 drm/i915: Allow PPGTT enable to fail by Ben Widawsky · 12 years ago
  65. 5963cf0 drm/i915: NULL aliasing_ppgtt on cleanup by Ben Widawsky · 12 years ago
  66. 6197349 drm/i915: Abstract PPGTT enabling by Ben Widawsky · 12 years ago
  67. 3ed124b drm/i915: Rework PPGTT init code by Ben Widawsky · 12 years ago
  68. 3eb1c00 drm/i915: Conditionally carve out GGTT PDE by Ben Widawsky · 12 years ago
  69. 1e7d12d drm/i915/ppgtt: Set scratch page "globally" by Ben Widawsky · 12 years ago
  70. c81dbe0 drm/i915: random checkpatch fixes by Ben Widawsky · 12 years ago
  71. 1e1bd0f drm/i915: Map registers before GTT init by Ben Widawsky · 12 years ago
  72. e7c2b58 drm/i915: Call out GEN6 PTE specificity by Ben Widawsky · 12 years ago
  73. a93e416 drm/i915: generalize pte vs. register BAR allocation by Ben Widawsky · 12 years ago
  74. 4615d4c drm/i915: Use MLC (l3$) for context objects by Chris Wilson · 12 years ago
  75. 57d277b drm/i915: update FDI mPHY setup code by Daniel Vetter · 12 years ago
  76. 25ff119 drm/i915: Workaround incoherence between fences and LLC across multiple CPUs by Chris Wilson · 12 years ago
  77. 8bb6e95 drm/i915: tune down Y tiling scanout warning by Daniel Vetter · 12 years ago
  78. 9a7c789 drm/i915: set CB tuning also for the reduce clock by Daniel Vetter · 12 years ago
  79. f0b4405 drm/i915: fix FP CB tuning limits for lvds by Daniel Vetter · 12 years ago
  80. 7d0ac5b drm/i915: fix lost FP_CB_TUNE setting for pch plls by Daniel Vetter · 12 years ago
  81. 7a7d1fb drm/i915: Fix SDVO connector and encoder get_hw_state functions by Egbert Eich · 12 years ago
  82. 999bcde drm/i915: Add a pipeless ivybridge configuration by Ben Widawsky · 12 years ago
  83. ce1bb32 drm/i915: Set PCH_NOP by Ben Widawsky · 12 years ago
  84. 88a2b2a drm/i915: Don't wait for PCH on reset by Ben Widawsky · 12 years ago
  85. ab5c608 drm/i915: Don't touch South Display when PCH_NOP by Ben Widawsky · 12 years ago
  86. 40c7ead drm/i915: PCH_NOP by Ben Widawsky · 12 years ago
  87. e3c7475 drm/i915: Support PCH no display by Ben Widawsky · 12 years ago
  88. bae3699 drm/i915: info level for simulated gpu hang dmesg notice by Daniel Vetter · 12 years ago
  89. 57c2196 drm/i915: revert eDP bpp clamping code changes by Daniel Vetter · 12 years ago
  90. 2af8898 Revert "drm/i915: fix DP get_hw_state return value" by Daniel Vetter · 12 years ago
  91. 83a2af8 drm/i915: Don't use the HDMI port color range bit on Valleyview by Ville Syrjälä · 12 years ago
  92. 9c8e09b drm/i915: Set PIPECONF color range bit on Valleyview by Ville Syrjälä · 12 years ago
  93. 84b046f drm/i915: extract i9xx_set_pipeconf by Daniel Vetter · 12 years ago
  94. 9e9dd0e drm/i915: Add no-lvds quirk for Fujitsu Esprimo Q900 by Christian Lamparter · 12 years ago
  95. f47709a drm/i915: create pipe_config->dpll for clock state by Daniel Vetter · 12 years ago
  96. 88adfff drm/i915: hw readout support for ->has_pch_encoders by Daniel Vetter · 12 years ago
  97. 0e8ffe1 drm/i915: add hw state readout/checking for pipe_config by Daniel Vetter · 12 years ago
  98. 8b47047 drm/i915: rip out superflous is_dp&is_cpu_edp tracking by Daniel Vetter · 12 years ago
  99. 947978f drm/i915: remove leaky eDP functions by Daniel Vetter · 12 years ago
  100. df92b1e drm/i915: track dp target_clock in pipe_config by Daniel Vetter · 12 years ago