Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm-4.19 / 608c1a526c99d1858b02d035657e28c9837667a5 / drivers / gpu / drm / i915 / intel_runtime_pm.c
  1. 0a9d2be drm/i915/skl: Making DC6 entry is the last call in suspend flow. by Animesh Manna · 9 years ago
  2. 3be60de drm/i915: Skip CHV PHY asserts until PHY has been fully reset by Ville Syrjälä · 9 years ago
  3. 165ed87c drm/i915: fixup runtime PM handling v2 by Jesse Barnes · 9 years ago
  4. 08aef7c drm/i915/skl: Block disable call for pw1 if dmc firmware is present. by Animesh Manna · 9 years ago
  5. 6ff8ab0 drm/i915: make CSR firmware messages less verbose by Jesse Barnes · 9 years ago
  6. e93c28f Merge tag 'drm-intel-next-fixes-2015-09-02' into drm-intel-next-queued by Daniel Vetter · 9 years ago
  7. 3014227 drm/i915: Add CHV PHY LDO power sanity checks by Ville Syrjälä · 9 years ago
  8. 6669e39 drm/i915: Add some CHV DPIO lane power state asserts by Ville Syrjälä · 9 years ago
  9. d8e19f9 drm/i915/skl: Adding DDI_E power well domain by Xiong Zhang · 9 years ago
  10. 3e28878 drm/i915: Force CL2 off in CHV x1 PHY by Ville Syrjälä · 9 years ago
  11. ee27921 drm/i915: Enable DPIO SUS clock gating on CHV by Ville Syrjälä · 9 years ago
  12. b0b3384 drm/i915: Trick CL2 into life on CHV when using pipe B with port B by Ville Syrjälä · 9 years ago
  13. e0fce78 drm/i915: Implement PHY lane power gating for CHV by Ville Syrjälä · 9 years ago
  14. 5a8fbb7 drm/i915: Move DPLL ref/cri/VGA mode frobbing to the disp2d well enable by Ville Syrjälä · 9 years ago
  15. 770effb drm/i915: Add locking around chv_phy_control_init() by Ville Syrjälä · 9 years ago
  16. dcddab3 drm/i915: Extract a intel_power_well_disable() function by Damien Lespiau · 9 years ago
  17. e8ca932 drm/i915: Extract a intel_power_well_enable() function by Damien Lespiau · 9 years ago
  18. 2be7d54 drm/i915: Refactor VLV display power well init/deinit by Ville Syrjälä · 9 years ago
  19. 8fcd5cd drm/i915: Simplify CHV pipe A power well code by Ville Syrjälä · 9 years ago
  20. 60bfe44 drm/i915: Apply OCD to VLV/CHV DPLL defines by Ville Syrjälä · 9 years ago
  21. b8afb91 drm/i915: Keep GMCH DPLL VGA mode always disabled by Ville Syrjälä · 9 years ago
  22. fde61e4 drm/i915: Throw out WIP CHV power well definitions by Ville Syrjälä · 10 years ago
  23. bc28454 drm/i915: Use the default 600ns LDO programming sequence delay by Ville Syrjälä · 10 years ago
  24. 7e35ab8 drm/i915: Fix typo in intel_runtime_pm.c by Masanari Iida · 10 years ago
  25. 71849b6 Revert "drm/i915: Hack to tie both common lanes together on chv" by Ville Syrjälä · 10 years ago
  26. 7072246 drm/i915: Work around DISPLAY_PHY_CONTROL register corruption on CHV by Ville Syrjälä · 10 years ago
  27. 6222709 drm/i915/skl: Make the Misc I/O power well part of the PLLS domain by Damien Lespiau · 10 years ago
  28. aeaa212 drm/i915/skl: Add the INIT power domain to the MISC I/O power well by Damien Lespiau · 10 years ago
  29. 93c7cb6 drm/i915/skl: Assert the requirements to enter or exit DC6. by Suketu Shah · 10 years ago
  30. 74b4f37 Implement enable/disable for Display C6 state by A.Sunil Kamath · 10 years ago
  31. f75a198 drm/i915/skl: Add DC6 Trigger sequence. by Suketu Shah · 10 years ago
  32. 5aefb23 drm/i915/skl: Assert the requirements to enter or exit DC5. by Suketu Shah · 10 years ago
  33. 6b457d3 drm/i915/skl: Implement enable/disable for Display C5 state. by A.Sunil Kamath · 10 years ago
  34. dc17430 drm/i915/skl: Add DC5 Trigger Sequence by Suketu Shah · 10 years ago
  35. 664326f drm/i915/bxt: Implement enable/disable for Display C9 state by A.Sunil Kamath · 10 years ago
  36. 0b4a2a3 drm/i915/bxt: Define BXT power domains by Satheeshakrishna M · 10 years ago
  37. ca2b140 drm/i915: Spelling s/auxilliary/auxiliary/ by Geert Uytterhoeven · 10 years ago
  38. 1d2b952 drm/i915/skl: Restore the DDI translation tables when enabling PW1 by Damien Lespiau · 10 years ago
  39. 2540039 drm/i915: Remove unused condition in hsw_power_well_post_enable() by Damien Lespiau · 10 years ago
  40. d14c034 drm/i915/skl: Restore pipe interrupt registers after power well enabling by Damien Lespiau · 10 years ago
  41. 510e6fd drm/i915/skl: Mirror what we do on HSW for the power well enable log message by Damien Lespiau · 10 years ago
  42. 2a51835 drm/i915/skl: Introduce enable_requested and is_enabled in the power well code by Damien Lespiau · 10 years ago
  43. 4c6c03b drm/i915/skl: Make gen8_irq_power_well_post_enable() take a pipe mask by Damien Lespiau · 10 years ago
  44. 94dd513 drm/i915/skl: Implementation of SKL display power well support by Satheeshakrishna M · 10 years ago
  45. 1407121 drm/i915/skl: Adding power domains for AUX controllers by Satheeshakrishna M · 10 years ago
  46. 0a87a2d Merge tag 'topic/i915-hda-componentized-2015-01-12' into drm-intel-next-queued by Daniel Vetter · 10 years ago
  47. fcf3aac drm/i915: remove unused power_well/get_cdclk_freq api by Imre Deak · 10 years ago
  48. 7f1241e drm/i915: Kill check_power_well() calls by Ville Syrjälä · 10 years ago
  49. e2c719b drm/i915: tame the chattermouth (v2) by Rob Clark · 10 years ago
  50. f61ccae drm/i915: Fix short description of intel_display_power_is_enabled() by Damien Lespiau · 10 years ago
  51. afd6275 drm/i915: Reinit display irqs and hpd from chv pipe-a power well by Ville Syrjälä · 10 years ago
  52. baa4e57 drm/i915: Enable pipe-a power well on chv by Ville Syrjälä · 10 years ago
  53. 5d93a6e drm/i915: Do vlv cmnlane toggle w/a in more cases by Ville Syrjälä · 10 years ago
  54. 6d729bf drm/i915: only run hsw_power_well_post_enable when really needed by Paulo Zanoni · 10 years ago
  55. b963291 drm/i915: Use dev_priv instead of dev in irq setup functions by Daniel Vetter · 10 years ago
  56. e4e7684 drm/i915: Kerneldoc for intel_runtime_pm.c by Daniel Vetter · 10 years ago
  57. 41373cd drm/i915: Call runtime_pm_disable directly by Daniel Vetter · 10 years ago
  58. d9bc89d9 drm/i915: Move intel_display_set_init_power to intel_runtime_pm.c by Daniel Vetter · 10 years ago
  59. f458ebb drm/i915: Bikeshed rpm functions name a bit. by Daniel Vetter · 10 years ago
  60. 9c065a7 drm/i915: Extract intel_runtime_pm.c by Daniel Vetter · 10 years ago