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gerrit-public.fairphone.software
/
kernel
/
msm-4.19
/
61bf86ad86443a710ae7eed372cccb8ed5038eda
/
drivers
/
gpu
/
drm
/
i915
/
i915_reg.h
884020b
drm/i915: Invalidate TLBs for the rings after a reset
by Chris Wilson
· 11 years ago
0ce99f7
drm/i915: fix gen4 digital port hotplug definitions
by Daniel Vetter
· 11 years ago
a0de80a
drm/i915: Fix context sizes on HSW
by Ben Widawsky
· 11 years ago
921c3b6
drm/i915: Fix VLV sprite register offsets
by Ville Syrjälä
· 11 years ago
4abb2c3
drm/i915: s/LFP/LPF in DPIO PLL register names
by Ville Syrjälä
· 11 years ago
4f7fd70
drm/i915: Fix up sdvo hpd pins for i965g/gm
by Daniel Vetter
· 11 years ago
3eff4fa
drm/i915: explicitly set up PIPECONF (and gamma table) on haswell
by Daniel Vetter
· 11 years ago
e0d8d59
drm/i915: Try harder to disable trickle feed on VLV
by Ville Syrjälä
· 11 years ago
e9a632a
drm/i915: scrap register address storage
by Daniel Vetter
· 11 years ago
1188739
drm/i915: refactor PCH_DPLL_SEL #defines
by Daniel Vetter
· 11 years ago
fd3da6c
drm/i915: WA: FBC Render Nuke.
by Rodrigo Vivi
· 11 years ago
5434fd9
Revert "drm/i915: Include display_mmio_offset in sequencer index/data registers"
by Ville Syrjälä
· 11 years ago
d7fe0cc
drm/i915: Fix DSPCLK_GATE_D for VLV
by Ville Syrjälä
· 11 years ago
42db64e
drm/i915: implement IPS feature
by Paulo Zanoni
· 11 years ago
12638c5
drm/i915: Enable vebox interrupts
by Ben Widawsky
· 11 years ago
cc609d5
drm/i915: consolidate interrupt naming scheme
by Ben Widawsky
· 11 years ago
4848405
drm/i915: make PM interrupt writes non-destructive
by Ben Widawsky
· 11 years ago
cca32e9
drm/i915: properly set HSW WM_LP watermarks
by Paulo Zanoni
· 11 years ago
801bcff
drm/i915: properly set HSW WM_PIPE registers
by Paulo Zanoni
· 11 years ago
9a8a221
drm/i915: Vebox ringbuffer init
by Ben Widawsky
· 11 years ago
1950de1
drm/i915: Add VECS semaphore bits
by Ben Widawsky
· 11 years ago
ad776f8
drm/i915: Semaphore MBOX update generalization
by Ben Widawsky
· 11 years ago
5586181
drm/i915: Comments for semaphore clarification
by Ben Widawsky
· 11 years ago
5a09ae9f
drm/i915: refactor VLV IOSF sideband accessors to use one helper
by Jani Nikula
· 11 years ago
90a8864
drm/i915: set FORCE_ARB_IDLE_PLANES workaround
by Paulo Zanoni
· 11 years ago
e1b73cb
Merge tag 'v3.10-rc2' into drm-intel-next-queued
by Daniel Vetter
· 11 years ago
d89f207
drm/i915: HSW FBC WaFbcDisableDpfcClockGating
by Rodrigo Vivi
· 11 years ago
2855416
drm/i915: HSW FBC WaFbcAsynchFlipDisableFbcQueue
by Rodrigo Vivi
· 11 years ago
abe959c
drm/i915: Add support for FBC on Ivybridge.
by Rodrigo Vivi
· 11 years ago
c9cddff
drm/i915: BIOS and power context stolen mem handling for VLV v7
by Jesse Barnes
· 11 years ago
c4ae25e
Revert "drm/i915: Calculate correct stolen size for GEN7+"
by Ben Widawsky
· 11 years ago
e3b95f1
drm/i915: Apply OCD to data/link m/n register #defines
by Daniel Vetter
· 11 years ago
275f01b2
drm/i915: PCH_ prefix for transcoder timings
by Daniel Vetter
· 11 years ago
ab9412b
drm/i915: s/TRANSCONF/PCH_TRANSCONF/
by Daniel Vetter
· 11 years ago
17aa6be
drm/i915: simplify DP/DDI port width macros
by Daniel Vetter
· 11 years ago
1bd1bd8
drm/i915: hw state readout support for pipe timings
by Daniel Vetter
· 11 years ago
7241920
drm/i915: hw state readout support for fdi m/n
by Daniel Vetter
· 11 years ago
627eb5a
drm/i915: hw state readout support for pipe_config->fdi_lanes
by Daniel Vetter
· 11 years ago
35ffda4
drm/i915: hsw backlight registers need transcoder instead of pipe
by Jani Nikula
· 11 years ago
a65851a
drm/i915: Make data/link N value power of two
by Ville Syrjälä
· 11 years ago
29a397b
drm/i915: Move the CSC_MODE bits next to the register
by Ville Syrjälä
· 11 years ago
de032bf
drm/i915: print Gen5+ CPU/PCH poison interrupts
by Paulo Zanoni
· 11 years ago
8664281
drm/i915: report Gen5+ CPU and PCH FIFO underruns
by Paulo Zanoni
· 11 years ago
598fac6
drm/i915: magic VLV PLL registers in the dpio sideband
by Daniel Vetter
· 11 years ago
0a073b8
drm/i915: turbo & RC6 support for VLV v7
by Jesse Barnes
· 11 years ago
dc4bd2d
drm/i915: preserve the PBC bits of TRANS_CHICKEN2
by Paulo Zanoni
· 11 years ago
3f704fa
drm/i915: set CPT FDI RX polarity bits based on VBT
by Paulo Zanoni
· 11 years ago
3ebecd0
drm/i915: Scale ring, rather than ia, frequency on Haswell
by Chris Wilson
· 11 years ago
3a06247
drm/i915: Increase max fence pitch limit to 256KB on IVB+
by Ville Syrjälä
· 11 years ago
a6f429a
drm/i915: Configure GAM_ECOCHK appropriatly for Gen7
by Ville Syrjälä
· 11 years ago
3b9d788
drm/i915: Add ECOBITS_SNB_BIT
by Ville Syrjälä
· 11 years ago
88a2b2a
drm/i915: Don't wait for PCH on reset
by Ben Widawsky
· 11 years ago
a0e4e19
drm/i915: add Punit read/write routines for VLV v2
by Jesse Barnes
· 11 years ago
453c542
drm/i915: panel power sequencing for VLV eDP v2
by Jesse Barnes
· 11 years ago
7f1f385
drm/i915: sprite support for ValleyView v4
by Jesse Barnes
· 11 years ago
8a5c2ae
drm/i915: fix ILK GPU reset for render
by Jesse Barnes
· 11 years ago
73c352a
drm/i915: wire up SDVO hpd support on cpt/ppt
by Daniel Vetter
· 11 years ago
e5868a3
DRM/i915: Convert HPD interrupts to make use of HPD pin assignment in encoders (v2)
by Egbert Eich
· 12 years ago
92bd1bf
drm/i915: HSW PM Frequency bits fix
by Rodrigo Vivi
· 11 years ago
e3dff58
drm/i915: Implement WaSwitchSolVfFArbitrationPriority
by Ben Widawsky
· 12 years ago
12569ad
drm/i915: DSPFW and BLC regs are in the display offset range
by Jesse Barnes
· 12 years ago
ed5de39
drm/i915: add media well to VLV force wake routines v2
by Jesse Barnes
· 12 years ago
0d4a42f
Merge tag 'v3.9-rc3' into drm-intel-next-queued
by Daniel Vetter
· 12 years ago
d62b489
drm/i915: allow force wake at init time on VLV v2
by Jesse Barnes
· 12 years ago
60222c0
drm/i915: Fix incorrect definition of ADPA HSYNC and VSYNC bits
by Patrik Jakobsson
· 12 years ago
4f3a8bc
drm/i915: rename some HDMI bit definitions
by Paulo Zanoni
· 12 years ago
dc0fa71
drm/i915: remove duplicated SDVO/HDMI bit definitions
by Paulo Zanoni
· 12 years ago
c20cd31
drm/i915: unify the definitions of the HDMI/SDVO register
by Paulo Zanoni
· 12 years ago
e2debe9
drm/i915: clarify confusion between SDVO and HDMI registers
by Paulo Zanoni
· 12 years ago
7d9bceb
drm/i915: Use cpu_transcoder for HSW_TVIDEO_DIP_* instead of pipe
by Rodrigo Vivi
· 12 years ago
90a72f8
drm/i915: Refactor gen2 to gen4 vblank interrupt handling
by Ville Syrjälä
· 12 years ago
3f1e109
drm/i915: use FPGA_DBG for the "unclaimed register" checks
by Paulo Zanoni
· 12 years ago
86d3efc
drm/i915: Implement pipe CSC based limited range RGB output
by Ville Syrjälä
· 12 years ago
b9e1faa
drm/i915: Fix PIPE_CONTROL DW/QW write through global GTT on IVB+
by Ville Syrjälä
· 12 years ago
876a8cd
drm/i915: Preserve the DDI link reversal configuration
by Damien Lespiau
· 12 years ago
3e68320
drm/i915: Preserve the FDI line reversal override bit on CPT
by Damien Lespiau
· 12 years ago
1d7aaa0
drm/i915: detect wrong MCH watermark values
by Daniel Vetter
· 12 years ago
26739f1
drm/i915: unify HDMI/DP hpd definitions
by Daniel Vetter
· 12 years ago
7083e05
drm/i915: Fix RC6VIDS encode/decode
by Ben Widawsky
· 12 years ago
6dc1c49
Merge branch 'fbcon-locking-fixes' of ssh://people.freedesktop.org/~airlied/linux into drm-next
by Dave Airlie
· 12 years ago
766aa1c
drm/i915: Introduce i915_vgacntrl_reg()
by Ville Syrjälä
· 12 years ago
f82855d
drm/i915: Fix CAGF for HSW
by Ben Widawsky
· 12 years ago
41c0b3a
drm/i915: Implement WaVSRefCountFullforceMissDisable
by Ben Widawsky
· 12 years ago
fa42e23
drm/i915: fix intel_init_power_wells
by Paulo Zanoni
· 12 years ago
80a75f7
drm/i915: SWF screatch registers need an offset on VLV
by Ville Syrjälä
· 12 years ago
56a12a5
drm/i915: Include display_mmio_offset in sequencer index/data registers
by Ville Syrjälä
· 12 years ago
fc2de40
drm/i915: PLL registers need an offset on VLV
by Ville Syrjälä
· 12 years ago
54d9d49
drm/i915: DPIO registers are VLV only and need an offset
by Ville Syrjälä
· 12 years ago
ff76301
drm/i915: Spell out VLV_DISPLAY_BASE for interrupt registers
by Ville Syrjälä
· 12 years ago
07ec7ec
drm/i915: Make VLV_GUNIT_CLOCK_GATE register value more readable
by Ville Syrjälä
· 12 years ago
d88b227
drm/i915: FB_BLC_SELF_VLV is VLV only and needs an offset
by Ville Syrjälä
· 12 years ago
4b05998
drm/i915: Pipe palette registers need an offset on VLV
by Ville Syrjälä
· 12 years ago
4e8e7eb
drm/i915: Pipe timing registers need an offset on VLV
by Ville Syrjälä
· 12 years ago
67d62c5
drm/i915: PORT_HOTPLUG registers need an offset on VLV
by Ville Syrjälä
· 12 years ago
7e470ab
drm/i915: Panel fitter registers need an offset on VLV
by Ville Syrjälä
· 12 years ago
b41fbda
drm/i915: DPFLIPSTAT and DPINVGTT registers are VLV only and need an offset
by Ville Syrjälä
· 12 years ago
90f7da3
drm/i915: DSPFW registers need an offset on VLV
by Ville Syrjälä
· 12 years ago
8f6d8ee
drm/i915: VLV_DDL is VLV only and needs an offset
by Ville Syrjälä
· 12 years ago
9dc33f3
drm/i915: Cursor registers need an offset on VLV
by Ville Syrjälä
· 12 years ago
0c3870e
drm/i915: Pipe registers need an offset on VLV
by Ville Syrjälä
· 12 years ago
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