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gerrit-public.fairphone.software / kernel / msm-4.19 / fc58acdbf153f12783b80cb19c04cc9de121b518 / arch / mips / include / asm / cpu-features.h
  1. ee80f7c7 MIPS: Add detection of DSP ASE Revision 2. by Steven J. Hill · 12 years ago
  2. da4b62c MIPS: perf: Add cpu feature bit for PCI (performance counter interrupt) by Al Cooper · 12 years ago
  3. 05857c6 MIPS: Replace 'kernel_uses_smartmips_rixi' with 'cpu_has_rixi'. by Steven J. Hill · 12 years ago
  4. b2ab4f0 MIPS: Add base architecture support for RI and XI. by Steven J. Hill · 12 years ago
  5. 417a5eb MIPS: Update comment for cpu_has_clo_clz by Ralf Baechle · 14 years ago
  6. 6dd9344 MIPS: Implement Read Inhibit/eXecute Inhibit by David Daney · 15 years ago
  7. 91dfc42 MIPS: 64-bit: Detect virtual memory size by Guenter Roeck · 15 years ago
  8. b791d11 MIPS: Allow kernel use of LL/SC to be separate from the presence of LL/SC. by David Daney · 15 years ago
  9. fbeda19 MIPS: Allow CPU specific overriding of CP0 hwrena impl bits. by David Daney · 16 years ago
  10. 41f0e4d MIPS: Allow R2 CPUs to turn off generation of 'ehb' instructions. by David Daney · 16 years ago
  11. 47740eb MIPS: Enable CLO / CLZ instructions via separate CPU property by Ralf Baechle · 16 years ago
  12. 47d979e MIPS: Hook Cavium OCTEON cache init into cache.c by David Daney · 16 years ago
  13. c46b302 MIPS: New feature test macro cpu_has_mips_r by Ralf Baechle · 16 years ago
  14. 384740d MIPS: Move headfiles to new location below arch/mips/include by Ralf Baechle · 16 years ago[Renamed from include/asm-mips/cpu-features.h]
  15. 54fd644 [MIPS] Fix use of smp_processor_id() in preemptible code. by Pavel Kiryukhin · 17 years ago
  16. 10cc352 [MIPS] Allow hardwiring of the CPU type to a single type for optimization. by Ralf Baechle · 17 years ago
  17. 641e97f [MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code. by Ralf Baechle · 17 years ago
  18. a369202 [MIPS] Enable support for the userlocal hardware register by Ralf Baechle · 17 years ago
  19. 53dc802 [MIPS] FPU ownership management & preemption fixes by Atsushi Nemoto · 18 years ago
  20. fc5d2d2 [MIPS] Use the proper technical term for naming some of the cache macros. by Ralf Baechle · 18 years ago
  21. 2e128de [MIPS] Default cpu_has_mipsmt to a runtime check by Chris Dearman · 18 years ago
  22. f41ae0b [MIPS] Fix configuration of R2 CPU features and multithreading. by Ralf Baechle · 18 years ago
  23. 62c4f0a Don't include linux/config.h from anywhere else in include/ by David Woodhouse · 19 years ago
  24. f088fc8 [MIPS] FPU affinity for MT ASE. by Ralf Baechle · 19 years ago
  25. de62893 [MIPS] local_r4k_flush_cache_page fix by Atsushi Nemoto · 19 years ago
  26. 0401572 MIPS: Reorganize ISA constants strictly as bitmasks. by Ralf Baechle · 19 years ago
  27. b4672d3 MIPS: Introduce machinery for testing for MIPSxxR1/2. by Ralf Baechle · 19 years ago
  28. 02cf211 Cleanup the mess in cpu_cache_init. by Ralf Baechle · 19 years ago
  29. 8f40611 Detect the MIPS R2 vectored interrupt, external interrupt controller by Ralf Baechle · 19 years ago
  30. 02416dc Redo RM9000 workaround which along with other DSP ASE changes was by Ralf Baechle · 19 years ago
  31. e50c0a8 Support the MIPS32 / MIPS64 DSP ASE. by Ralf Baechle · 19 years ago
  32. 4194318 Cleanup decoding of MIPSxx config registers. by Ralf Baechle · 20 years ago
  33. 875d43e [PATCH] mips: clean up 32/64-bit configuration by Ralf Baechle · 19 years ago
  34. 1da177e Linux-2.6.12-rc2 by Linus Torvalds · 20 years ago