| commit | 444f9a8030ecda8dedd374fc3efed03d9f20e9cb | [log] [tgz] |
|---|---|---|
| author | Joseph Lo <josephl@nvidia.com> | Mon Aug 12 17:40:01 2013 +0800 |
| committer | Stephen Warren <swarren@nvidia.com> | Mon Aug 12 12:22:39 2013 -0600 |
| tree | 396cc998a2265b70ef00d80c2b88f4f62132fe56 | |
| parent | 5b795d051c61862cebf4f1d55edab6e9b3383b44 [diff] |
ARM: tegra: config the polarity of the request of sys clock When suspending to LP1 mode, the SYSCLK will be clock gated. And different board may have different polarity of the request of SYSCLK, this patch configure the polarity from the DT for the board. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>