tree 76265f416bbaef69fb1bd94b636ec2ad77d48a97
parent 1ca04065c3569beb42b9376952df8c96f430f753
author Mark Brown <broonie@opensource.wolfsonmicro.com> 1250531504 +0100
committer Mark Brown <broonie@opensource.wolfsonmicro.com> 1250531624 +0100

ASoC: Fix WM8993 MCLK configuration for high frequency MCLKs

When used without the PLL we were accidentally clearing the MCLK/2
divider, resulting in a double rate SYSCLK when the divider should
have been used.

Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>