| commit | 5cbdcc2f49b4a8372052952799d2cb1de387443b | [log] [tgz] |
|---|---|---|
| author | Huang, Xiong <xiong@qca.qualcomm.com> | Wed Apr 18 22:01:27 2012 +0000 |
| committer | David S. Miller <davem@davemloft.net> | Thu Apr 19 20:14:20 2012 -0400 |
| tree | 7a6ad570c04d880a26febdc1ad613e8a3a9a90de | |
| parent | 7f5544d6693ab2593b4f13521a577387f3be6b2f [diff] |
atl1c: clear bit MASTER_CTRL_CLK_SEL_DIS in atl1c_pcie_patch bit MASTER_CTRL_CLK_SEL_DIS could be set before enter suspend clear it after resume to enable pclk(PCIE clock) switch to low frequency(25M) in some circumstances to save power. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>