| commit | 034fbcc3d8a5dff5d3df5a4ad6bf9cc0b01bd970 | [log] [tgz] |
|---|---|---|
| author | Rob Clark <robdclark@gmail.com> | Wed Jun 25 09:54:36 2014 -0400 |
| committer | Rob Clark <robdclark@gmail.com> | Mon Aug 04 11:55:28 2014 -0400 |
| tree | 9c27803c6c44f446ed71680fb058927bbc08dd98 | |
| parent | 89301471e6bf942c026d6ebfcbc9a6a937cc6865 [diff] |
drm/msm: hdmi phy 8960 phy pll On downstream kernel the clk driver directly bangs hdmi phy registers. For upstream kernel, we need to model this as a clock and register with the clock framework. Signed-off-by: Rob Clark <robdclark@gmail.com>