Merge "soc: qcom: service-notifier: Create qmi_client per service path"
diff --git a/Documentation/devicetree/bindings/power/supply/qcom/qpnp-qg.txt b/Documentation/devicetree/bindings/power/supply/qcom/qpnp-qg.txt
index 0da71a3..83f964d 100644
--- a/Documentation/devicetree/bindings/power/supply/qcom/qpnp-qg.txt
+++ b/Documentation/devicetree/bindings/power/supply/qcom/qpnp-qg.txt
@@ -295,6 +295,13 @@
attempted by QG. If not defined the value defaults
to 10%.
+- qcom,esr-chg-min-ibat-ua
+ Usage: optional
+ Value type: <int>
+ Definition: Minimun charge current (IBAT) in uA at which ESR will
+ be attempted. If not specified the default value is
+ in -450mA.
+
- qcom,qg-ext-sns
Usage: optional
Value type: <bool>
diff --git a/Documentation/devicetree/bindings/power/supply/qcom/qpnp-smb5.txt b/Documentation/devicetree/bindings/power/supply/qcom/qpnp-smb5.txt
index 65dcf59..0b6daab 100644
--- a/Documentation/devicetree/bindings/power/supply/qcom/qpnp-smb5.txt
+++ b/Documentation/devicetree/bindings/power/supply/qcom/qpnp-smb5.txt
@@ -107,6 +107,27 @@
then charge inhibit will be disabled by default.
Allowed values are: 50, 100, 200, 300.
+- qcom,chg-term-src
+ Usage: optional
+ Value type: <u32>
+ Definition: Specify either the ADC or analog comparators to be used in order
+ to set threshold values for charge termination current.
+ 0 - Unspecified
+ 1 - Select ADC comparator
+ 2 - Select ANALOG comparator
+
+- qcom,chg-term-current-ma
+ Usage: optional
+ Value type: <u32>
+ Definition: When ADC comparator is selected as qcom,chg-term-src, this
+ parameter should be set to the desired upper threshold.
+
+- qcom,chg-term-base-current-ma
+ Usage: optional
+ Value type: <u32>
+ Definition: When ADC comparator is selected as qcom,chg-term-src, this
+ parameter should be set to the desired lower threshold.
+
- qcom,auto-recharge-soc
Usage: optional
Value type: <u32>
diff --git a/arch/arm/boot/dts/qcom/sdxpoorwills-mtp.dts b/arch/arm/boot/dts/qcom/sdxpoorwills-mtp.dts
index ae3de38..3ae5b2c 100644
--- a/arch/arm/boot/dts/qcom/sdxpoorwills-mtp.dts
+++ b/arch/arm/boot/dts/qcom/sdxpoorwills-mtp.dts
@@ -20,3 +20,7 @@
"qcom,sdxpoorwills", "qcom,mtp";
qcom,board-id = <8 0x102>;
};
+
+&qcom_seecom {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/qcom/sdxpoorwills-usb.dtsi b/arch/arm/boot/dts/qcom/sdxpoorwills-usb.dtsi
index 9f74227..642a541 100644
--- a/arch/arm/boot/dts/qcom/sdxpoorwills-usb.dtsi
+++ b/arch/arm/boot/dts/qcom/sdxpoorwills-usb.dtsi
@@ -44,8 +44,8 @@
clock-names = "core_clk", "iface_clk", "utmi_clk", "sleep_clk",
"cfg_ahb_clk", "xo";
- qcom,core-clk-rate = <133333333>;
- qcom,core-clk-rate-hs = <66666667>;
+ qcom,core-clk-rate = <120000000>; /* MAX SVS */
+ qcom,core-clk-rate-hs = <75000000>; /* MAX LOW SVS */
resets = <&clock_gcc GCC_USB30_BCR>;
reset-names = "core_reset";
diff --git a/arch/arm/boot/dts/qcom/sdxpoorwills.dtsi b/arch/arm/boot/dts/qcom/sdxpoorwills.dtsi
index 3e31826..2014885 100644
--- a/arch/arm/boot/dts/qcom/sdxpoorwills.dtsi
+++ b/arch/arm/boot/dts/qcom/sdxpoorwills.dtsi
@@ -1359,6 +1359,8 @@
vreg_emac_phy-supply = <&vreg_emac_phy>;
vreg_rgmii_io_pads-supply = <&vreg_rgmii_io_pads>;
gdsc_emac-supply = <&gdsc_emac>;
+ mboxes = <&qmp_aop 0>;
+ mbox-names = "emac_aop";
io-macro-info {
io-macro-bypass-mode = <0>;
io-interface = "rgmii";
diff --git a/arch/arm/configs/sdm670_defconfig b/arch/arm/configs/sdm670_defconfig
index ca82f05..2fda0e2 100644
--- a/arch/arm/configs/sdm670_defconfig
+++ b/arch/arm/configs/sdm670_defconfig
@@ -334,7 +334,6 @@
CONFIG_MFD_I2C_PMIC=y
CONFIG_MFD_SPMI_PMIC=y
CONFIG_MFD_SYSCON=y
-CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_PROXY_CONSUMER=y
CONFIG_REGULATOR_QPNP_LABIBB=y
@@ -352,7 +351,10 @@
CONFIG_MSM_SDE_ROTATOR=y
CONFIG_MSM_SDE_ROTATOR_EVTLOG_DEBUG=y
CONFIG_QCOM_KGSL=y
-CONFIG_FB=y
+CONFIG_DRM=y
+CONFIG_DRM_SDE_EVTLOG_DEBUG=y
+CONFIG_DRM_SDE_RSC=y
+CONFIG_DRM_LT_LT9611=y
CONFIG_FB_VIRTUAL=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
@@ -452,6 +454,7 @@
CONFIG_CLOCK_CPU_OSM=y
CONFIG_MSM_GPUCC_SDM845=y
CONFIG_MSM_CLK_AOP_QMP=y
+CONFIG_QCOM_MDSS_PLL=y
CONFIG_REMOTE_SPINLOCK_MSM=y
CONFIG_MSM_QMP=y
CONFIG_ARM_SMMU=y
@@ -466,7 +469,6 @@
CONFIG_QCOM_LLCC_PERFMON=m
CONFIG_MSM_SERVICE_LOCATOR=y
CONFIG_MSM_SERVICE_NOTIFIER=y
-CONFIG_QCOM_SCM=y
CONFIG_MSM_BOOT_STATS=y
CONFIG_MSM_CORE_HANG_DETECT=y
CONFIG_MSM_GLADIATOR_HANG_DETECT=y
@@ -532,7 +534,6 @@
CONFIG_FUSE_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
CONFIG_ECRYPT_FS=y
CONFIG_ECRYPT_FS_MESSAGING=y
# CONFIG_NETWORK_FILESYSTEMS is not set
diff --git a/arch/arm/configs/sdxpoorwills-perf_defconfig b/arch/arm/configs/sdxpoorwills-perf_defconfig
index 258b7a2..d5930a7 100644
--- a/arch/arm/configs/sdxpoorwills-perf_defconfig
+++ b/arch/arm/configs/sdxpoorwills-perf_defconfig
@@ -299,6 +299,8 @@
CONFIG_USB_STORAGE_CYPRESS_ATACB=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_MSM=y
+CONFIG_USB_EHSET_TEST_FIXTURE=y
+CONFIG_USB_LINK_LAYER_TEST=y
CONFIG_NOP_USB_XCEIV=y
CONFIG_USB_MSM_SSPHY_QMP=y
CONFIG_MSM_HSUSB_PHY=y
diff --git a/arch/arm/configs/sdxpoorwills_defconfig b/arch/arm/configs/sdxpoorwills_defconfig
index 687885a..f5abbb4 100644
--- a/arch/arm/configs/sdxpoorwills_defconfig
+++ b/arch/arm/configs/sdxpoorwills_defconfig
@@ -300,6 +300,7 @@
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_MSM=y
CONFIG_USB_EHSET_TEST_FIXTURE=y
+CONFIG_USB_LINK_LAYER_TEST=y
CONFIG_NOP_USB_XCEIV=y
CONFIG_USB_MSM_SSPHY_QMP=y
CONFIG_MSM_HSUSB_PHY=y
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index a03a99a..3b2f4ce 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -239,15 +239,13 @@
return 0;
}
-static DECLARE_COMPLETION(cpu_died);
-
/*
* called on the thread which is asking for a CPU to be shutdown -
* waits until shutdown has completed, or it is timed out.
*/
void __cpu_die(unsigned int cpu)
{
- if (!wait_for_completion_timeout(&cpu_died, msecs_to_jiffies(5000))) {
+ if (!cpu_wait_death(cpu, 5)) {
pr_err("CPU%u: cpu didn't die\n", cpu);
return;
}
@@ -293,7 +291,7 @@
* this returns, power and/or clocks can be removed at any point
* from this CPU and its cache by platform_cpu_kill().
*/
- complete(&cpu_died);
+ (void)cpu_report_death();
/*
* Ensure that the cache lines associated with that completion are
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index bc6defc..e4d6200 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -296,6 +296,13 @@
endif
ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
+dtbo-$(CONFIG_ARCH_MSM8917) += msm8917-mtp-overlay.dtbo \
+ msm8917-qrd-overlay.dtbo \
+ msm8917-cdp-overlay.dtbo \
+ msm8917-cdp-ext-codec-overlay.dtbo \
+ msm8917-cdp-ml-touch-overlay.dtbo \
+ msm8917-rcm-overlay.dtbo
+
dtbo-$(CONFIG_ARCH_MSM8953) += msm8953-mtp-overlay.dtbo \
msm8953-cdp-overlay.dtbo \
msm8953-rcm-overlay.dtbo \
@@ -334,6 +341,33 @@
sdm429-cdp-overlay.dtbo \
sdm429-qrd-overlay.dtbo
+msm8917-mtp-overlay.dtbo-base := msm8917-pmi8950.dtb \
+ msm8917-pmi8937.dtb \
+ msm8917-pmi8940.dtb
+
+msm8917-qrd-overlay.dtbo-base := msm8917-pmi8937.dtb
+
+msm8917-cdp-ext-codec-overlay.dtbo-base := msm8917-pmi8950.dtb
+
+msm8917-cdp-ml-touch-overlay.dtbo-base := msm8917-pmi8950.dtb
+
+msm8917-cdp-overlay.dtbo-base := msm8917-pmi8950.dtb \
+ msm8917-pmi8937.dtb \
+ msm8917-pmi8940.dtb
+
+msm8917-rcm-overlay.dtbo-base := msm8917-pmi8950.dtb \
+ msm8917-pmi8937.dtb \
+ msm8917-pmi8940.dtb
+
+apq8017-mtp-overlay.dtbo-base := apq8017-pmi8950.dtb \
+ apq8017-pmi8937.dtb
+
+apq8017-cdp-overlay.dtbo-base := apq8017-pmi8950.dtb \
+ apq8017-pmi8937.dtb
+
+apq8017-cdp-wcd-rome-overlay.dtbo-base := apq8017-pmi8950.dtb \
+ apq8017-pmi8937.dtb
+
msm8953-mtp-overlay.dtbo-base := sdm450.dtb \
msm8953.dtb \
apq8053.dtb \
diff --git a/arch/arm64/boot/dts/qcom/apq8009-robot-som-refboard.dts b/arch/arm64/boot/dts/qcom/apq8009-robot-som-refboard.dts
index b999684..ab711dd 100644
--- a/arch/arm64/boot/dts/qcom/apq8009-robot-som-refboard.dts
+++ b/arch/arm64/boot/dts/qcom/apq8009-robot-som-refboard.dts
@@ -371,7 +371,3 @@
&ext_codec {
status = "okay";
};
-
-&blsp1_uart2_hs {
- status = "disabled";
-};
diff --git a/arch/arm64/boot/dts/qcom/apq8017-cdp-overlay.dts b/arch/arm64/boot/dts/qcom/apq8017-cdp-overlay.dts
new file mode 100644
index 0000000..6c8bef4
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/apq8017-cdp-overlay.dts
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "msm8917-cdp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. APQ8017-CDP";
+ qcom,board-id = <1 0>;
+};
+
+&mdss_fb0 {
+ /delete-node/ qcom,cont-splash-memory;
+};
diff --git a/arch/arm64/boot/dts/qcom/apq8017-cdp-wcd-rome-overlay.dts b/arch/arm64/boot/dts/qcom/apq8017-cdp-wcd-rome-overlay.dts
new file mode 100644
index 0000000..055c457
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/apq8017-cdp-wcd-rome-overlay.dts
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "msm8917-cdp.dtsi"
+#include "apq8017-rome.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. APQ8017-CDP \
+ with WCD codec/Rome card";
+ qcom,board-id = <1 2>;
+};
+
+&blsp1_uart1 {
+ status = "ok";
+};
+
+&sdhc_2 {
+ /* device core power supply */
+ /delete-property/vdd-supply;
+ /delete-property/qcom,vdd-voltage-level;
+ /delete-property/qcom,vdd-current-level;
+
+ /* device communication power supply */
+ vdd-io-supply = <&pm8937_l5>;
+ qcom,vdd-io-always-on;
+ qcom,vdd-io-voltage-level = <1800000 1800000>;
+ qcom,vdd-io-current-level = <200 325000>;
+
+ qcom,core_3_0v_support;
+ qcom,nonremovable;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on
+ &sdc2_wlan_gpio_active>;
+ pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off
+ &sdc2_wlan_gpio_sleep>;
+
+ #address-cells = <0>;
+ interrupt-parent = <&sdhc_2>;
+ interrupts = <0 1 2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xffffffff>;
+ interrupt-map = <0 &intc 0 125 0
+ 1 &intc 0 221 0
+ 2 &tlmm 124 0x4>;
+ interrupt-names = "hc_irq", "pwr_irq", "sdiowakeup_irq";
+
+ /delete-property/cd-gpios;
+ /delete-property/qcom,devfreq,freq-table;
+
+ status = "ok";
+
+};
+
+&modem_mem {
+ reg = <0x0 0x86800000 0x0 0x1500000>;
+};
+
+&adsp_fw_mem {
+ reg = <0x0 0x87d00000 0x0 0x1100000>;
+};
+
+&wcnss_fw_mem {
+ reg = <0x0 0x88e00000 0x0 0x700000>;
+};
+
+&secure_mem {
+ status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/qcom/apq8017-mtp-overlay.dts b/arch/arm64/boot/dts/qcom/apq8017-mtp-overlay.dts
new file mode 100644
index 0000000..23bbb0f
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/apq8017-mtp-overlay.dts
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "msm8917-mtp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. APQ8017-MTP";
+ qcom,board-id = <8 0>;
+};
+
+&blsp1_uart1 {
+ status = "ok";
+};
+
+&vendor {
+ mtp_batterydata: qcom,battery-data {
+ qcom,batt-id-range-pct = <15>;
+ #include "batterydata-itech-3000mah.dtsi"
+ #include "batterydata-ascent-3450mAh.dtsi"
+ };
+};
+
+&qpnp_fg {
+ qcom,battery-data = <&mtp_batterydata>;
+};
+
+&qpnp_smbcharger {
+ qcom,battery-data = <&mtp_batterydata>;
+};
+
+&i2c_2 {
+ /* DSI_TO_HDMI I2C configuration */
+ adv7533@39 {
+ compatible = "adv7533";
+ reg = <0x39>;
+ instance_id = <0>;
+ adi,video-mode = <3>; /* 3 = 1080p */
+ adi,main-addr = <0x39>;
+ adi,cec-dsi-addr = <0x3C>;
+ adi,enable-audio;
+ adi,irq-gpio = <&tlmm 0x29 0x2002>;
+ adi,power-down-gpio = <&tlmm 0x7D 0x0>;
+ adi,switch-gpio = <&pm8937_gpios 0x8 0x1>;
+ pinctrl-names = "pmx_adv7533_active",
+ "pmx_adv7533_suspend";
+ pinctrl-0 = <&adv7533_int_active>;
+ pinctrl-1 = <&adv7533_int_suspend>;
+ };
+};
+
+&mdss_dsi {
+ hw-config = "single_dsi";
+};
+
+&mdss_dsi0 {
+ qcom,dsi-pref-prim-pan = <&dsi_adv7533_1080p>;
+ qcom,platform-intf-mux-gpio = <&tlmm 115 0>;
+ status = "ok";
+ qcom,bridge-index = <0>;
+ qcom,pluggable;
+};
+
+&dsi_adv7533_1080p {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+};
diff --git a/arch/arm64/boot/dts/qcom/apq8017-pmi8937.dts b/arch/arm64/boot/dts/qcom/apq8017-pmi8937.dts
new file mode 100644
index 0000000..c060461
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/apq8017-pmi8937.dts
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "apq8017.dtsi"
+#include "msm8917-pmi8937.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. MSM8917 + PMI8937 SOC";
+ compatible = "qcom,msm8917";
+ qcom,pmic-id = <0x10019 0x020037 0x0 0x0>;
+ qcom,pmic-name = "PMI8937";
+};
diff --git a/arch/arm64/boot/dts/qcom/apq8017-pmi8950.dts b/arch/arm64/boot/dts/qcom/apq8017-pmi8950.dts
new file mode 100644
index 0000000..5fc2b60
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/apq8017-pmi8950.dts
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "apq8017.dtsi"
+#include "msm8917-pmi8950.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. MSM8917 + PMI8950 SOC ";
+ compatible = "qcom,msm8917";
+ qcom,pmic-id = <0x10019 0x010011 0x0 0x0>;
+ qcom,pmic-name = "PMI8950";
+};
diff --git a/arch/arm64/boot/dts/qcom/apq8053-dragon-memory.dtsi b/arch/arm64/boot/dts/qcom/apq8053-dragon-memory.dtsi
new file mode 100644
index 0000000..a26926a
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/apq8053-dragon-memory.dtsi
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+&modem_mem {
+ reg = <0x0 0x86c00000 0x0 0x1800000>;
+};
+
+&adsp_fw_mem {
+ reg = <0x0 0x88400000 0x0 0x1100000>;
+};
+
+&wcnss_fw_mem {
+ reg = <0x0 0x89500000 0x0 0x700000>;
+};
diff --git a/arch/arm64/boot/dts/qcom/apq8053-lite-dragon.dtsi b/arch/arm64/boot/dts/qcom/apq8053-lite-dragon.dtsi
index 00dc555..90b1d4f 100644
--- a/arch/arm64/boot/dts/qcom/apq8053-lite-dragon.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8053-lite-dragon.dtsi
@@ -16,6 +16,7 @@
#include "apq8053-camera-sensor-dragon.dtsi"
#include "pmi8950.dtsi"
#include "msm8953-pmi8950.dtsi"
+#include "apq8053-dragon-memory.dtsi"
&soc {
vreg_5p0: vreg_5p0 {
@@ -118,6 +119,10 @@
gpio-key,wakeup;
};
};
+
+ qcom,rmnet-ipa {
+ status = "disabled";
+ };
};
&firmware {
@@ -502,3 +507,11 @@
status = "okay";
};
};
+
+&ipa_hw {
+ status = "disabled";
+};
+
+&msm_gpu {
+ /delete-node/ qcom,gpu-mempools;
+};
diff --git a/arch/arm64/boot/dts/qcom/msm8909-pm8916-camera-sensor-robot-som.dtsi b/arch/arm64/boot/dts/qcom/msm8909-pm8916-camera-sensor-robot-som.dtsi
index 310b53a..9c0e539 100644
--- a/arch/arm64/boot/dts/qcom/msm8909-pm8916-camera-sensor-robot-som.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8909-pm8916-camera-sensor-robot-som.dtsi
@@ -26,6 +26,7 @@
cam_vdig-supply = <&pm8916_l2>;
cam_vana-supply = <&pm8916_l17>;
cam_vio-supply = <&pm8916_l6>;
+ qcom,cam-vreg-type = <0 0 0>;
qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana";
qcom,cam-vreg-min-voltage = <1200000 1800000 2850000>;
qcom,cam-vreg-max-voltage = <1200000 1800000 2850000>;
@@ -66,6 +67,7 @@
qcom,cam-vreg-min-voltage = <1800000 2850000>;
qcom,cam-vreg-max-voltage = <1800000 2850000>;
qcom,cam-vreg-op-mode = <0 80000>;
+ qcom,cam-vreg-type = <0 0>;
pinctrl-names = "cam_default", "cam_suspend";
pinctrl-0 = <&cam_sensor_mclk0_default
&cam_sensor_rear_default>;
diff --git a/arch/arm64/boot/dts/qcom/msm8909-pm8916-camera-sensor-robot.dtsi b/arch/arm64/boot/dts/qcom/msm8909-pm8916-camera-sensor-robot.dtsi
index 6f6655a..ce12d33 100644
--- a/arch/arm64/boot/dts/qcom/msm8909-pm8916-camera-sensor-robot.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8909-pm8916-camera-sensor-robot.dtsi
@@ -16,6 +16,95 @@
};
&i2c_3 {
+ otp_eeprom: qcom,msm_eeprom@6e{
+ status = "ok";
+ cell-index = <0>;
+ reg = <0x6e>;
+ compatible = "msm_eeprom";
+ qcom,eeprom-name = "sunny_imx241_otp";
+ qcom,slave-addr = <0x6e>;
+ qcom,i2c-freq-mode = <1>;
+
+ cam_vdig-supply = <&pm8916_l2>;
+ cam_vio-supply = <&pm8916_l6>;
+ cam_vana-supply = <&pm8916_l17>;
+ qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana";
+ qcom,cam-vreg-min-voltage = <1200000 1800000 2850000>;
+ qcom,cam-vreg-max-voltage = <1200000 1800000 2850000>;
+ qcom,cam-vreg-op-mode = <200000 0 80000>;
+ qcom,cam-vreg-type = <0 0 0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_default
+ &cam_sensor_rear_default>;
+ pinctrl-1 = <&cam_sensor_mclk0_sleep
+ &cam_sensor_rear_sleep>;
+ gpios = <&msm_gpio 26 0>,
+ <&msm_gpio 35 0>;
+ qcom,gpio-reset = <1>;
+ qcom,gpio-req-tbl-num = <0 1>;
+ qcom,gpio-req-tbl-flags = <1 0>;
+ qcom,gpio-req-tbl-label = "CAMIF_MCLK", "CAM_RESET";
+
+ qcom,cam-power-seq-type = "sensor_vreg",
+ "sensor_vreg",
+ "sensor_vreg",
+ "sensor_gpio",
+ "sensor_clk",
+ "sensor_i2c_mux";
+ qcom,cam-power-seq-val = "cam_vana",
+ "cam_vdig",
+ "cam_vio",
+ "sensor_gpio_reset",
+ "sensor_cam_mclk",
+ "none";
+ qcom,cam-power-seq-cfg-val = <2850000 1200000
+ 1800000 1 24000000 0>;
+ qcom,cam-power-seq-delay = <1 1 1 1 1 0>;
+
+ clocks = <&clock_gcc clk_mclk0_clk_src>,
+ <&clock_gcc clk_gcc_camss_mclk0_clk>;
+ clock-names = "cam_src_clk", "cam_clk";
+ qcom,clock-rates = <24000000 0>;
+
+ qcom,num-blocks = <12>;
+ qcom,page0 = <1 0x34C5 2 0x02 1 1>;
+ qcom,poll0 = <0 0x0 2 0 1 1>;
+ qcom,mem0 = <0 0x0 2 0 1 0>;
+ qcom,page1 = <1 0x34C9 2 0x02 1 10>;
+ qcom,poll1 = <0 0x0 2 0 1 1>;
+ qcom,mem1 = <8 0x3510 2 0 1 0>;
+ qcom,page2 = <1 0x34C5 2 0x03 1 1>;
+ qcom,poll2 = <0 0x0 2 0 1 1>;
+ qcom,mem2 = <0 0x0 2 0 1 0>;
+ qcom,page3 = <1 0x34C9 2 0x03 1 10>;
+ qcom,poll3 = <0 0x0 2 0 1 1>;
+ qcom,mem3 = <8 0x3518 2 0 1 0>;
+ qcom,page4 = <1 0x34C5 2 0x06 1 1>;
+ qcom,poll4 = <0 0x0 2 0 1 1>;
+ qcom,mem4 = <0 0x0 2 0 1 0>;
+ qcom,page5 = <1 0x34C9 2 0x06 1 10>;
+ qcom,poll5 = <0 0x0 2 0 1 1>;
+ qcom,mem5 = <8 0x3530 2 0 1 0>;
+ qcom,page6 = <1 0x34C5 2 0x07 1 1>;
+ qcom,poll6 = <0 0x0 2 0 1 1>;
+ qcom,mem6 = <0 0x0 2 0 1 0>;
+ qcom,page7 = <1 0x34C9 2 0x07 1 10>;
+ qcom,poll7 = <0 0x0 2 0 1 1>;
+ qcom,mem7 = <8 0x3538 2 0 1 0>;
+ qcom,page8 = <1 0x34C5 2 0x0A 1 1>;
+ qcom,poll8 = <0 0x0 2 0 1 1>;
+ qcom,mem8 = <0 0x0 2 0 1 0>;
+ qcom,page9 = <1 0x34C9 2 0x0A 1 10>;
+ qcom,poll9 = <0 0x0 2 0 1 1>;
+ qcom,mem9 = <8 0x3550 2 0 1 0>;
+ qcom,page10 = <1 0x34C5 2 0x0B 1 1>;
+ qcom,poll10 = <0 0x0 2 0 1 1>;
+ qcom,mem10 = <0 0x0 2 0 1 0>;
+ qcom,page11 = <1 0x34C9 2 0x0B 1 10>;
+ qcom,poll11 = <0 0x0 2 0 1 1>;
+ qcom,mem11 = <8 0x3558 2 0 1 0>;
+ };
+
qcom,camera@0 {
cell-index = <0>;
compatible = "qcom,camera";
@@ -26,6 +115,7 @@
cam_vdig-supply = <&pm8916_l2>;
cam_vana-supply = <&pm8916_l17>;
cam_vio-supply = <&pm8916_l6>;
+ qcom,cam-vreg-type = <0 0 0>;
qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana";
qcom,cam-vreg-min-voltage = <1200000 1800000 2850000>;
qcom,cam-vreg-max-voltage = <1200000 1800000 2850000>;
@@ -46,6 +136,7 @@
"CAM_STANDBY";
qcom,sensor-position = <0>;
qcom,sensor-mode = <0>;
+ qcom,eeprom-src = <&otp_eeprom>;
status = "ok";
clocks = <&clock_gcc clk_mclk0_clk_src>,
<&clock_gcc clk_gcc_camss_mclk0_clk>;
@@ -66,6 +157,7 @@
qcom,cam-vreg-min-voltage = <1800000 2850000>;
qcom,cam-vreg-max-voltage = <1800000 2850000>;
qcom,cam-vreg-op-mode = <0 80000>;
+ qcom,cam-vreg-type = <0 0>;
pinctrl-names = "cam_default", "cam_suspend";
pinctrl-0 = <&cam_sensor_mclk0_default
&cam_sensor_rear_default>;
diff --git a/arch/arm64/boot/dts/qcom/msm8917-cdp-ext-codec-overlay.dts b/arch/arm64/boot/dts/qcom/msm8917-cdp-ext-codec-overlay.dts
new file mode 100644
index 0000000..7dba042
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8917-cdp-ext-codec-overlay.dts
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "msm8917-cdp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. MSM8917 External Audio Codec CDP";
+ qcom,board-id = <1 1>;
+};
+
+&pm8937_gpios {
+ gpio@c000 {
+ status = "ok";
+ qcom,mode = <1>;
+ qcom,pull = <5>;
+ qcom,vin-sel = <0>;
+ qcom,src-sel = <2>;
+ qcom,master-en = <1>;
+ qcom,out-strength = <2>;
+ };
+
+ gpio@c600 {
+ status = "ok";
+ qcom,mode = <1>;
+ qcom,pull = <5>;
+ qcom,vin-sel = <0>;
+ qcom,src-sel = <0>;
+ qcom,master-en = <1>;
+ qcom,out-strength = <2>;
+ };
+};
+
+&slim_msm {
+ status = "okay";
+};
+
+&wcd9xxx_intc {
+ status = "okay";
+};
+
+&clock_audio {
+ status = "okay";
+};
+
+&wcd9335 {
+ status = "okay";
+};
+
+&wcd_rst_gpio {
+ status = "okay";
+};
+
+&ext_codec {
+ status = "okay";
+};
+
+&int_codec {
+ status = "disabled";
+};
+
+&wsa881x_i2c_f {
+ status = "disabled";
+};
+
+&wsa881x_i2c_45 {
+ status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/qcom/msm8917-cdp-mirror-lake-touch.dtsi b/arch/arm64/boot/dts/qcom/msm8917-cdp-mirror-lake-touch.dtsi
index ac8817b..ef17b35 100644
--- a/arch/arm64/boot/dts/qcom/msm8917-cdp-mirror-lake-touch.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8917-cdp-mirror-lake-touch.dtsi
@@ -11,7 +11,6 @@
* GNU General Public License for more details.
*/
-#include "msm8917-pinctrl.dtsi"
/* #include "msm8917-camera-sensor-cdp.dtsi"*/
&soc {
@@ -113,131 +112,6 @@
pinctrl-names = "default";
pinctrl-0 = <&uart_console_active>;
};
-
-#include "msm8937-mdss-panels.dtsi"
-
-&mdss_mdp {
- qcom,mdss-pref-prim-intf = "dsi";
-};
-
-&mdss_dsi {
- hw-config = "single_dsi";
-};
-
-&mdss_dsi0 {
- qcom,dsi-pref-prim-pan = <&dsi_truly_720_vid>;
- pinctrl-names = "mdss_default", "mdss_sleep";
- pinctrl-0 = <&mdss_dsi_active &mdss_te_active>;
- pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>;
-
- qcom,platform-te-gpio = <&tlmm 24 0>;
- qcom,platform-reset-gpio = <&tlmm 60 0>;
- qcom,platform-bklight-en-gpio = <&tlmm 98 0>;
-};
-
-&dsi_truly_720_vid {
- qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
- qcom,mdss-dsi-pan-enable-dynamic-fps;
- qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
-};
-
-&dsi_truly_720_cmd {
- qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
- qcom,ulps-enabled;
- qcom,partial-update-enabled;
- qcom,panel-roi-alignment = <2 2 2 2 2 2>;
-};
-
-&dsi_icn9706_720_1440_vid {
- qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
- qcom,mdss-dsi-pan-enable-dynamic-fps;
- qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
-};
-
-&tlmm {
- tlmm_gpio_key {
- gpio_key_active: gpio_key_active {
- mux {
- pins = "gpio86", "gpio91", "gpio127", "gpio128";
- function = "gpio";
- };
-
- config {
- pins = "gpio86", "gpio91", "gpio127", "gpio128";
- };
- };
-
- gpio_key_suspend: gpio_key_suspend {
- mux {
- pins = "gpio86", "gpio91", "gpio127", "gpio128";
- function = "gpio";
- };
-
- config {
- pins = "gpio86", "gpio91", "gpio127", "gpio128";
- };
- };
- };
-};
-
-&sdhc_1 {
- /* device core power supply */
- vdd-supply = <&pm8937_l8>;
- qcom,vdd-voltage-level = <2900000 2900000>;
- qcom,vdd-current-level = <200 570000>;
-
- /* device communication power supply */
- vdd-io-supply = <&pm8937_l5>;
- qcom,vdd-io-always-on;
- qcom,vdd-io-lpm-sup;
- qcom,vdd-io-voltage-level = <1800000 1800000>;
- qcom,vdd-io-current-level = <200 325000>;
-
- pinctrl-names = "active", "sleep";
- pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
- pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
-
- qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 192000000
- 384000000>;
- qcom,nonremovable;
- qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v";
-
- status = "ok";
-};
-
-&sdhc_2 {
- /* device core power supply */
- vdd-supply = <&pm8937_l11>;
- qcom,vdd-voltage-level = <2950000 2950000>;
- qcom,vdd-current-level = <15000 800000>;
-
- /* device communication power supply */
- vdd-io-supply = <&pm8937_l12>;
- qcom,vdd-io-voltage-level = <1800000 2950000>;
- qcom,vdd-io-current-level = <200 22000>;
-
- pinctrl-names = "active", "sleep";
- pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
- pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
-
- #address-cells = <0>;
- interrupt-parent = <&sdhc_2>;
- interrupts = <0 1 2>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0xffffffff>;
- interrupt-map = <0 &intc 0 125 0
- 1 &intc 0 221 0
- 2 &tlmm 67 0>;
- interrupt-names = "hc_irq", "pwr_irq", "status_irq";
- cd-gpios = <&tlmm 67 0x1>;
-
- qcom,clk-rates = <400000 20000000 25000000 50000000 100000000
- 200000000>;
- qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104";
-
- status = "ok";
-};
-
&i2c_3 {
status = "okay";
synaptics@22 {
diff --git a/arch/arm64/boot/dts/qcom/msm8917-cdp-ml-touch-overlay.dts b/arch/arm64/boot/dts/qcom/msm8917-cdp-ml-touch-overlay.dts
new file mode 100644
index 0000000..377eda4
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8917-cdp-ml-touch-overlay.dts
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/msm-clocks-8952.h>
+#include "msm8917-cdp.dtsi"
+#include "msm8917-cdp-mirror-lake-touch.dtsi"
+#include "msm8917-audio-cdp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. MSM8917-CDP ML Touch";
+ qcom,board-id = <1 4>;
+};
+
+&soc {
+ led_flash0: qcom,camera-flash {
+ cell-index = <0>;
+ compatible = "qcom,camera-flash";
+ qcom,flash-type = <1>;
+ qcom,flash-source = <&pmi8950_flash0 &pmi8950_flash1>;
+ qcom,torch-source = <&pmi8950_torch0 &pmi8950_torch1>;
+ qcom,switch-source = <&pmi8950_switch>;
+ };
+
+ bluetooth: bt_qca6174 {
+ compatible = "qca,qca6174";
+ qca,bt-reset-gpio = <&tlmm 129 0>; /* BT_EN */
+ };
+};
+
+&qpnp_smbcharger {
+ /delete-property/ dpdm-supply;
+};
+
+&pm8937_gpios {
+ gpio@c400 {
+ qcom,mode = <0>;
+ qcom,output-type = <0>;
+ qcom,pull = <0>;
+ qcom,vin-sel = <2>;
+ qcom,out-strength = <3>;
+ qcom,src-sel = <0>;
+ qcom,master-en = <1>;
+ status = "okay";
+ };
+};
+
+&i2c_5 { /* BLSP2 QUP1 */
+ nq@28 {
+ compatible = "qcom,nq-nci";
+ reg = <0x28>;
+ qcom,nq-irq = <&tlmm 17 0x00>;
+ qcom,nq-ven = <&tlmm 16 0x00>;
+ qcom,nq-firm = <&tlmm 130 0x00>;
+ qcom,nq-clkreq = <&pm8937_gpios 5 0x00>;
+ interrupt-parent = <&tlmm>;
+ qcom,clk-src = "BBCLK2";
+ interrupts = <17 0>;
+ interrupt-names = "nfc_irq";
+ pinctrl-names = "nfc_active", "nfc_suspend";
+ pinctrl-0 = <&nfc_int_active &nfc_disable_active>;
+ pinctrl-1 = <&nfc_int_suspend &nfc_disable_suspend>;
+ clocks = <&clock_gcc clk_bb_clk2_pin>;
+ clock-names = "ref_clk";
+ };
+};
+
+&mdss_dsi0 {
+ lab-supply = <&lab_regulator>;
+ ibb-supply = <&ibb_regulator>;
+};
+
+&labibb {
+ status = "ok";
+ qpnp,qpnp-labibb-mode = "lcd";
+};
+
+&ibb_regulator {
+ qcom,qpnp-ibb-discharge-resistor = <32>;
+};
+
+&dsi_panel_pwr_supply {
+ qcom,panel-supply-entry@2 {
+ reg = <2>;
+ qcom,supply-name = "lab";
+ qcom,supply-min-voltage = <4600000>;
+ qcom,supply-max-voltage = <6000000>;
+ qcom,supply-enable-load = <100000>;
+ qcom,supply-disable-load = <100>;
+ };
+
+ qcom,panel-supply-entry@3 {
+ reg = <3>;
+ qcom,supply-name = "ibb";
+ qcom,supply-min-voltage = <4600000>;
+ qcom,supply-max-voltage = <6000000>;
+ qcom,supply-enable-load = <100000>;
+ qcom,supply-disable-load = <100>;
+ qcom,supply-post-on-sleep = <20>;
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/msm8917-cdp-overlay.dts b/arch/arm64/boot/dts/qcom/msm8917-cdp-overlay.dts
new file mode 100644
index 0000000..c695324
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8917-cdp-overlay.dts
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "msm8917-cdp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. MSM8917-CDP";
+ qcom,board-id = <1 0>,
+ <1 4>,
+ <1 1>;
+};
diff --git a/arch/arm64/boot/dts/qcom/msm8917-cdp.dtsi b/arch/arm64/boot/dts/qcom/msm8917-cdp.dtsi
index 513e995..6a2fecd 100644
--- a/arch/arm64/boot/dts/qcom/msm8917-cdp.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8917-cdp.dtsi
@@ -10,8 +10,6 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
-#include "msm8917-pinctrl.dtsi"
-/* #include "msm8917-camera-sensor-cdp.dtsi"*/
&soc {
gpio_keys {
@@ -126,6 +124,12 @@
qcom,panel-roi-alignment = <2 2 2 2 2 2>;
};
+&dsi_icn9706_720_1440_vid {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-pan-enable-dynamic-fps;
+ qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
+};
+
&tlmm {
tlmm_gpio_key {
gpio_key_active: gpio_key_active {
diff --git a/arch/arm64/boot/dts/qcom/msm8917-mtp-overlay.dts b/arch/arm64/boot/dts/qcom/msm8917-mtp-overlay.dts
new file mode 100644
index 0000000..920bcae
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8917-mtp-overlay.dts
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/msm-clocks-8952.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "msm8917-mtp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. MSM8917-MTP";
+ qcom,board-id = <8 0>;
+};
+
+&blsp1_uart1 {
+ status = "ok";
+};
+
+&vendor {
+ mtp_batterydata: qcom,battery-data {
+ qcom,batt-id-range-pct = <15>;
+ #include "batterydata-itech-3000mah.dtsi"
+ #include "batterydata-ascent-3450mAh.dtsi"
+ };
+};
+
+&qpnp_fg {
+ qcom,battery-data = <&mtp_batterydata>;
+};
+
+&qpnp_smbcharger {
+ qcom,battery-data = <&mtp_batterydata>;
+};
diff --git a/arch/arm64/boot/dts/qcom/msm8917-mtp.dtsi b/arch/arm64/boot/dts/qcom/msm8917-mtp.dtsi
index c79b9f8..d2e100e9 100644
--- a/arch/arm64/boot/dts/qcom/msm8917-mtp.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8917-mtp.dtsi
@@ -11,7 +11,6 @@
* GNU General Public License for more details.
*/
-#include "msm8917-pinctrl.dtsi"
&blsp1_uart2 {
status = "ok";
diff --git a/arch/arm64/boot/dts/qcom/msm8917-pmi8937.dts b/arch/arm64/boot/dts/qcom/msm8917-pmi8937.dts
new file mode 100644
index 0000000..635705b
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8917-pmi8937.dts
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "msm8917.dtsi"
+#include "msm8917-pmi8937.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. MSM8917 + PMI8937 SOC";
+ compatible = "qcom,msm8917";
+ qcom,pmic-id = <0x10019 0x020037 0x0 0x0>;
+ qcom,pmic-name = "PMI8937";
+};
diff --git a/arch/arm64/boot/dts/qcom/msm8917-pmi8940.dts b/arch/arm64/boot/dts/qcom/msm8917-pmi8940.dts
new file mode 100644
index 0000000..e4017c7
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8917-pmi8940.dts
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "msm8917.dtsi"
+#include "msm8917-pmi8940.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. MSM8917 + PMI8940 SOC";
+ compatible = "qcom,msm8917";
+ qcom,pmic-id = <0x10019 0x020040 0x0 0x0>;
+ qcom,pmic-name = "PMI8940";
+};
diff --git a/arch/arm64/boot/dts/qcom/msm8917-pmi8950-cdp-mirror-lake-touch.dts b/arch/arm64/boot/dts/qcom/msm8917-pmi8950-cdp-mirror-lake-touch.dts
index 4a38b6f..ae35baf 100644
--- a/arch/arm64/boot/dts/qcom/msm8917-pmi8950-cdp-mirror-lake-touch.dts
+++ b/arch/arm64/boot/dts/qcom/msm8917-pmi8950-cdp-mirror-lake-touch.dts
@@ -14,8 +14,8 @@
/dts-v1/;
#include "msm8917.dtsi"
-#include "msm8917-cdp.dtsi"
#include "msm8917-pmi8950.dtsi"
+#include "msm8917-cdp.dtsi"
#include "msm8917-pmi8950-cdp-mirror-lake-touch.dtsi"
/ {
diff --git a/arch/arm64/boot/dts/qcom/msm8917-pmi8950-cdp-mirror-lake-touch.dtsi b/arch/arm64/boot/dts/qcom/msm8917-pmi8950-cdp-mirror-lake-touch.dtsi
index 4701101..6415241 100644
--- a/arch/arm64/boot/dts/qcom/msm8917-pmi8950-cdp-mirror-lake-touch.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8917-pmi8950-cdp-mirror-lake-touch.dtsi
@@ -11,7 +11,6 @@
* GNU General Public License for more details.
*/
-#include "pmi8950.dtsi"
#include "msm8917-cdp-mirror-lake-touch.dtsi"
#include "msm8917-audio-cdp.dtsi"
diff --git a/arch/arm64/boot/dts/qcom/msm8917-pmi8950.dts b/arch/arm64/boot/dts/qcom/msm8917-pmi8950.dts
new file mode 100644
index 0000000..4a904c6
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8917-pmi8950.dts
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "msm8917.dtsi"
+#include "msm8917-pmi8950.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. MSM8917 + PMI8950 SOC ";
+ compatible = "qcom,msm8917";
+ qcom,pmic-id = <0x10019 0x010011 0x0 0x0>;
+ qcom,pmic-name = "PMI8950";
+};
diff --git a/arch/arm64/boot/dts/qcom/msm8917-qrd-overlay.dts b/arch/arm64/boot/dts/qcom/msm8917-qrd-overlay.dts
new file mode 100644
index 0000000..6517757
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8917-qrd-overlay.dts
@@ -0,0 +1,123 @@
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/msm-clocks-8952.h>
+#include "msm8917-qrd.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. MSM8917-QRD SKU5";
+ qcom,board-id = <0x1000b 0>;
+};
+
+&vendor{
+ qrd_batterydata: qcom,battery-data {
+ qcom,batt-id-range-pct = <15>;
+ #include "batterydata-qrd-sku2-4v35-2590mah.dtsi"
+ };
+};
+
+&qpnp_smbcharger {
+ qcom,battery-data = <&qrd_batterydata>;
+};
+
+&qpnp_fg {
+ qcom,battery-data = <&qrd_batterydata>;
+};
+
+&mdss_mdp {
+ qcom,mdss-pref-prim-intf = "dsi";
+};
+
+&mdss_dsi {
+ hw-config = "single_dsi";
+};
+
+&mdss_dsi0 {
+ qcom,dsi-pref-prim-pan = <&dsi_hx8394f_720p_video>;
+ pinctrl-names = "mdss_default", "mdss_sleep";
+ pinctrl-0 = <&mdss_dsi_active>;
+ pinctrl-1 = <&mdss_dsi_suspend>;
+
+ qcom,platform-reset-gpio = <&tlmm 60 0>;
+};
+
+&dsi_hx8394f_720p_video {
+ qcom,esd-check-enabled;
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+};
+
+&soc {
+ i2c@78b7000 {
+ status = "ok";
+ focaltech@38 {
+ compatible = "focaltech,5x06";
+ reg = <0x38>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <65 0x2>;
+ vdd-supply = <&pm8937_l10>;
+ vcc_i2c-supply = <&pm8937_l5>;
+ /* pins used by touchscreen */
+ pinctrl-names = "pmx_ts_active",
+ "pmx_ts_suspend",
+ "pmx_ts_release";
+ pinctrl-0 = <&ts_int_active &ts_reset_active>;
+ pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+ pinctrl-2 = <&ts_release>;
+ focaltech,name = "ft5436";
+ focaltech,family-id = <0x06>;
+ focaltech,reset-gpio = <&tlmm 64 0x0>;
+ focaltech,irq-gpio = <&tlmm 65 0x2008>;
+ focaltech,display-coords = <0 0 720 1280>;
+ focaltech,panel-coords = <0 0 720 1400>;
+ focaltech,button-map= <139 102 158>;
+ focaltech,no-force-update;
+ focaltech,i2c-pull-up;
+ focaltech,group-id = <1>;
+ focaltech,hard-reset-delay-ms = <20>;
+ focaltech,soft-reset-delay-ms = <200>;
+ focaltech,num-max-touches = <5>;
+ focaltech,fw-delay-aa-ms = <30>;
+ focaltech,fw-delay-55-ms = <30>;
+ focaltech,fw-upgrade-id1 = <0x79>;
+ focaltech,fw-upgrade-id2 = <0x08>;
+ focaltech,fw-delay-readid-ms = <10>;
+ focaltech,fw-delay-era-flsh-ms = <2000>;
+ focaltech,fw-auto-cal;
+ focaltech,ignore-id-check;
+ focaltech,resume-in-workqueue;
+ };
+ };
+
+ gen-vkeys {
+ compatible = "qcom,gen-vkeys";
+ label = "ft5x06_ts";
+ qcom,disp-maxx = <720>;
+ qcom,disp-maxy = <1280>;
+ qcom,panel-maxx = <720>;
+ qcom,panel-maxy = <1400>;
+ qcom,key-codes = <139 172 158>;
+ qcom,y-offset = <0>;
+ };
+
+ led_flash0: qcom,camera-flash {
+ cell-index = <0>;
+ compatible = "qcom,camera-flash";
+ qcom,flash-type = <1>;
+ qcom,flash-source = <&pmi8937_flash0>;
+ qcom,torch-source = <&pmi8937_torch0>;
+ qcom,switch-source = <&pmi8937_switch>;
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/msm8917-qrd.dtsi b/arch/arm64/boot/dts/qcom/msm8917-qrd.dtsi
index 1e5393b..d5fd1ff 100644
--- a/arch/arm64/boot/dts/qcom/msm8917-qrd.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8917-qrd.dtsi
@@ -10,9 +10,8 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
-
-#include "msm8917-pinctrl.dtsi"
#include "msm8917-camera-sensor-qrd.dtsi"
+#include "msm8937-mdss-panels.dtsi"
&blsp1_uart2 {
status = "ok";
diff --git a/arch/arm64/boot/dts/qcom/msm8917-rcm-overlay.dts b/arch/arm64/boot/dts/qcom/msm8917-rcm-overlay.dts
new file mode 100644
index 0000000..fdf98db
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8917-rcm-overlay.dts
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "msm8917-cdp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. MSM8917-RCM";
+ qcom,board-id = <21 0>;
+};
diff --git a/arch/arm64/boot/dts/qcom/msm8917.dtsi b/arch/arm64/boot/dts/qcom/msm8917.dtsi
index 1d5fe79..cc51694 100644
--- a/arch/arm64/boot/dts/qcom/msm8917.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8917.dtsi
@@ -53,6 +53,11 @@
firmware: firmware {
android {
compatible = "android,firmware";
+ vbmeta {
+ compatible = "android,vbmeta";
+ parts = "vbmeta,boot,system,vendor,dtbo,recovery";
+ };
+
fstab {
compatible = "android,fstab";
vendor {
@@ -60,7 +65,7 @@
dev = "/dev/block/platform/soc/7824900.sdhci/by-name/vendor";
type = "ext4";
mnt_flags = "ro,barrier=1,discard";
- fsmgr_flags = "wait";
+ fsmgr_flags = "wait,avb";
status = "ok";
};
system {
@@ -68,7 +73,7 @@
dev = "/dev/block/platform/soc/7824900.sdhci/by-name/system";
type = "ext4";
mnt_flags = "ro,barrier=1,discard";
- fsmgr_flags = "wait";
+ fsmgr_flags = "wait,avb";
status = "ok";
};
};
diff --git a/arch/arm64/boot/dts/qcom/sdm439-camera-sensor-cdp.dtsi b/arch/arm64/boot/dts/qcom/sdm439-camera-sensor-cdp.dtsi
index eae8c56..2987d67 100644
--- a/arch/arm64/boot/dts/qcom/sdm439-camera-sensor-cdp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm439-camera-sensor-cdp.dtsi
@@ -30,7 +30,7 @@
cell-index = <1>;
reg = <0x1>;
compatible = "qcom,actuator";
- qcom,cci-master = <0>;
+ qcom,cci-master = <1>;
cam_vaf-supply = <&pm8953_l17>;
qcom,cam-vreg-name = "cam_vaf";
qcom,cam-vreg-min-voltage = <2850000>;
@@ -156,6 +156,43 @@
qcom,clock-rates = <19200000 0>;
};
+ eeprom2: qcom,eeprom@2 {
+ cell-index = <2>;
+ compatible = "qcom,eeprom";
+ qcom,cci-master = <1>;
+ reg = <0x2>;
+ cam_vdig-supply = <&pm8953_l3>;
+ cam_vana-supply = <&pm8953_l22>;
+ cam_vio-supply = <&pm8953_l6>;
+ cam_vaf-supply = <&pm8953_l17>;
+ qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana",
+ "cam_vaf";
+ qcom,cam-vreg-min-voltage = <1200000 0 2800000 2850000>;
+ qcom,cam-vreg-max-voltage = <1200000 0 2800000 2850000>;
+ qcom,cam-vreg-op-mode = <105000 0 80000 100000>;
+ qcom,gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_default
+ &cam_sensor_front1_default>;
+ pinctrl-1 = <&cam_sensor_mclk2_sleep
+ &cam_sensor_front1_sleep>;
+ gpios = <&tlmm 28 0>,
+ <&tlmm 40 0>,
+ <&tlmm 39 0>;
+ qcom,gpio-reset = <1>;
+ qcom,gpio-standby = <2>;
+ qcom,gpio-req-tbl-num = <0 1 2>;
+ qcom,gpio-req-tbl-flags = <1 0 0>;
+ qcom,gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2",
+ "CAM_STANDBY2";
+ status = "ok";
+ clocks = <&clock_gcc clk_mclk2_clk_src>,
+ <&clock_gcc clk_gcc_camss_mclk2_clk>;
+ clock-names = "cam_src_clk", "cam_clk";
+ qcom,clock-rates = <19200000 0>;
+ };
+
qcom,camera@0 {
cell-index = <0>;
compatible = "qcom,camera";
@@ -249,9 +286,9 @@
qcom,csiphy-sd-index = <1>;
qcom,csid-sd-index = <1>;
qcom,mount-angle = <90>;
- qcom,eeprom-src = <&eeprom1>;
+ qcom,eeprom-src = <&eeprom2>;
qcom,actuator-src = <&actuator1>;
- cam_vdig-supply = <&pm8953_l23>;
+ cam_vdig-supply = <&pm8953_l3>;
cam_vana-supply = <&pm8953_l22>;
cam_vio-supply = <&pm8953_l6>;
cam_vaf-supply = <&pm8953_l17>;
@@ -278,7 +315,7 @@
"CAM_STANDBY2";
qcom,sensor-position = <1>;
qcom,sensor-mode = <0>;
- qcom,cci-master = <0>;
+ qcom,cci-master = <1>;
status = "ok";
clocks = <&clock_gcc clk_mclk2_clk_src>,
<&clock_gcc clk_gcc_camss_mclk2_clk>;
diff --git a/arch/arm64/boot/dts/qcom/sdm439-qrd.dtsi b/arch/arm64/boot/dts/qcom/sdm439-qrd.dtsi
index a3c5b1f..20562d1 100644
--- a/arch/arm64/boot/dts/qcom/sdm439-qrd.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm439-qrd.dtsi
@@ -428,3 +428,8 @@
qcom,hw-die-temp-mitigation;
};
};
+
+&pmi632_charger {
+ qcom,thermal-mitigation = <4200000 3500000 3000000 2500000
+ 2000000 1500000 1000000 500000>;
+};
diff --git a/arch/arm64/boot/dts/qcom/sdm450-qrd-sku4.dtsi b/arch/arm64/boot/dts/qcom/sdm450-qrd-sku4.dtsi
index 40fdb91..8671877 100644
--- a/arch/arm64/boot/dts/qcom/sdm450-qrd-sku4.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm450-qrd-sku4.dtsi
@@ -255,3 +255,8 @@
qcom,hw-die-temp-mitigation;
};
};
+
+&pmi632_charger {
+ qcom,thermal-mitigation = <4200000 3500000 3000000 2500000
+ 2000000 1500000 1000000 500000>;
+};
diff --git a/arch/arm64/boot/dts/qcom/sdm632-qrd.dtsi b/arch/arm64/boot/dts/qcom/sdm632-qrd.dtsi
index cefc078..6a07bfe 100644
--- a/arch/arm64/boot/dts/qcom/sdm632-qrd.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm632-qrd.dtsi
@@ -18,3 +18,8 @@
qcom,redrive-voltage-level = <0 1800000 1900000>;
qcom,redrive-load = <105000>;
};
+
+&pmi632_charger {
+ qcom,thermal-mitigation = <4200000 3500000 3000000 2500000
+ 2000000 1500000 1000000 500000>;
+};
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index d934d2a..4efab0b 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -1550,6 +1550,7 @@
qcom,firmware-name = "modem";
qcom,pil-self-auth;
qcom,sysmon-id = <0>;
+ qcom,minidump-id = <3>;
qcom,ssctl-instance-id = <0x12>;
qcom,override-acc;
qcom,signal-aop;
diff --git a/drivers/bluetooth/bluetooth-power.c b/drivers/bluetooth/bluetooth-power.c
index 7f7c942..0574e44 100644
--- a/drivers/bluetooth/bluetooth-power.c
+++ b/drivers/bluetooth/bluetooth-power.c
@@ -666,7 +666,7 @@
bluetooth_power_rfkill_remove(pdev);
- if (bt_power_pdata->bt_chip_pwd->reg)
+ if (bt_power_pdata->bt_chip_pwd)
regulator_put(bt_power_pdata->bt_chip_pwd->reg);
kfree(bt_power_pdata);
diff --git a/drivers/cpuidle/lpm-levels.c b/drivers/cpuidle/lpm-levels.c
index c7ec868..e692f660 100644
--- a/drivers/cpuidle/lpm-levels.c
+++ b/drivers/cpuidle/lpm-levels.c
@@ -1777,6 +1777,7 @@
.driver = {
.name = "lpm-levels",
.owner = THIS_MODULE,
+ .suppress_bind_attrs = true,
.of_match_table = lpm_mtch_tbl,
},
};
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c b/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c
index a457070..011e3b8 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c
@@ -69,6 +69,7 @@
ctrl->ops.get_hw_version = dsi_ctrl_hw_cmn_get_hw_version;
ctrl->ops.wait_for_cmd_mode_mdp_idle =
dsi_ctrl_hw_cmn_wait_for_cmd_mode_mdp_idle;
+ ctrl->ops.set_continuous_clk = dsi_ctrl_hw_cmn_set_continuous_clk;
switch (version) {
case DSI_CTRL_VERSION_1_4:
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.h b/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.h
index 9a923aa..c55bbe0 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.h
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.h
@@ -224,4 +224,6 @@
/* Definitions specific to 2.2 DSI controller hardware */
bool dsi_ctrl_hw_22_get_cont_splash_status(struct dsi_ctrl_hw *ctrl);
+void dsi_ctrl_hw_cmn_set_continuous_clk(struct dsi_ctrl_hw *ctrl, bool enable);
+
#endif /* _DSI_CATALOG_H_ */
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c
index a4af58a..31c3b1a 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c
@@ -1239,9 +1239,10 @@
}
}
- if (dsi_ctrl->hw.ops.mask_error_intr)
+ if (dsi_ctrl->hw.ops.mask_error_intr &&
+ !dsi_ctrl->esd_check_underway)
dsi_ctrl->hw.ops.mask_error_intr(&dsi_ctrl->hw,
- BIT(DSI_FIFO_OVERFLOW), false);
+ BIT(DSI_FIFO_OVERFLOW), false);
dsi_ctrl->hw.ops.reset_cmd_fifo(&dsi_ctrl->hw);
/*
@@ -2603,6 +2604,16 @@
mutex_unlock(&dsi_ctrl->ctrl_lock);
}
+void dsi_ctrl_set_continuous_clk(struct dsi_ctrl *dsi_ctrl, bool enable)
+{
+ if (!dsi_ctrl)
+ return;
+
+ mutex_lock(&dsi_ctrl->ctrl_lock);
+ dsi_ctrl->hw.ops.set_continuous_clk(&dsi_ctrl->hw, enable);
+ mutex_unlock(&dsi_ctrl->ctrl_lock);
+}
+
int dsi_ctrl_soft_reset(struct dsi_ctrl *dsi_ctrl)
{
if (!dsi_ctrl)
@@ -2888,7 +2899,8 @@
dsi_ctrl->cell_index);
}
}
- if (dsi_ctrl->hw.ops.mask_error_intr)
+ if (dsi_ctrl->hw.ops.mask_error_intr &&
+ !dsi_ctrl->esd_check_underway)
dsi_ctrl->hw.ops.mask_error_intr(&dsi_ctrl->hw,
BIT(DSI_FIFO_OVERFLOW), false);
@@ -3386,7 +3398,8 @@
return misr;
}
-void dsi_ctrl_mask_error_status_interrupts(struct dsi_ctrl *dsi_ctrl)
+void dsi_ctrl_mask_error_status_interrupts(struct dsi_ctrl *dsi_ctrl, u32 idx,
+ bool mask_enable)
{
if (!dsi_ctrl || !dsi_ctrl->hw.ops.error_intr_ctrl
|| !dsi_ctrl->hw.ops.clear_error_status) {
@@ -3399,9 +3412,23 @@
* register
*/
mutex_lock(&dsi_ctrl->ctrl_lock);
- dsi_ctrl->hw.ops.error_intr_ctrl(&dsi_ctrl->hw, false);
- dsi_ctrl->hw.ops.clear_error_status(&dsi_ctrl->hw,
+ if (idx & BIT(DSI_ERR_INTR_ALL)) {
+ /*
+ * The behavior of mask_enable is different in ctrl register
+ * and mask register and hence mask_enable is manipulated for
+ * selective error interrupt masking vs total error interrupt
+ * masking.
+ */
+
+ dsi_ctrl->hw.ops.error_intr_ctrl(&dsi_ctrl->hw, !mask_enable);
+ dsi_ctrl->hw.ops.clear_error_status(&dsi_ctrl->hw,
DSI_ERROR_INTERRUPT_COUNT);
+ } else {
+ dsi_ctrl->hw.ops.mask_error_intr(&dsi_ctrl->hw, idx,
+ mask_enable);
+ dsi_ctrl->hw.ops.clear_error_status(&dsi_ctrl->hw,
+ DSI_ERROR_INTERRUPT_COUNT);
+ }
mutex_unlock(&dsi_ctrl->ctrl_lock);
}
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.h b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.h
index 6ac7dd7..61c6116 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.h
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.h
@@ -221,6 +221,7 @@
* @cmd_buffer_size: Size of command buffer.
* @vaddr: CPU virtual address of cmd buffer.
* @secure_mode: Indicates if secure-session is in progress
+ * @esd_check_underway: Indicates if esd status check is in progress
* @debugfs_root: Root for debugfs entries.
* @misr_enable: Frame MISR enable/disable
* @misr_cache: Cached Frame MISR value
@@ -266,6 +267,7 @@
u32 cmd_len;
void *vaddr;
bool secure_mode;
+ bool esd_check_underway;
/* Debug Information */
struct dentry *debugfs_root;
@@ -743,8 +745,11 @@
* dsi_ctrl_mask_error_status_interrupts() - API to mask dsi ctrl error status
* interrupts
* @dsi_ctrl: DSI controller handle.
+ * @idx: id indicating which interrupts to enable/disable.
+ * @mask_enable: boolean to enable/disable masking.
*/
-void dsi_ctrl_mask_error_status_interrupts(struct dsi_ctrl *dsi_ctrl);
+void dsi_ctrl_mask_error_status_interrupts(struct dsi_ctrl *dsi_ctrl, u32 idx,
+ bool mask_enable);
/**
* dsi_ctrl_irq_update() - Put a irq vote to process DSI error
@@ -772,4 +777,10 @@
*/
int dsi_ctrl_wait_for_cmd_mode_mdp_idle(struct dsi_ctrl *dsi_ctrl);
+/**
+ * dsi_ctrl_set_continuous_clk() - API to set/unset force clock lane HS request.
+ * @dsi_ctrl: DSI controller handle.
+ * @enable: variable to control continuous clock.
+ */
+void dsi_ctrl_set_continuous_clk(struct dsi_ctrl *dsi_ctrl, bool enable);
#endif /* _DSI_CTRL_H_ */
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw.h b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw.h
index 8c62984..348ef36 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw.h
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw.h
@@ -803,6 +803,13 @@
* @ctrl: Pointer to the controller host hardware.
*/
int (*wait_for_cmd_mode_mdp_idle)(struct dsi_ctrl_hw *ctrl);
+
+ /**
+ * hw.ops.set_continuous_clk() - Set continuous clock
+ * @ctrl: Pointer to the controller host hardware.
+ * @enable: Bool to control continuous clock request.
+ */
+ void (*set_continuous_clk)(struct dsi_ctrl_hw *ctrl, bool enable);
};
/*
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_cmn.c b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_cmn.c
index 6dde454..7c58c43 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_cmn.c
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_cmn.c
@@ -1420,17 +1420,20 @@
reg = DSI_R32(ctrl, 0x10c);
if (idx & BIT(DSI_FIFO_OVERFLOW)) {
- if (en)
- reg |= (0xf << 16);
- else
- reg &= ~(0xf << 16);
+ if (en) {
+ reg |= (0x1f << 16);
+ reg |= BIT(9);
+ } else {
+ reg &= ~(0x1f << 16);
+ reg &= ~BIT(9);
+ }
}
if (idx & BIT(DSI_FIFO_UNDERFLOW)) {
if (en)
- reg |= (0xf << 26);
+ reg |= (0x1b << 26);
else
- reg &= ~(0xf << 26);
+ reg &= ~(0x1b << 26);
}
if (idx & BIT(DSI_LP_Rx_TIMEOUT)) {
@@ -1493,3 +1496,16 @@
return rc;
}
+
+void dsi_ctrl_hw_cmn_set_continuous_clk(struct dsi_ctrl_hw *ctrl, bool enable)
+{
+ u32 reg = 0;
+
+ reg = DSI_R32(ctrl, DSI_LANE_CTRL);
+ if (enable)
+ reg |= BIT(28);
+ else
+ reg &= ~BIT(28);
+ DSI_W32(ctrl, DSI_LANE_CTRL, reg);
+ wmb(); /* make sure request is set */
+}
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h b/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h
index 6540182..3b2ef70 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h
@@ -404,6 +404,7 @@
* @ignore_rx_eot: Ignore Rx EOT packets if set to true.
* @append_tx_eot: Append EOT packets for forward transmissions if set to
* true.
+ * @force_hs_clk_lane: Send continuous clock to the panel.
*/
struct dsi_host_common_cfg {
enum dsi_pixel_format dst_format;
@@ -422,6 +423,7 @@
u32 t_clk_pre;
bool ignore_rx_eot;
bool append_tx_eot;
+ bool force_hs_clk_lane;
};
/**
@@ -598,6 +600,7 @@
DSI_FIFO_OVERFLOW = 1,
DSI_FIFO_UNDERFLOW,
DSI_LP_Rx_TIMEOUT,
+ DSI_ERR_INTR_ALL,
};
#endif /* _DSI_DEFS_H_ */
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_display.c b/drivers/gpu/drm/msm/dsi-staging/dsi_display.c
index fbf66dc..d58a746 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_display.c
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_display.c
@@ -59,7 +59,8 @@
static struct dsi_display *primary_display;
static struct dsi_display *secondary_display;
-static void dsi_display_mask_ctrl_error_interrupts(struct dsi_display *display)
+static void dsi_display_mask_ctrl_error_interrupts(struct dsi_display *display,
+ u32 mask, bool enable)
{
int i;
struct dsi_display_ctrl *ctrl;
@@ -72,7 +73,25 @@
ctrl = &display->ctrl[i];
if (!ctrl)
continue;
- dsi_ctrl_mask_error_status_interrupts(ctrl->ctrl);
+ dsi_ctrl_mask_error_status_interrupts(ctrl->ctrl, mask, enable);
+ }
+}
+
+static void dsi_display_set_ctrl_esd_check_flag(struct dsi_display *display,
+ bool enable)
+{
+ int i;
+ struct dsi_display_ctrl *ctrl;
+
+ if (!display)
+ return;
+
+ for (i = 0; (i < display->ctrl_count) &&
+ (i < MAX_DSI_CTRLS_PER_DISPLAY); i++) {
+ ctrl = &display->ctrl[i];
+ if (!ctrl)
+ continue;
+ ctrl->ctrl->esd_check_underway = enable;
}
}
@@ -671,10 +690,6 @@
}
}
exit:
- /* mask only error interrupts */
- if (rc <= 0)
- dsi_display_mask_ctrl_error_interrupts(display);
-
dsi_display_cmd_engine_disable(display);
done:
return rc;
@@ -715,6 +730,7 @@
struct dsi_panel *panel;
u32 status_mode;
int rc = 0x1;
+ u32 mask;
if (!dsi_display || !dsi_display->panel)
return -EINVAL;
@@ -730,6 +746,12 @@
}
SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
+ /* Prevent another ESD check,when ESD recovery is underway */
+ if (atomic_read(&panel->esd_recovery_pending)) {
+ dsi_panel_release_panel_lock(panel);
+ return rc;
+ }
+
if (te_check_override && gpio_is_valid(dsi_display->disp_te_gpio))
status_mode = ESD_MODE_PANEL_TE;
else
@@ -738,6 +760,11 @@
dsi_display_clk_ctrl(dsi_display->dsi_clk_handle,
DSI_ALL_CLKS, DSI_CLK_ON);
+ /* Mask error interrupts before attempting ESD read */
+ mask = BIT(DSI_FIFO_OVERFLOW) | BIT(DSI_FIFO_UNDERFLOW);
+ dsi_display_set_ctrl_esd_check_flag(dsi_display, true);
+ dsi_display_mask_ctrl_error_interrupts(dsi_display, mask, true);
+
if (status_mode == ESD_MODE_REG_READ) {
rc = dsi_display_status_reg_read(dsi_display);
} else if (status_mode == ESD_MODE_SW_BTA) {
@@ -749,6 +776,16 @@
panel->esd_config.esd_enabled = false;
}
+ /* Unmask error interrupts */
+ if (rc > 0) {
+ dsi_display_set_ctrl_esd_check_flag(dsi_display, false);
+ dsi_display_mask_ctrl_error_interrupts(dsi_display, mask,
+ false);
+ } else {
+ /* Handle Panel failures during display disable sequence */
+ atomic_set(&panel->esd_recovery_pending, 1);
+ }
+
dsi_display_clk_ctrl(dsi_display->dsi_clk_handle,
DSI_ALL_CLKS, DSI_CLK_OFF);
dsi_panel_release_panel_lock(panel);
@@ -838,6 +875,21 @@
return rc;
}
+static void _dsi_display_continuous_clk_ctrl(struct dsi_display *display,
+ bool enable)
+{
+ int i;
+ struct dsi_display_ctrl *ctrl;
+
+ if (!display || !display->panel->host_config.force_hs_clk_lane)
+ return;
+
+ for (i = 0; i < display->ctrl_count; i++) {
+ ctrl = &display->ctrl[i];
+ dsi_ctrl_set_continuous_clk(ctrl->ctrl, enable);
+ }
+}
+
int dsi_display_soft_reset(void *display)
{
struct dsi_display *dsi_display;
@@ -2738,7 +2790,7 @@
static ssize_t dsi_host_transfer(struct mipi_dsi_host *host,
const struct mipi_dsi_msg *msg)
{
- struct dsi_display *display = to_dsi_display(host);
+ struct dsi_display *display;
int rc = 0, ret = 0;
if (!host || !msg) {
@@ -2746,6 +2798,14 @@
return 0;
}
+ display = to_dsi_display(host);
+
+ /* Avoid sending DCS commands when ESD recovery is pending */
+ if (atomic_read(&display->panel->esd_recovery_pending)) {
+ pr_debug("ESD recovery pending\n");
+ return 0;
+ }
+
rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
DSI_ALL_CLKS, DSI_CLK_ON);
if (rc) {
@@ -3044,6 +3104,12 @@
if ((clk & DSI_LINK_CLK) && (new_state == DSI_CLK_OFF) &&
(l_type && DSI_LINK_LP_CLK)) {
/*
+ * If continuous clock is enabled then disable it
+ * before entering into ULPS Mode.
+ */
+ if (display->panel->host_config.force_hs_clk_lane)
+ _dsi_display_continuous_clk_ctrl(display, false);
+ /*
* If ULPS feature is enabled, enter ULPS first.
* However, when blanking the panel, we should enter ULPS
* only if ULPS during suspend feature is enabled.
@@ -3174,6 +3240,9 @@
goto error;
}
}
+
+ if (display->panel->host_config.force_hs_clk_lane)
+ _dsi_display_continuous_clk_ctrl(display, true);
}
/* enable dsi to serve irqs */
@@ -5853,6 +5922,8 @@
mode = display->panel->cur_mode;
+ dsi_display_set_ctrl_esd_check_flag(display, false);
+
if (mode->dsi_mode_flags & DSI_MODE_FLAG_DMS) {
if (display->is_cont_splash_enabled) {
pr_err("DMS is not supposed to be set on first frame\n");
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_drm.c b/drivers/gpu/drm/msm/dsi-staging/dsi_drm.c
index 6b5bfb4..250314b 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_drm.c
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_drm.c
@@ -139,8 +139,12 @@
return;
}
- if (!c_bridge || !c_bridge->display)
+ if (!c_bridge || !c_bridge->display || !c_bridge->display->panel) {
pr_err("Incorrect bridge details\n");
+ return;
+ }
+
+ atomic_set(&c_bridge->display->panel->esd_recovery_pending, 0);
/* By this point mode should have been validated through mode_fixup */
rc = dsi_display_set_mode(c_bridge->display,
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c
index dab85f4..f0ea211 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c
@@ -1076,6 +1076,8 @@
host->append_tx_eot = of_property_read_bool(of_node,
"qcom,mdss-dsi-tx-eot-append");
+ host->force_hs_clk_lane = of_property_read_bool(of_node,
+ "qcom,mdss-dsi-force-clock-lane-hs");
return 0;
}
@@ -3720,11 +3722,14 @@
mutex_lock(&panel->panel_lock);
- rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_OFF);
- if (rc) {
- pr_err("[%s] failed to send DSI_CMD_SET_OFF cmds, rc=%d\n",
- panel->name, rc);
- goto error;
+ /* Avoid sending panel off commands when ESD recovery is underway */
+ if (!atomic_read(&panel->esd_recovery_pending)) {
+ rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_OFF);
+ if (rc) {
+ pr_err("[%s] failed to send DSI_CMD_SET_OFF cmds, rc=%d\n",
+ panel->name, rc);
+ goto error;
+ }
}
panel->panel_initialized = false;
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h
index c0ecb7f..f6a9c60 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h
@@ -180,6 +180,7 @@
bool ulps_enabled;
bool ulps_suspend_enabled;
bool allow_phy_power_off;
+ atomic_t esd_recovery_pending;
bool panel_initialized;
bool te_using_watchdog_timer;
diff --git a/drivers/gpu/drm/msm/sde/sde_color_processing.c b/drivers/gpu/drm/msm/sde/sde_color_processing.c
index 218509e..8680449b 100644
--- a/drivers/gpu/drm/msm/sde/sde_color_processing.c
+++ b/drivers/gpu/drm/msm/sde/sde_color_processing.c
@@ -1297,6 +1297,33 @@
/* placeholder for operations needed during resume */
}
+void sde_cp_crtc_clear(struct drm_crtc *crtc)
+{
+ struct sde_crtc *sde_crtc = NULL;
+ unsigned long flags;
+
+ if (!crtc) {
+ DRM_ERROR("crtc %pK\n", crtc);
+ return;
+ }
+ sde_crtc = to_sde_crtc(crtc);
+ if (!sde_crtc) {
+ DRM_ERROR("sde_crtc %pK\n", sde_crtc);
+ return;
+ }
+
+ mutex_lock(&sde_crtc->crtc_cp_lock);
+ list_del_init(&sde_crtc->active_list);
+ list_del_init(&sde_crtc->dirty_list);
+ list_del_init(&sde_crtc->ad_active);
+ list_del_init(&sde_crtc->ad_dirty);
+ mutex_unlock(&sde_crtc->crtc_cp_lock);
+
+ spin_lock_irqsave(&sde_crtc->spin_lock, flags);
+ list_del_init(&sde_crtc->user_event_list);
+ spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
+}
+
static void dspp_pcc_install_property(struct drm_crtc *crtc)
{
char feature_name[256];
diff --git a/drivers/gpu/drm/msm/sde/sde_color_processing.h b/drivers/gpu/drm/msm/sde/sde_color_processing.h
index 620db26..fb8ee1f 100644
--- a/drivers/gpu/drm/msm/sde/sde_color_processing.h
+++ b/drivers/gpu/drm/msm/sde/sde_color_processing.h
@@ -116,6 +116,12 @@
void sde_cp_crtc_resume(struct drm_crtc *crtc);
/**
+ * sde_cp_crtc_clear: Clear the active list and dirty list of crtc features
+ * @crtc: Pointer to crtc.
+ */
+void sde_cp_crtc_clear(struct drm_crtc *crtc);
+
+/**
* sde_cp_ad_interrupt: Api to enable/disable ad interrupt
* @crtc: Pointer to crtc.
* @en: Variable to enable/disable interrupt.
diff --git a/drivers/gpu/drm/msm/sde/sde_crtc.c b/drivers/gpu/drm/msm/sde/sde_crtc.c
index b9c4b52..34d8400 100644
--- a/drivers/gpu/drm/msm/sde/sde_crtc.c
+++ b/drivers/gpu/drm/msm/sde/sde_crtc.c
@@ -4918,6 +4918,8 @@
sde_crtc = to_sde_crtc(crtc);
cstate = to_sde_crtc_state(crtc_state);
+ sde_cp_crtc_clear(crtc);
+
for (prop_idx = 0; prop_idx < CRTC_PROP_COUNT; prop_idx++) {
uint64_t val = cstate->property_values[prop_idx].value;
uint64_t def;
diff --git a/drivers/gpu/drm/msm/sde/sde_kms.c b/drivers/gpu/drm/msm/sde/sde_kms.c
index 620aae9..9a4c785 100644
--- a/drivers/gpu/drm/msm/sde/sde_kms.c
+++ b/drivers/gpu/drm/msm/sde/sde_kms.c
@@ -1686,6 +1686,16 @@
drm_for_each_crtc(crtc, dev)
sde_crtc_timeline_status(crtc);
+ if (mutex_is_locked(&dev->mode_config.mutex)) {
+ /*
+ *Probably locked from last close dumping status anyway
+ */
+ SDE_ERROR("dumping conn_timeline without mode_config lock\n");
+ drm_for_each_connector(conn, dev)
+ sde_conn_timeline_status(conn);
+ return;
+ }
+
mutex_lock(&dev->mode_config.mutex);
drm_for_each_connector(conn, dev)
sde_conn_timeline_status(conn);
diff --git a/drivers/gpu/drm/msm/sde/sde_plane.c b/drivers/gpu/drm/msm/sde/sde_plane.c
index 4f21b39..be6e756 100644
--- a/drivers/gpu/drm/msm/sde/sde_plane.c
+++ b/drivers/gpu/drm/msm/sde/sde_plane.c
@@ -831,7 +831,6 @@
input_fence = pstate->input_fence;
if (input_fence) {
- psde->is_error = false;
prefix = sde_sync_get_name_prefix(input_fence);
rc = sde_sync_wait(input_fence, wait_ms);
@@ -971,8 +970,15 @@
ret = sde_format_populate_layout(aspace, fb, &pipe_cfg->layout);
if (ret == -EAGAIN)
SDE_DEBUG_PLANE(psde, "not updating same src addrs\n");
- else if (ret)
+ else if (ret) {
SDE_ERROR_PLANE(psde, "failed to get format layout, %d\n", ret);
+
+ /*
+ * Force solid fill color on error. This is to prevent
+ * smmu faults during secure session transition.
+ */
+ psde->is_error = true;
+ }
else if (psde->pipe_hw->ops.setup_sourceaddress) {
SDE_EVT32_VERBOSE(psde->pipe_hw->idx,
pipe_cfg->layout.width,
diff --git a/drivers/mailbox/qcom-rpmh-mailbox.c b/drivers/mailbox/qcom-rpmh-mailbox.c
index 9f699db..57329f7 100644
--- a/drivers/mailbox/qcom-rpmh-mailbox.c
+++ b/drivers/mailbox/qcom-rpmh-mailbox.c
@@ -1312,6 +1312,7 @@
.driver = {
.name = KBUILD_MODNAME,
.of_match_table = rsc_drv_match,
+ .suppress_bind_attrs = true,
},
};
diff --git a/drivers/media/platform/msm/sde/rotator/sde_rotator_r3.c b/drivers/media/platform/msm/sde/rotator/sde_rotator_r3.c
index 84efd3d..eeca9f3 100644
--- a/drivers/media/platform/msm/sde/rotator/sde_rotator_r3.c
+++ b/drivers/media/platform/msm/sde/rotator/sde_rotator_r3.c
@@ -1496,7 +1496,7 @@
(fmt->bits[C0_G_Y] << 0);
/* alpha control */
- if (fmt->bits[C3_ALPHA] || fmt->alpha_enable) {
+ if (fmt->alpha_enable || (!fmt->is_yuv && (fmt->unpack_count == 4))) {
dst_format |= BIT(8);
if (!fmt->alpha_enable) {
dst_format |= BIT(14);
diff --git a/drivers/power/reset/msm-poweroff.c b/drivers/power/reset/msm-poweroff.c
index 0c520f8..0b8c212 100644
--- a/drivers/power/reset/msm-poweroff.c
+++ b/drivers/power/reset/msm-poweroff.c
@@ -150,9 +150,6 @@
if (ret)
pr_err("Failed to set secure DLOAD mode: %d\n", ret);
- if (!on)
- scm_disable_sdi();
-
dload_mode_enabled = on;
}
@@ -212,7 +209,7 @@
#else
static void set_dload_mode(int on)
{
- scm_disable_sdi();
+ return;
}
static void enable_emergency_dload_mode(void)
@@ -412,6 +409,7 @@
msm_trigger_wdog_bite();
#endif
+ scm_disable_sdi();
halt_spmi_pmic_arbiter();
deassert_ps_hold();
@@ -423,6 +421,7 @@
pr_notice("Powering off the SoC\n");
set_dload_mode(0);
+ scm_disable_sdi();
qpnp_pon_system_pwr_off(PON_POWER_OFF_SHUTDOWN);
halt_spmi_pmic_arbiter();
@@ -675,6 +674,8 @@
scm_deassert_ps_hold_supported = true;
set_dload_mode(download_mode);
+ if (!download_mode)
+ scm_disable_sdi();
return 0;
diff --git a/drivers/power/supply/qcom/qg-core.h b/drivers/power/supply/qcom/qg-core.h
index f21b2a8..b3bf42a 100644
--- a/drivers/power/supply/qcom/qg-core.h
+++ b/drivers/power/supply/qcom/qg-core.h
@@ -54,6 +54,7 @@
int esr_qual_i_ua;
int esr_qual_v_uv;
int esr_disable_soc;
+ int esr_min_ibat_ua;
bool hold_soc_while_full;
bool linearize_soc;
bool cl_disable;
diff --git a/drivers/power/supply/qcom/qg-reg.h b/drivers/power/supply/qcom/qg-reg.h
index e0f400d..894e076 100644
--- a/drivers/power/supply/qcom/qg-reg.h
+++ b/drivers/power/supply/qcom/qg-reg.h
@@ -41,6 +41,9 @@
#define QG_DATA_CTL1_REG 0x41
#define MASTER_HOLD_OR_CLR_BIT BIT(0)
+#define QG_DATA_CTL2_REG 0x42
+#define BURST_AVG_HOLD_FOR_READ_BIT BIT(0)
+
#define QG_MODE_CTL1_REG 0x43
#define PARALLEL_IBAT_SENSE_EN_BIT BIT(7)
@@ -97,6 +100,8 @@
#define QG_LAST_ADC_V_DATA0_REG 0xC0
#define QG_LAST_ADC_I_DATA0_REG 0xC2
+#define QG_LAST_BURST_AVG_I_DATA0_REG 0xC6
+
#define QG_LAST_S3_SLEEP_V_DATA0_REG 0xCC
/* SDAM offsets */
diff --git a/drivers/power/supply/qcom/qg-util.c b/drivers/power/supply/qcom/qg-util.c
index 824d914..85efdbf 100644
--- a/drivers/power/supply/qcom/qg-util.c
+++ b/drivers/power/supply/qcom/qg-util.c
@@ -332,3 +332,38 @@
return rc;
}
+
+int qg_get_battery_current(struct qpnp_qg *chip, int *ibat_ua)
+{
+ int rc = 0, last_ibat = 0;
+
+ if (chip->battery_missing) {
+ *ibat_ua = 0;
+ return 0;
+ }
+
+ /* hold data */
+ rc = qg_masked_write(chip, chip->qg_base + QG_DATA_CTL2_REG,
+ BURST_AVG_HOLD_FOR_READ_BIT,
+ BURST_AVG_HOLD_FOR_READ_BIT);
+ if (rc < 0) {
+ pr_err("Failed to hold burst-avg data rc=%d\n", rc);
+ goto release;
+ }
+
+ rc = qg_read(chip, chip->qg_base + QG_LAST_BURST_AVG_I_DATA0_REG,
+ (u8 *)&last_ibat, 2);
+ if (rc < 0) {
+ pr_err("Failed to read LAST_BURST_AVG_I reg, rc=%d\n", rc);
+ goto release;
+ }
+
+ last_ibat = sign_extend32(last_ibat, 15);
+ *ibat_ua = I_RAW_TO_UA(last_ibat);
+
+release:
+ /* release */
+ qg_masked_write(chip, chip->qg_base + QG_DATA_CTL2_REG,
+ BURST_AVG_HOLD_FOR_READ_BIT, 0);
+ return rc;
+}
diff --git a/drivers/power/supply/qcom/qg-util.h b/drivers/power/supply/qcom/qg-util.h
index bb17afb..2dbafe7 100644
--- a/drivers/power/supply/qcom/qg-util.h
+++ b/drivers/power/supply/qcom/qg-util.h
@@ -25,5 +25,6 @@
bool is_parallel_enabled(struct qpnp_qg *chip);
int qg_write_monotonic_soc(struct qpnp_qg *chip, int msoc);
int qg_get_battery_temp(struct qpnp_qg *chip, int *batt_temp);
+int qg_get_battery_current(struct qpnp_qg *chip, int *ibat_ua);
#endif
diff --git a/drivers/power/supply/qcom/qpnp-qg.c b/drivers/power/supply/qcom/qpnp-qg.c
index 6ecde06..d1b6bea 100644
--- a/drivers/power/supply/qcom/qpnp-qg.c
+++ b/drivers/power/supply/qcom/qpnp-qg.c
@@ -45,12 +45,12 @@
debug_mask, qg_debug_mask, int, 0600
);
-static int qg_esr_mod_count = 10;
+static int qg_esr_mod_count = 30;
module_param_named(
esr_mod_count, qg_esr_mod_count, int, 0600
);
-static int qg_esr_count = 5;
+static int qg_esr_count = 3;
module_param_named(
esr_count, qg_esr_count, int, 0600
);
@@ -854,7 +854,7 @@
static int qg_esr_estimate(struct qpnp_qg *chip)
{
- int rc, i, ibat;
+ int rc, i, ibat = 0;
u8 esr_done_count, reg0 = 0, reg1 = 0;
bool is_charging = false;
@@ -862,13 +862,17 @@
return 0;
/*
- * Charge - enable ESR estimation only during fast-charging.
+ * Charge - enable ESR estimation if IBAT > MIN_IBAT.
* Discharge - enable ESR estimation only if enabled via DT.
*/
+ rc = qg_get_battery_current(chip, &ibat);
+ if (rc < 0)
+ return rc;
if (chip->charge_status == POWER_SUPPLY_STATUS_CHARGING &&
- chip->charge_type != POWER_SUPPLY_CHARGE_TYPE_FAST) {
+ ibat > chip->dt.esr_min_ibat_ua) {
qg_dbg(chip, QG_DEBUG_ESR,
- "Skip ESR, Not in fast-charge (CC)\n");
+ "Skip CHG ESR, Fails IBAT ibat(%d) min_ibat(%d)\n",
+ ibat, chip->dt.esr_min_ibat_ua);
return 0;
}
@@ -1002,6 +1006,8 @@
pr_err("Failed to release master, rc=%d\n", rc);
goto done;
}
+ /* FIFOs restarted */
+ chip->last_fifo_update_time = ktime_get();
if (chip->esr_avg) {
chip->kdata.param[QG_ESR].data = chip->esr_avg;
@@ -1508,47 +1514,6 @@
return DEFAULT_BATT_TYPE;
}
-static int qg_get_battery_current(struct qpnp_qg *chip, int *ibat_ua)
-{
- int rc = 0, last_ibat = 0;
- u32 fifo_length = 0;
-
- if (chip->battery_missing) {
- *ibat_ua = 0;
- return 0;
- }
-
- if (chip->parallel_enabled) {
- /* read the last real-time FIFO */
- rc = get_fifo_length(chip, &fifo_length, true);
- if (rc < 0) {
- pr_err("Failed to read RT FIFO length, rc=%d\n", rc);
- return rc;
- }
- fifo_length = (fifo_length == 0) ? 0 : fifo_length - 1;
- fifo_length *= 2;
- rc = qg_read(chip, chip->qg_base + QG_I_FIFO0_DATA0_REG +
- fifo_length, (u8 *)&last_ibat, 2);
- if (rc < 0) {
- pr_err("Failed to read FIFO_I_%d reg, rc=%d\n",
- fifo_length / 2, rc);
- return rc;
- }
- } else {
- rc = qg_read(chip, chip->qg_base + QG_LAST_ADC_I_DATA0_REG,
- (u8 *)&last_ibat, 2);
- if (rc < 0) {
- pr_err("Failed to read LAST_ADV_I reg, rc=%d\n", rc);
- return rc;
- }
- }
-
- last_ibat = sign_extend32(last_ibat, 15);
- *ibat_ua = I_RAW_TO_UA(last_ibat);
-
- return rc;
-}
-
static int qg_get_battery_voltage(struct qpnp_qg *chip, int *vbat_uv)
{
int rc = 0;
@@ -3115,6 +3080,7 @@
#define DEFAULT_ESR_QUAL_CURRENT_UA 130000
#define DEFAULT_ESR_QUAL_VBAT_UV 7000
#define DEFAULT_ESR_DISABLE_SOC 1000
+#define ESR_CHG_MIN_IBAT_UA (-450000)
static int qg_parse_dt(struct qpnp_qg *chip)
{
int rc = 0;
@@ -3333,6 +3299,12 @@
else
chip->dt.esr_disable_soc = temp * 100;
+ rc = of_property_read_u32(node, "qcom,esr-chg-min-ibat-ua", &temp);
+ if (rc < 0)
+ chip->dt.esr_min_ibat_ua = ESR_CHG_MIN_IBAT_UA;
+ else
+ chip->dt.esr_min_ibat_ua = (int)temp;
+
chip->dt.qg_ext_sense = of_property_read_bool(node, "qcom,qg-ext-sns");
/* Capacity learning params*/
diff --git a/drivers/power/supply/qcom/qpnp-smb5.c b/drivers/power/supply/qcom/qpnp-smb5.c
index 2a997dd..122c0869 100644
--- a/drivers/power/supply/qcom/qpnp-smb5.c
+++ b/drivers/power/supply/qcom/qpnp-smb5.c
@@ -210,6 +210,9 @@
int wd_bark_time;
int batt_profile_fcc_ua;
int batt_profile_fv_uv;
+ int term_current_src;
+ int term_current_thresh_hi_ma;
+ int term_current_thresh_lo_ma;
};
struct smb5 {
@@ -408,6 +411,18 @@
chg->otg_cl_ua = (chip->chg.smb_version == PMI632_SUBTYPE) ?
MICRO_1PA : MICRO_1P5A;
+ rc = of_property_read_u32(node, "qcom,chg-term-src",
+ &chip->dt.term_current_src);
+ if (rc < 0)
+ chip->dt.term_current_src = ITERM_SRC_UNSPECIFIED;
+
+ rc = of_property_read_u32(node, "qcom,chg-term-current-ma",
+ &chip->dt.term_current_thresh_hi_ma);
+
+ if (chip->dt.term_current_src == ITERM_SRC_ADC)
+ rc = of_property_read_u32(node, "qcom,chg-term-base-current-ma",
+ &chip->dt.term_current_thresh_lo_ma);
+
if (of_find_property(node, "qcom,thermal-mitigation", &byte_len)) {
chg->thermal_mitigation = devm_kzalloc(chg->dev, byte_len,
GFP_KERNEL);
@@ -490,7 +505,7 @@
static int smb5_get_adc_data(struct smb_charger *chg, int channel,
union power_supply_propval *val)
{
- int rc, ret = 0;
+ int rc = 0;
struct qpnp_vadc_result result;
u8 reg;
@@ -516,6 +531,8 @@
if (IS_ERR(chg->vadc_dev))
return PTR_ERR(chg->vadc_dev);
+ mutex_lock(&chg->vadc_lock);
+
switch (channel) {
case USBIN_VOLTAGE:
/* Store ADC channel config */
@@ -523,7 +540,7 @@
if (rc < 0) {
dev_err(chg->dev,
"Couldn't read ADC config rc=%d\n", rc);
- return rc;
+ goto done;
}
/* Disable all ADC channels except IBAT channel */
@@ -532,44 +549,40 @@
if (rc < 0) {
dev_err(chg->dev,
"Couldn't write ADC config rc=%d\n", rc);
- return rc;
+ goto done;
}
rc = qpnp_vadc_read(chg->vadc_dev, VADC_USB_IN_V_DIV_16_PM5,
&result);
- if (rc < 0) {
+ if (rc < 0)
pr_err("Failed to read USBIN_V over vadc, rc=%d\n", rc);
- ret = rc;
- goto restore;
- }
- val->intval = result.physical;
+ else
+ val->intval = result.physical;
-restore:
/* Restore ADC channel config */
- rc = smblib_write(chg, BATIF_ADC_CHANNEL_EN_REG, reg);
- if (rc < 0) {
+ rc |= smblib_write(chg, BATIF_ADC_CHANNEL_EN_REG, reg);
+ if (rc < 0)
dev_err(chg->dev,
"Couldn't write ADC config rc=%d\n", rc);
- return rc;
- }
- /* If ADC read failed return ADC error */
- if (ret < 0)
- rc = ret;
+
break;
case USBIN_CURRENT:
rc = qpnp_vadc_read(chg->vadc_dev, VADC_USB_IN_I_PM5, &result);
if (rc < 0) {
pr_err("Failed to read USBIN_I over vadc, rc=%d\n", rc);
- return rc;
+ goto done;
}
val->intval = result.physical;
break;
default:
pr_debug("Invalid channel\n");
- return -EINVAL;
+ rc = -EINVAL;
+ break;
}
- return 0;
+done:
+ mutex_unlock(&chg->vadc_lock);
+ return rc;
}
@@ -1219,6 +1232,7 @@
POWER_SUPPLY_PROP_VOLTAGE_MAX,
POWER_SUPPLY_PROP_CURRENT_NOW,
POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT_MAX,
+ POWER_SUPPLY_PROP_CHARGE_TERM_CURRENT,
POWER_SUPPLY_PROP_TEMP,
POWER_SUPPLY_PROP_TECHNOLOGY,
POWER_SUPPLY_PROP_STEP_CHARGING_ENABLED,
@@ -1295,6 +1309,9 @@
val->intval = get_client_vote(chg->fcc_votable,
BATT_PROFILE_VOTER);
break;
+ case POWER_SUPPLY_PROP_CHARGE_TERM_CURRENT:
+ rc = smblib_get_prop_batt_iterm(chg, val);
+ break;
case POWER_SUPPLY_PROP_TEMP:
rc = smblib_get_prop_batt_temp(chg, val);
break;
@@ -1714,6 +1731,77 @@
return 0;
}
+static int smb5_configure_iterm_thresholds_adc(struct smb5 *chip)
+{
+ u8 *buf;
+ int rc = 0;
+ s16 raw_hi_thresh, raw_lo_thresh;
+ struct smb_charger *chg = &chip->chg;
+
+ if (chip->dt.term_current_thresh_hi_ma < -10000 ||
+ chip->dt.term_current_thresh_hi_ma > 10000 ||
+ chip->dt.term_current_thresh_lo_ma < -10000 ||
+ chip->dt.term_current_thresh_lo_ma > 10000) {
+ dev_err(chg->dev, "ITERM threshold out of range rc=%d\n", rc);
+ return -EINVAL;
+ }
+
+ /*
+ * Conversion:
+ * raw (A) = (scaled_mA * ADC_CHG_TERM_MASK) / (10 * 1000)
+ * Note: raw needs to be converted to big-endian format.
+ */
+
+ if (chip->dt.term_current_thresh_hi_ma) {
+ raw_hi_thresh = ((chip->dt.term_current_thresh_hi_ma *
+ ADC_CHG_TERM_MASK) / 10000);
+ raw_hi_thresh = sign_extend32(raw_hi_thresh, 15);
+ buf = (u8 *)&raw_hi_thresh;
+ raw_hi_thresh = buf[1] | (buf[0] << 8);
+
+ rc = smblib_batch_write(chg, CHGR_ADC_ITERM_UP_THD_MSB_REG,
+ (u8 *)&raw_hi_thresh, 2);
+ if (rc < 0) {
+ dev_err(chg->dev, "Couldn't configure ITERM threshold HIGH rc=%d\n",
+ rc);
+ return rc;
+ }
+ }
+
+ if (chip->dt.term_current_thresh_lo_ma) {
+ raw_lo_thresh = ((chip->dt.term_current_thresh_lo_ma *
+ ADC_CHG_TERM_MASK) / 10000);
+ raw_lo_thresh = sign_extend32(raw_lo_thresh, 15);
+ buf = (u8 *)&raw_lo_thresh;
+ raw_lo_thresh = buf[1] | (buf[0] << 8);
+
+ rc = smblib_batch_write(chg, CHGR_ADC_ITERM_LO_THD_MSB_REG,
+ (u8 *)&raw_lo_thresh, 2);
+ if (rc < 0) {
+ dev_err(chg->dev, "Couldn't configure ITERM threshold LOW rc=%d\n",
+ rc);
+ return rc;
+ }
+ }
+
+ return rc;
+}
+
+static int smb5_configure_iterm_thresholds(struct smb5 *chip)
+{
+ int rc = 0;
+
+ switch (chip->dt.term_current_src) {
+ case ITERM_SRC_ADC:
+ rc = smb5_configure_iterm_thresholds_adc(chip);
+ break;
+ default:
+ break;
+ }
+
+ return rc;
+}
+
static int smb5_init_hw(struct smb5 *chip)
{
struct smb_charger *chg = &chip->chg;
@@ -1897,6 +1985,14 @@
return rc;
}
+ /* set termination current threshold values */
+ rc = smb5_configure_iterm_thresholds(chip);
+ if (rc < 0) {
+ pr_err("Couldn't configure ITERM thresholds rc=%d\n",
+ rc);
+ return rc;
+ }
+
/* configure float charger options */
switch (chip->dt.float_option) {
case FLOAT_DCP:
@@ -2602,6 +2698,7 @@
chg->irq_info = smb5_irqs;
chg->die_health = -EINVAL;
chg->otg_present = false;
+ mutex_init(&chg->vadc_lock);
chg->regmap = dev_get_regmap(chg->dev->parent, NULL);
if (!chg->regmap) {
diff --git a/drivers/power/supply/qcom/smb5-lib.c b/drivers/power/supply/qcom/smb5-lib.c
index 23070e6..be0832e 100644
--- a/drivers/power/supply/qcom/smb5-lib.c
+++ b/drivers/power/supply/qcom/smb5-lib.c
@@ -1513,6 +1513,45 @@
return rc;
}
+int smblib_get_prop_batt_iterm(struct smb_charger *chg,
+ union power_supply_propval *val)
+{
+ int rc, temp;
+ u8 stat, buf[2];
+
+ /*
+ * Currently, only ADC comparator-based termination is supported,
+ * hence read only the threshold corresponding to ADC source.
+ * Proceed only if CHGR_ITERM_USE_ANALOG_BIT is 0.
+ */
+ rc = smblib_read(chg, CHGR_ENG_CHARGING_CFG_REG, &stat);
+ if (rc < 0) {
+ smblib_err(chg, "Couldn't read CHGR_ENG_CHARGING_CFG_REG rc=%d\n",
+ rc);
+ return rc;
+ }
+
+ if (stat & CHGR_ITERM_USE_ANALOG_BIT) {
+ val->intval = -EINVAL;
+ return 0;
+ }
+
+ rc = smblib_batch_read(chg, CHGR_ADC_ITERM_UP_THD_MSB_REG, buf, 2);
+
+ if (rc < 0) {
+ smblib_err(chg, "Couldn't read CHGR_ADC_ITERM_UP_THD_MSB_REG rc=%d\n",
+ rc);
+ return rc;
+ }
+
+ temp = buf[1] | (buf[0] << 8);
+ temp = sign_extend32(temp, 15);
+ temp = DIV_ROUND_CLOSEST(temp * 10000, ADC_CHG_TERM_MASK);
+ val->intval = temp;
+
+ return rc;
+}
+
int smblib_get_prop_batt_temp(struct smb_charger *chg,
union power_supply_propval *val)
{
@@ -2027,6 +2066,8 @@
return POWER_SUPPLY_TYPEC_SOURCE_MEDIUM;
case SNK_RP_3P0_BIT:
return POWER_SUPPLY_TYPEC_SOURCE_HIGH;
+ case SNK_RP_SHORT_BIT:
+ return POWER_SUPPLY_TYPEC_NON_COMPLIANT;
default:
break;
}
diff --git a/drivers/power/supply/qcom/smb5-lib.h b/drivers/power/supply/qcom/smb5-lib.h
index e59b11b..5be985e 100644
--- a/drivers/power/supply/qcom/smb5-lib.h
+++ b/drivers/power/supply/qcom/smb5-lib.h
@@ -82,6 +82,7 @@
#define TYPEC_DEFAULT_CURRENT_UA 900000
#define TYPEC_MEDIUM_CURRENT_UA 1500000
#define TYPEC_HIGH_CURRENT_UA 3000000
+#define ADC_CHG_TERM_MASK 32767
enum smb_mode {
PARALLEL_MASTER = 0,
@@ -188,6 +189,12 @@
SUSPEND_INPUT = 4,
};
+enum chg_term_config_src {
+ ITERM_SRC_UNSPECIFIED,
+ ITERM_SRC_ADC,
+ ITERM_SRC_ANALOG
+};
+
struct smb_irq_info {
const char *name;
const irq_handler_t handler;
@@ -295,6 +302,7 @@
/* locks */
struct mutex lock;
struct mutex ps_change_lock;
+ struct mutex vadc_lock;
/* power supplies */
struct power_supply *batt_psy;
@@ -487,6 +495,8 @@
union power_supply_propval *val);
int smblib_get_prop_batt_current_now(struct smb_charger *chg,
union power_supply_propval *val);
+int smblib_get_prop_batt_iterm(struct smb_charger *chg,
+ union power_supply_propval *val);
int smblib_get_prop_batt_temp(struct smb_charger *chg,
union power_supply_propval *val);
int smblib_get_prop_batt_charge_counter(struct smb_charger *chg,
diff --git a/drivers/power/supply/qcom/smb5-reg.h b/drivers/power/supply/qcom/smb5-reg.h
index e8cdda3..e9c4a0f 100644
--- a/drivers/power/supply/qcom/smb5-reg.h
+++ b/drivers/power/supply/qcom/smb5-reg.h
@@ -73,6 +73,11 @@
#define CHGR_FAST_CHARGE_CURRENT_CFG_REG (CHGR_BASE + 0x61)
+#define CHGR_ADC_ITERM_UP_THD_MSB_REG (CHGR_BASE + 0x67)
+#define CHGR_ADC_ITERM_UP_THD_LSB_REG (CHGR_BASE + 0x68)
+#define CHGR_ADC_ITERM_LO_THD_MSB_REG (CHGR_BASE + 0x69)
+#define CHGR_ADC_ITERM_LO_THD_LSB_REG (CHGR_BASE + 0x6A)
+
#define CHGR_NO_SAMPLE_TERM_RCHG_CFG_REG (CHGR_BASE + 0x6B)
#define NO_OF_SAMPLE_FOR_RCHG_SHIFT 2
#define NO_OF_SAMPLE_FOR_RCHG GENMASK(3, 2)
@@ -102,6 +107,10 @@
#define JEITA_CCCOMP_CFG_COLD_REG (CHGR_BASE + 0x93)
#define CHGR_JEITA_THRESHOLD_BASE_REG(i) (CHGR_BASE + 0x94 + (i * 4))
+
+#define CHGR_ENG_CHARGING_CFG_REG (CHGR_BASE + 0xC0)
+#define CHGR_ITERM_USE_ANALOG_BIT BIT(3)
+
/********************************
* DCDC Peripheral Registers *
********************************/
@@ -267,10 +276,11 @@
* TYPEC Peripheral Registers *
********************************/
#define TYPE_C_SNK_STATUS_REG (TYPEC_BASE + 0x06)
-#define DETECTED_SRC_TYPE_MASK GENMASK(3, 1)
+#define DETECTED_SRC_TYPE_MASK GENMASK(3, 0)
#define SNK_RP_STD_BIT BIT(3)
#define SNK_RP_1P5_BIT BIT(2)
#define SNK_RP_3P0_BIT BIT(1)
+#define SNK_RP_SHORT_BIT BIT(0)
#define TYPE_C_SRC_STATUS_REG (TYPEC_BASE + 0x08)
#define DETECTED_SNK_TYPE_MASK GENMASK(4, 0)
diff --git a/drivers/soc/qcom/qmp-debugfs-client.c b/drivers/soc/qcom/qmp-debugfs-client.c
index d7a473e..a327e031 100644
--- a/drivers/soc/qcom/qmp-debugfs-client.c
+++ b/drivers/soc/qcom/qmp-debugfs-client.c
@@ -116,8 +116,8 @@
.driver = {
.name = "debugfs-qmp-client",
.owner = THIS_MODULE,
+ .suppress_bind_attrs = true,
.of_match_table = aop_qmp_match_tbl,
},
};
-
builtin_platform_driver(aop_qmp_msg_driver);
diff --git a/drivers/soc/qcom/rpm-smd.c b/drivers/soc/qcom/rpm-smd.c
index c29cfcb..675551a 100644
--- a/drivers/soc/qcom/rpm-smd.c
+++ b/drivers/soc/qcom/rpm-smd.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2017, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -2138,6 +2138,7 @@
.driver = {
.name = "rpm-smd",
.owner = THIS_MODULE,
+ .suppress_bind_attrs = true,
.of_match_table = msm_rpm_match_table,
},
};
diff --git a/drivers/soc/qcom/system_pm.c b/drivers/soc/qcom/system_pm.c
index 1befdcf..9ef685b 100644
--- a/drivers/soc/qcom/system_pm.c
+++ b/drivers/soc/qcom/system_pm.c
@@ -106,6 +106,7 @@
.probe = sys_pm_probe,
.driver = {
.name = KBUILD_MODNAME,
+ .suppress_bind_attrs = true,
.of_match_table = sys_pm_drv_match,
},
};
diff --git a/drivers/usb/gadget/function/f_gsi.c b/drivers/usb/gadget/function/f_gsi.c
index b7fcc35..0c4baf2 100644
--- a/drivers/usb/gadget/function/f_gsi.c
+++ b/drivers/usb/gadget/function/f_gsi.c
@@ -2565,6 +2565,11 @@
static int gsi_get_status(struct usb_function *f)
{
unsigned int remote_wakeup_en_status = f->func_wakeup_allowed ? 1 : 0;
+ struct f_gsi *gsi = func_to_gsi(f);
+
+ /* Disable function remote wake-up for DPL interface */
+ if (gsi->prot_id == USB_PROT_DIAG_IPA)
+ return 0;
return (remote_wakeup_en_status << FUNC_WAKEUP_ENABLE_SHIFT) |
(1 << FUNC_WAKEUP_CAPABLE_SHIFT);
diff --git a/net/packet/af_packet.c b/net/packet/af_packet.c
index 430a7c7..3ec89bb 100644
--- a/net/packet/af_packet.c
+++ b/net/packet/af_packet.c
@@ -2918,7 +2918,7 @@
if (unlikely(offset < 0))
goto out_free;
} else if (reserve) {
- skb_push(skb, reserve);
+ skb_reserve(skb, -reserve);
}
/* Returns -EFAULT on error */