| commit | b8a033023994c4e59697bb3b16b441b38f258390 | [log] [tgz] |
|---|---|---|
| author | Vineet Gupta <vgupta@synopsys.com> | Wed Mar 11 21:42:37 2015 +0530 |
| committer | Vineet Gupta <vgupta@synopsys.com> | Thu Jun 25 06:00:17 2015 +0530 |
| tree | 2a5524af921d907162b1f476537117a02c02a127 | |
| parent | 470c27e4695add2a4e167467775081870d83185a [diff] |
ARCv2: barriers ARCv2 based HS38 cores are weakly ordered and thus explicit barriers for kernel proper. SMP barrier is provided by DMB instruction which also guarantees local barrier hence used as backend of smp_*mb() as well as *mb() APIs Also hookup barriers into MMIO accessors to avoid ordering issues in IO Cc: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>