Merge "drm/msm: move dynamic fps and seamless updates" into msm-4.8
diff --git a/drivers/gpu/drm/msm/msm_atomic.c b/drivers/gpu/drm/msm/msm_atomic.c
index d13b396..a241b7a 100644
--- a/drivers/gpu/drm/msm/msm_atomic.c
+++ b/drivers/gpu/drm/msm/msm_atomic.c
@@ -279,13 +279,7 @@
drm_atomic_helper_update_legacy_modeset_state(dev, old_state);
- msm_atomic_wait_for_commit_done(dev, old_state,
- MSM_MODE_FLAG_VBLANK_PRE_MODESET);
-
msm_crtc_set_mode(dev, old_state);
-
- msm_atomic_wait_for_commit_done(dev, old_state,
- MSM_MODE_FLAG_VBLANK_POST_MODESET);
}
/**
@@ -337,6 +331,10 @@
}
}
+ /* ensure bridge/encoder updates happen on same vblank */
+ msm_atomic_wait_for_commit_done(dev, old_state,
+ MSM_MODE_FLAG_VBLANK_PRE_MODESET);
+
for_each_connector_in_state(old_state, connector, old_conn_state, i) {
const struct drm_encoder_helper_funcs *funcs;
struct drm_encoder *encoder;
@@ -349,9 +347,6 @@
connector->state->crtc->state))
continue;
- if (msm_is_mode_seamless(&connector->state->crtc->state->mode))
- continue;
-
encoder = connector->state->best_encoder;
funcs = encoder->helper_private;
diff --git a/drivers/gpu/drm/msm/msm_kms.h b/drivers/gpu/drm/msm/msm_kms.h
index e811103..22493cb 100644
--- a/drivers/gpu/drm/msm/msm_kms.h
+++ b/drivers/gpu/drm/msm/msm_kms.h
@@ -33,8 +33,6 @@
#define MSM_MODE_FLAG_SEAMLESS_DYNAMIC_FPS (1<<0)
/* Transition to new mode requires a wait-for-vblank before the modeset */
#define MSM_MODE_FLAG_VBLANK_PRE_MODESET (1<<1)
-/* Transition to new mode requires a wait-for-vblank after the modeset */
-#define MSM_MODE_FLAG_VBLANK_POST_MODESET (1<<2)
/* As there are different display controller blocks depending on the
* snapdragon version, the kms support is split out and the appropriate
diff --git a/drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c b/drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c
index 1b38c08..9219fa0 100644
--- a/drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c
@@ -216,9 +216,6 @@
/*
* Modifying mode has consequences when the mode comes back to us
*/
- if (phys_enc->hw_intf->cap->quirks & SDE_INTF_QUIRK_STAGGER_LM_UPDATE)
- adj_mode->private_flags |= MSM_MODE_FLAG_VBLANK_POST_MODESET;
-
return true;
}
@@ -391,26 +388,6 @@
phys_enc->cached_mode = *adj_mode;
DBG("intf %d, caching mode:", phys_enc->hw_intf->idx);
drm_mode_debug_printmodeline(adj_mode);
-
- if (msm_is_mode_dynamic_fps(adj_mode)) {
- DBG("seamless dynamic fps transition");
- /* Connector has already updated the HFP/VFP values
- * Encoder needs to program in the new values
- * An enable of the timing engine is not required
- * But a Flush of the INTF block is required
- * Encoder mode_set happens first
- * 1. msm_atomic_layer waits for VSYNC so DSI and INTF are
- * updated in same VSYNC
- * 2. Update intf timing with new porch values
- * 3. Flush INTF config
- * 4. DSI config flushes
- * 5. 8996 workaround:
- * Cannot update INTF timing and Layer Mixers
- * in same VSYNC. In case there is an immediate commit
- * after this, wait another VSYNC
- */
- sde_encoder_phys_vid_setup_timing_engine(phys_enc);
- }
}
static void sde_encoder_phys_vid_enable(struct sde_encoder_phys *phys_enc)
@@ -429,11 +406,13 @@
sde_encoder_phys_vid_setup_timing_engine(phys_enc);
+ sde_encoder_phys_vid_flush_intf(phys_enc);
+
/* Register for interrupt unless we're the slave encoder */
if (phys_enc->split_role != ENC_ROLE_SLAVE)
ret = sde_encoder_phys_vid_register_irq(phys_enc);
- if (!ret) {
+ if (!ret && !phys_enc->enabled) {
unsigned long lock_flags = 0;
/* Now enable timing engine */
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_catalog.h b/drivers/gpu/drm/msm/sde/sde_hw_catalog.h
index 918cf8d..0b0effa 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_catalog.h
+++ b/drivers/gpu/drm/msm/sde/sde_hw_catalog.h
@@ -170,26 +170,15 @@
};
/**
- * INTF sub-blocks
- * @SDE_INTF_QUIRK_STAGGER_LM_UPDATE HW quirk requires LM and Timing engine
- * be flushed in different VBLANKs
- */
-enum {
- SDE_INTF_QUIRK_STAGGER_LM_UPDATE = BIT(0)
-};
-
-/**
* MACRO SDE_HW_BLK_INFO - information of HW blocks inside SDE
* @id: enum identifying this block
* @base: register base offset to mdss
* @features bit mask identifying sub-blocks/features
- * @quirks: bit mask listing chip specific behaviors
*/
#define SDE_HW_BLK_INFO \
u32 id; \
u32 base; \
unsigned long features; \
- unsigned long quirks
/**
* MACRO SDE_HW_SUBBLK_INFO - information of HW sub-block inside SDE
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_catalog_8996.c b/drivers/gpu/drm/msm/sde/sde_hw_catalog_8996.c
index 3aa1413..7a4542a 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_catalog_8996.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_catalog_8996.c
@@ -257,19 +257,15 @@
.intf_count = 4,
.intf = {
{.id = INTF_0, .base = 0x0006B000,
- .quirks = SDE_INTF_QUIRK_STAGGER_LM_UPDATE,
.type = INTF_NONE, .controller_id = 0,
.prog_fetch_lines_worst_case = 21},
{.id = INTF_1, .base = 0x0006B800,
- .quirks = SDE_INTF_QUIRK_STAGGER_LM_UPDATE,
.type = INTF_DSI, .controller_id = 0,
.prog_fetch_lines_worst_case = 21},
{.id = INTF_2, .base = 0x0006C000,
- .quirks = SDE_INTF_QUIRK_STAGGER_LM_UPDATE,
.type = INTF_DSI, .controller_id = 1,
.prog_fetch_lines_worst_case = 21},
{.id = INTF_3, .base = 0x0006C800,
- .quirks = SDE_INTF_QUIRK_STAGGER_LM_UPDATE,
.type = INTF_HDMI, .controller_id = 0,
.prog_fetch_lines_worst_case = 21},
},