tree 74ae1433a9d3923472ba49d47a57a31c0a352de4
parent 9d0394c6bed5b4b78167cc0eea294754a9cb2bbc
author Xia Yang <xiay@nvidia.com> 1456390748 +0900
committer Ben Skeggs <bskeggs@redhat.com> 1457914410 +1000

drm/nouveau/fifo/gk104: fix chid bit mask

Fix the channel id bit mask in FIFO schedule timeout error handling.

FIFO_ENGINE_STATUS_NEXT_ID is bit 27:16 thus 0x0fff0000.
FIFO_ENGINE_STATUS_ID      is bit 11:0  thus 0x00000fff.

Signed-off-by: Xia Yang <xiay@nvidia.com>
Reviewed-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>