| commit | 071ecc812e31cb1fc15a175cf7f09c43f4511136 | [log] [tgz] |
|---|---|---|
| author | Aravind Venkateswaran <aravindh@codeaurora.org> | Wed May 18 15:18:34 2016 -0700 |
| committer | Narendra Muppalla <NarendraM@codeaurora.org> | Fri Jan 20 12:01:50 2017 -0800 |
| tree | af2478d7633c99ecb6237f69ca6e6623db6ad6b7 | |
| parent | 4f60e8d84561bf26b85da18cd49930511e4cd220 [diff] |
clk: msm: mdss: fix DSI PLL programming for msm8998 VCO configuration should be based on the requested vco clock rate and should not factor in the bit clock source divider. In addition, the bit clock source divider for the slave controller should always be set to 1. This will ensure that the PLL is locked at the correct rate. CRs-Fixed: 1019289 Change-Id: Ie5c171e13dcccc711ba03acb38fcd7876e792cee Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>