tree e881d8aefaf87c8e7e7cc37652833841feb11a42
parent 4de2d58bc973caa8988b44ddd11787e57051c843
author Maxime Ripard <maxime.ripard@free-electrons.com> 1459592911 +0200
committer Maxime Ripard <maxime.ripard@free-electrons.com> 1465552187 +0200

clk: sunxi: display: Add per-clock flags

The TCON channel 0 clock that is the parent clock of our pixel clock is
expected to change its rate depending on the resolution we want to output
in our display engine.

However, since it's only a mux, the only way it can do that is by changing
its parents rate.

Allow to give flags in our display clocks description, and add the
CLK_SET_RATE_PARENT flag for the TCON channel 0 flag.

Fixes: a3b4956ee6d9 ("clk: sunxi: display: Add per-clock flags")
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>