ARM: dts: msm: Add thermal zone config for sdm670
Add thermal zone config to monitor virtual silver max,
virtual gold max, gpu virtual max, pop mem sensor, LMH DCVSh
to enable thermal core to set thresholds for the hardware algorithm
and monitor all tsens sensors for vdd restriction.
Change-Id: Ic51595460e3063889211f7235bc220806b2d746a
Signed-off-by: Manaf Meethalavalappu Pallikunhi <manafm@codeaurora.org>
diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi
index 181de62..30253f2 100644
--- a/arch/arm64/boot/dts/qcom/sdm670.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi
@@ -54,6 +54,7 @@
cpu-release-addr = <0x0 0x90000000>;
next-level-cache = <&L2_0>;
qcom,lmh-dcvs = <&lmh_dcvs0>;
+ #cooling-cells = <2>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
@@ -88,6 +89,7 @@
cpu-release-addr = <0x0 0x90000000>;
next-level-cache = <&L2_100>;
qcom,lmh-dcvs = <&lmh_dcvs0>;
+ #cooling-cells = <2>;
L2_100: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
@@ -117,6 +119,7 @@
cpu-release-addr = <0x0 0x90000000>;
next-level-cache = <&L2_200>;
qcom,lmh-dcvs = <&lmh_dcvs0>;
+ #cooling-cells = <2>;
L2_200: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
@@ -146,6 +149,7 @@
cpu-release-addr = <0x0 0x90000000>;
next-level-cache = <&L2_300>;
qcom,lmh-dcvs = <&lmh_dcvs0>;
+ #cooling-cells = <2>;
L2_300: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
@@ -175,6 +179,7 @@
cpu-release-addr = <0x0 0x90000000>;
next-level-cache = <&L2_400>;
qcom,lmh-dcvs = <&lmh_dcvs0>;
+ #cooling-cells = <2>;
L2_400: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
@@ -204,6 +209,7 @@
cpu-release-addr = <0x0 0x90000000>;
next-level-cache = <&L2_500>;
qcom,lmh-dcvs = <&lmh_dcvs0>;
+ #cooling-cells = <2>;
L2_500: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
@@ -233,6 +239,7 @@
cpu-release-addr = <0x0 0x90000000>;
next-level-cache = <&L2_600>;
qcom,lmh-dcvs = <&lmh_dcvs1>;
+ #cooling-cells = <2>;
L2_600: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x40000>;
@@ -262,6 +269,7 @@
cpu-release-addr = <0x0 0x90000000>;
next-level-cache = <&L2_700>;
qcom,lmh-dcvs = <&lmh_dcvs1>;
+ #cooling-cells = <2>;
L2_700: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x40000>;