commit 0955c6caef2247dd444fb04447472946b22cade1
author Lynus Vaz <lvaz@codeaurora.org> Mon Feb 20 18:59:44 2017 +0530
committer Gerrit - the friendly Code Review server <code-review@localhost> Sun Mar 19 23:18:12 2017 -0700
tree 781d7ce7fd7d0a86c3983e8d71604df88e349baa
parent c9e440da7c8a90306a29c3842676e286be6777bb

msm: kgsl: Protect the IOMMU register range on A6XX

Get the IOMMU register range on A6XX and add them to the list of
protected registers, to make sure they cannot be read without
disabling protected mode.

Change-Id: I4bc50bf406d3b46950603494978f86d3c2c69f09
Signed-off-by: Lynus Vaz <lvaz@codeaurora.org>

drivers/gpu/msm/adreno_a6xx.c

diff --git a/drivers/gpu/msm/adreno_a6xx.c b/drivers/gpu/msm/adreno_a6xx.c
index 7208672..ef555ca 100644
--- a/drivers/gpu/msm/adreno_a6xx.c
+++ b/drivers/gpu/msm/adreno_a6xx.c
@@ -134,16 +134,34 @@
 static void a6xx_protect_init(struct adreno_device *adreno_dev)
 {
 	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
+	struct kgsl_protected_registers *mmu_prot = NULL;
 	int i;
+	int num_sets;
+	int num_sets_array;
+	unsigned int mmu_base;
+	unsigned int mmu_range;
 
 	/* enable access protection to privileged registers */
 	kgsl_regwrite(device, A6XX_CP_PROTECT_CNTL, 0x00000007);
 
-	if (ARRAY_SIZE(a6xx_protected_regs_group) >
-			adreno_dev->gpucore->num_protected_regs)
-		WARN(1, "Size exceeds the num of protection regs available\n");
+	num_sets = ARRAY_SIZE(a6xx_protected_regs_group);
 
-	for (i = 0; i < ARRAY_SIZE(a6xx_protected_regs_group); i++) {
+	mmu_prot = kgsl_mmu_get_prot_regs(&device->mmu);
+
+	if (mmu_prot) {
+		mmu_base = mmu_prot->base;
+		mmu_range = 1 << mmu_prot->range;
+		num_sets += DIV_ROUND_UP(mmu_range, 0x2000);
+	}
+
+	if (num_sets > adreno_dev->gpucore->num_protected_regs) {
+		WARN(1, "Size exceeds the num of protection regs available\n");
+		num_sets = adreno_dev->gpucore->num_protected_regs;
+	}
+
+	num_sets_array = min_t(unsigned int,
+		ARRAY_SIZE(a6xx_protected_regs_group), num_sets);
+	for (i = 0; i < num_sets_array; i++) {
 		struct a6xx_protected_regs *regs =
 					&a6xx_protected_regs_group[i];
 
@@ -152,6 +170,16 @@
 				(regs->read_protect << 31));
 	}
 
+	for (; i < num_sets; i++) {
+		unsigned int cur_range = min_t(unsigned int, mmu_range,
+						0x2000);
+
+		kgsl_regwrite(device, A6XX_CP_PROTECT_REG + i,
+			mmu_base | ((cur_range - 1) << 18) | (1 << 31));
+
+		mmu_base += cur_range;
+		mmu_range -= cur_range;
+	}
 }
 
 static void a6xx_enable_64bit(struct adreno_device *adreno_dev)