tree 1db1f058b17823a6ae4722c21d7f916e129694c4
parent 577fb13199b11d8cd75609183649be4b5561243f
author Seungwon Jeon <tgih.jun@samsung.com> 1398240898 +0900
committer Chris Ball <chris@printf.net> 1399932366 -0400

mmc: add support for HS400 mode of eMMC5.0

This patch adds HS400 mode support for eMMC5.0 device.  HS400 mode is high
speed DDR interface timing from HS200.  Clock frequency is up to 200MHz
and only 8-bit bus width is supported. In addition, tuning process of
HS200 is required to synchronize the command response on the CMD line
because CMD input timing for HS400 mode is the same as HS200 mode.

Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com>
Reviewed-by: Jackey Shen <jackey.shen@amd.com>
Tested-by: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Chris Ball <chris@printf.net>