tree 4a6f49cfbfbf970a565a75d41853b5b19b9235ab
parent 886c73babe5ed681467dfd3b44bee06005229b98
author Stephen Boyd <sboyd@codeaurora.org> 1452297429 -0800
committer Andy Gross <andy.gross@linaro.org> 1456294442 -0600

arm64: dts: Add L2 cache node to msm8916

The msm8916 SoC has an L2 cache for all 4 CPUs. Add it to the
dtsi file so that the cache hierarchy can be probed.

Cc: <devicetree@vger.kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Andy Gross <andy.gross@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>