commit 0b2c3afdaaaa3e577300b2235df43eb8af00020b
author Chris Zankel <chris@zankel.net> Tue Feb 12 10:11:45 2008 -0800
committer Chris Zankel <chris@zankel.net> Wed Feb 13 17:08:18 2008 -0800
tree a19e12791a9d109f61f1edce731f50589302d04d
parent 70e137eb48f62e59dfa5e06d0d01f123e9464f9a

[XTENSA] Fix icache flush for cache aliasing

Set the execution bit in the temporary TLB when we flush the
instruction cache.

Signed-off-by: Chris Zankel <chris@zankel.net>

arch/xtensa/mm/misc.S

diff --git a/arch/xtensa/mm/misc.S b/arch/xtensa/mm/misc.S
index e1f8803..c885664 100644
--- a/arch/xtensa/mm/misc.S
+++ b/arch/xtensa/mm/misc.S
@@ -295,7 +295,7 @@
 ENTRY(__invalidate_icache_page_alias)
 	entry	sp, 16
 
-	addi	a6, a3, (PAGE_KERNEL | _PAGE_HW_WRITE)
+	addi	a6, a3, (PAGE_KERNEL_EXEC | _PAGE_HW_WRITE)
 	mov	a4, a2
 	witlb	a6, a2
 	isync