tree 989c920b532d4d5d7372c275ed828356cff9c581
parent 7ba28813b41120dd67329fd04dc732ea7fef05a0
author Peter De Schrijver <pdeschrijver@nvidia.com> 1365000039 +0300
committer Stephen Warren <swarren@nvidia.com> 1365113445 -0600

clk: tegra: Add PLL post divider table

Some PLLs in Tegra114 don't use a power of 2 mapping for the post divider.
Introduce a table based approach and switch PLLU to it.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>