ARM: zynq: PM: Enable DDR clock stop
The DDR controller can detect idle periods and leverage low power
features clock stop. When new requests occur, the DDRC resumes
normal operation.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
diff --git a/arch/arm/mach-zynq/common.h b/arch/arm/mach-zynq/common.h
index 596ef0b..0edbb69 100644
--- a/arch/arm/mach-zynq/common.h
+++ b/arch/arm/mach-zynq/common.h
@@ -40,6 +40,8 @@
/* Hotplug */
extern void zynq_platform_cpu_die(unsigned int cpu);
+void zynq_pm_late_init(void);
+
static inline void zynq_core_pm_init(void)
{
/* A9 clock gating */