tree bd869102a3f5f6b071d097e756b5e0293572f61c
parent 584c5e2ad3ada1a5ccfffa68347b79c3681cc36e
author françois romieu <romieu@fr.zoreil.com> 1334661100 +0000
committer David S. Miller <davem@davemloft.net> 1334717653 -0400

dmfe: enforce consistent timing delay.

The driver does not always use the same timing for what looks like
the same operations.

- DCR0
  Use the same udelay everywhere for reset. Upper bound is 100 us.
- DCR9
  Use 5us delay for srom clock. 1us delay for phy_write_1bit (writes
  PHY_DATA_[01]) are not changed as they stay withing a 2,5MHz MDIO
  clock range.

Signed-off-by: Francois Romieu <romieu@fr.zoreil.com>
Reviewed-by: Grant Grundler <grundler@parisc-linux.org>
Signed-off-by: David S. Miller <davem@davemloft.net>