tree 729c4e51baf9c05f2362cd6e9b1248130a59d7c6
parent d770e558e21961ad6cfdf0ff7df0eb5d7d4f0754
author Tuomas Tynkkynen <ttynkkynen@nvidia.com> 1431529115 +0300
committer Thierry Reding <treding@nvidia.com> 1437031963 +0200

clk: tegra: Add binding for the Tegra124 DFLL clocksource

The DFLL is the main clocksource for the fast CPU cluster on Tegra124
and also provides automatic CPU rail voltage scaling as well. The DFLL
is a separate IP block from the usual Tegra124 clock-and-reset
controller, so it gets its own node in the device tree.

Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi>
Acked-by: Michael Turquette <mturquette@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>