libata: convert to iomap
Convert libata core layer and LLDs to use iomap.
* managed iomap is used. Pointer to pcim_iomap_table() is cached at
host->iomap and used through out LLDs. This basically replaces
host->mmio_base.
* if possible, pcim_iomap_regions() is used
Most iomap operation conversions are taken from Jeff Garzik
<jgarzik@pobox.com>'s iomap branch.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
diff --git a/drivers/ata/pata_legacy.c b/drivers/ata/pata_legacy.c
index 9532b9b..78b5f71 100644
--- a/drivers/ata/pata_legacy.c
+++ b/drivers/ata/pata_legacy.c
@@ -164,7 +164,7 @@
.qc_prep = ata_qc_prep,
.qc_issue = ata_qc_issue_prot,
- .data_xfer = ata_pio_data_xfer_noirq,
+ .data_xfer = ata_data_xfer_noirq,
.irq_handler = ata_interrupt,
.irq_clear = ata_bmdma_irq_clear,
@@ -187,7 +187,7 @@
.qc_prep = ata_qc_prep,
.qc_issue = ata_qc_issue_prot,
- .data_xfer = ata_pio_data_xfer_noirq,
+ .data_xfer = ata_data_xfer_noirq,
.irq_handler = ata_interrupt,
.irq_clear = ata_bmdma_irq_clear,
@@ -253,31 +253,33 @@
local_irq_save(flags);
/* Perform the 32bit I/O synchronization sequence */
- inb(ap->ioaddr.nsect_addr);
- inb(ap->ioaddr.nsect_addr);
- inb(ap->ioaddr.nsect_addr);
+ ioread8(ap->ioaddr.nsect_addr);
+ ioread8(ap->ioaddr.nsect_addr);
+ ioread8(ap->ioaddr.nsect_addr);
/* Now the data */
if (write_data)
- outsl(ap->ioaddr.data_addr, buf, buflen >> 2);
+ iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
else
- insl(ap->ioaddr.data_addr, buf, buflen >> 2);
+ ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
if (unlikely(slop)) {
u32 pad;
if (write_data) {
memcpy(&pad, buf + buflen - slop, slop);
- outl(le32_to_cpu(pad), ap->ioaddr.data_addr);
+ pad = le32_to_cpu(pad);
+ iowrite32(pad, ap->ioaddr.data_addr);
} else {
- pad = cpu_to_le16(inl(ap->ioaddr.data_addr));
+ pad = ioread32(ap->ioaddr.data_addr);
+ pad = cpu_to_le16(pad);
memcpy(buf + buflen - slop, &pad, slop);
}
}
local_irq_restore(flags);
}
else
- ata_pio_data_xfer_noirq(adev, buf, buflen, write_data);
+ ata_data_xfer_noirq(adev, buf, buflen, write_data);
}
static struct ata_port_operations pdc20230_port_ops = {
@@ -326,8 +328,8 @@
inb(0x3E6);
inb(0x3E6);
- outb(recover << 4 | active, ap->ioaddr.device_addr);
- inb(ap->ioaddr.status_addr);
+ iowrite8(recover << 4 | active, ap->ioaddr.device_addr);
+ ioread8(ap->ioaddr.status_addr);
}
static struct ata_port_operations ht6560a_port_ops = {
@@ -345,7 +347,7 @@
.qc_prep = ata_qc_prep,
.qc_issue = ata_qc_issue_prot,
- .data_xfer = ata_pio_data_xfer, /* Check vlb/noirq */
+ .data_xfer = ata_data_xfer, /* Check vlb/noirq */
.irq_handler = ata_interrupt,
.irq_clear = ata_bmdma_irq_clear,
@@ -379,7 +381,7 @@
inb(0x3E6);
inb(0x3E6);
- outb(recover << 4 | active, ap->ioaddr.device_addr);
+ iowrite8(recover << 4 | active, ap->ioaddr.device_addr);
if (adev->class != ATA_DEV_ATA) {
u8 rconf = inb(0x3E6);
@@ -388,7 +390,7 @@
outb(rconf, 0x3E6);
}
}
- inb(ap->ioaddr.status_addr);
+ ioread8(ap->ioaddr.status_addr);
}
static struct ata_port_operations ht6560b_port_ops = {
@@ -406,7 +408,7 @@
.qc_prep = ata_qc_prep,
.qc_issue = ata_qc_issue_prot,
- .data_xfer = ata_pio_data_xfer, /* FIXME: Check 32bit and noirq */
+ .data_xfer = ata_data_xfer, /* FIXME: Check 32bit and noirq */
.irq_handler = ata_interrupt,
.irq_clear = ata_bmdma_irq_clear,
@@ -454,12 +456,12 @@
u8 rc;
/* Enter configuration mode */
- inw(ap->ioaddr.error_addr);
- inw(ap->ioaddr.error_addr);
- outb(3, ap->ioaddr.nsect_addr);
+ ioread16(ap->ioaddr.error_addr);
+ ioread16(ap->ioaddr.error_addr);
+ iowrite8(3, ap->ioaddr.nsect_addr);
/* Read VLB clock strapping */
- clock = 1000000000 / khz[inb(ap->ioaddr.lbah_addr) & 0x03];
+ clock = 1000000000 / khz[ioread8(ap->ioaddr.lbah_addr) & 0x03];
/* Get the timing data in cycles */
ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);
@@ -477,33 +479,33 @@
setup = FIT(t.setup, 1, 4) - 1;
/* Select the right timing bank for write timing */
- rc = inb(ap->ioaddr.lbal_addr);
+ rc = ioread8(ap->ioaddr.lbal_addr);
rc &= 0x7F;
rc |= (adev->devno << 7);
- outb(rc, ap->ioaddr.lbal_addr);
+ iowrite8(rc, ap->ioaddr.lbal_addr);
/* Write the timings */
- outb(active << 4 | recover, ap->ioaddr.error_addr);
+ iowrite8(active << 4 | recover, ap->ioaddr.error_addr);
/* Select the right bank for read timings, also
load the shared timings for address */
- rc = inb(ap->ioaddr.device_addr);
+ rc = ioread8(ap->ioaddr.device_addr);
rc &= 0xC0;
rc |= adev->devno; /* Index select */
rc |= (setup << 4) | 0x04;
- outb(rc, ap->ioaddr.device_addr);
+ iowrite8(rc, ap->ioaddr.device_addr);
/* Load the read timings */
- outb(active << 4 | recover, ap->ioaddr.data_addr);
+ iowrite8(active << 4 | recover, ap->ioaddr.data_addr);
/* Ensure the timing register mode is right */
- rc = inb (ap->ioaddr.lbal_addr);
+ rc = ioread8(ap->ioaddr.lbal_addr);
rc &= 0x73;
rc |= 0x84;
- outb(rc, ap->ioaddr.lbal_addr);
+ iowrite8(rc, ap->ioaddr.lbal_addr);
/* Exit command mode */
- outb(0x83, ap->ioaddr.nsect_addr);
+ iowrite8(0x83, ap->ioaddr.nsect_addr);
}
@@ -522,7 +524,7 @@
.qc_prep = ata_qc_prep,
.qc_issue = ata_qc_issue_prot,
- .data_xfer = ata_pio_data_xfer,
+ .data_xfer = ata_data_xfer,
.irq_handler = ata_interrupt,
.irq_clear = ata_bmdma_irq_clear,
@@ -551,9 +553,9 @@
sysclk = opti_syscfg(0xAC) & 0xC0; /* BIOS set */
/* Enter configuration mode */
- inw(ap->ioaddr.error_addr);
- inw(ap->ioaddr.error_addr);
- outb(3, ap->ioaddr.nsect_addr);
+ ioread16(ap->ioaddr.error_addr);
+ ioread16(ap->ioaddr.error_addr);
+ iowrite8(3, ap->ioaddr.nsect_addr);
/* Read VLB clock strapping */
clock = 1000000000 / khz[sysclk];
@@ -574,33 +576,33 @@
setup = FIT(t.setup, 1, 4) - 1;
/* Select the right timing bank for write timing */
- rc = inb(ap->ioaddr.lbal_addr);
+ rc = ioread8(ap->ioaddr.lbal_addr);
rc &= 0x7F;
rc |= (adev->devno << 7);
- outb(rc, ap->ioaddr.lbal_addr);
+ iowrite8(rc, ap->ioaddr.lbal_addr);
/* Write the timings */
- outb(active << 4 | recover, ap->ioaddr.error_addr);
+ iowrite8(active << 4 | recover, ap->ioaddr.error_addr);
/* Select the right bank for read timings, also
load the shared timings for address */
- rc = inb(ap->ioaddr.device_addr);
+ rc = ioread8(ap->ioaddr.device_addr);
rc &= 0xC0;
rc |= adev->devno; /* Index select */
rc |= (setup << 4) | 0x04;
- outb(rc, ap->ioaddr.device_addr);
+ iowrite8(rc, ap->ioaddr.device_addr);
/* Load the read timings */
- outb(active << 4 | recover, ap->ioaddr.data_addr);
+ iowrite8(active << 4 | recover, ap->ioaddr.data_addr);
/* Ensure the timing register mode is right */
- rc = inb (ap->ioaddr.lbal_addr);
+ rc = ioread8(ap->ioaddr.lbal_addr);
rc &= 0x73;
rc |= 0x84;
- outb(rc, ap->ioaddr.lbal_addr);
+ iowrite8(rc, ap->ioaddr.lbal_addr);
/* Exit command mode */
- outb(0x83, ap->ioaddr.nsect_addr);
+ iowrite8(0x83, ap->ioaddr.nsect_addr);
/* We need to know this for quad device on the MVB */
ap->host->private_data = ap;
@@ -650,7 +652,7 @@
.qc_prep = ata_qc_prep,
.qc_issue = opti82c46x_qc_issue_prot,
- .data_xfer = ata_pio_data_xfer,
+ .data_xfer = ata_data_xfer,
.irq_handler = ata_interrupt,
.irq_clear = ata_bmdma_irq_clear,
@@ -676,6 +678,7 @@
struct ata_probe_ent ae;
struct platform_device *pdev;
struct ata_port_operations *ops = &legacy_port_ops;
+ void __iomem *io_addr, *ctrl_addr;
int pio_modes = pio_mask;
u32 mask = (1 << port);
int ret;
@@ -689,6 +692,12 @@
devm_request_region(&pdev->dev, ctrl, 1, "pata_legacy") == NULL)
goto fail;
+ ret = -ENOMEM;
+ io_addr = devm_ioport_map(&pdev->dev, io, 8);
+ ctrl_addr = devm_ioport_map(&pdev->dev, ctrl, 1);
+ if (!io_addr || !ctrl_addr)
+ goto fail;
+
if (ht6560a & mask) {
ops = &ht6560a_port_ops;
pio_modes = 0x07;
@@ -754,9 +763,9 @@
ae.irq = irq;
ae.irq_flags = 0;
ae.port_flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST;
- ae.port[0].cmd_addr = io;
- ae.port[0].altstatus_addr = ctrl;
- ae.port[0].ctl_addr = ctrl;
+ ae.port[0].cmd_addr = io_addr;
+ ae.port[0].altstatus_addr = ctrl_addr;
+ ae.port[0].ctl_addr = ctrl_addr;
ata_std_ports(&ae.port[0]);
ae.private_data = ld;