tree 06b47117dce3c6e4296d4f32ca5dabdb885cfccc
parent ff83b377cb56875fb4daba63e2595d8c27d9204d
parent 3ff11fe8e8195d87090df9ffabfc85b4d35054c2
author Arnd Bergmann <arnd@arndb.de> 1461851124 +0200
committer Arnd Bergmann <arnd@arndb.de> 1461851124 +0200
mergetag object 3ff11fe8e8195d87090df9ffabfc85b4d35054c2
 type commit
 tag lpc32xx-dt-4.7
 tagger Vladimir Zapolskiy <vz@mleia.com> 1461800139 +0300
 
 NXP LPC32xx device tree updates for v4.7
 
 This includes a few functional changes:
 * new representation of MIC, SIC1 and SIC2 interrupt controllers,
 * disabled by default SPI1, SPI2, SSP0 and SSP1 SPI controllers in
   shared lpc32xx.dtsi file,
 * added clock sources for SPI1 and SPI2,
 * set default clock rate of HCLK PLL to main osc rate multiplied by 16.
 
 Also there are some non-functional changes:
 * flatten board DTS files by exploiting device node labels,
 * add 'partitions' device node for NAND SLC / MTD OF,
 * correct Atmel vendor prefix to describe on board AT24 EEPROMs,
 * rename board DTS files by adding SoC name prefix.
 
 Since now DTS files of LPC32xx boards match "^lpc32[2345]0-" pattern.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.12 (GNU/Linux)
 
 iQIcBAABCAAGBQJXIVDoAAoJEKo94to8JTlldp8P/Rq2daHz/cJwylGDUXP45Ja2
 IfEDCjfwyzMqDrQX7S6gCIILmY5RZqw/TOUmYgQ6t+5lsBtooxzLBOj2ZW7J2+3/
 4rni051kOKmPy9wVaQ0x8u335J993Um4mhZYPDW1Ca1vzTN0wPyC6PIxM7KInJ2J
 SQfRLlrY+wxiwG2h0fXXvhGH+7i8t7wRp78dIZZT56LYfJctwjPbAMXFEeeH/5bF
 GpQe2Y5hyxwQ2qL9D1LDiimdm/Mabd0D2R2dNXziWG37vu267Z2OjZqq1/pWk5rg
 dpo4AUkWwTIYrZ5oHpjrSqDgBGzZ7yQYxNIQfRzaZdYlc++Io53jKnXhdCIvMpfb
 lm1ENi3qD+R9BqUPjf7O9qDbkRbM+r8KcTBNuYjiC7pxj3bW6NaBbUs1P1RxUUSG
 +zdDswGZNr1jc26QizVAvvQezNY1nB/V0iIQGnYtxmhyhv1nPMhxf8iW1Iu2DNjE
 dEIHOM30BfPnQ16rGIvotUZ1n2Ka3fzuyqgjffwML8prILCeoo/Tuk5JGHdXblAh
 ousv6Xz9Xq9+ahnd10VFzdbbSrjnVR6ABOWSTS8I7DBlVSPhcd8rqQ1IXIT3GJ1k
 noKCW76Vs4kcrfYQrtIochV4IJYKhHVyI1OAJv/3CTBRT3HCVkrEUtCAukd3uiSs
 7IZU1KnnerNjUhvUvJLx
 =wDt+
 -----END PGP SIGNATURE-----

Merge tag 'lpc32xx-dt-4.7' of git://github.com/vzapolskiy/linux-lpc32xx into next/dt

Merge "NXP LPC32xx device tree updates for v4.7" from Vladimir Zapolskiy:

This includes a few functional changes:
* new representation of MIC, SIC1 and SIC2 interrupt controllers,
* disabled by default SPI1, SPI2, SSP0 and SSP1 SPI controllers in
  shared lpc32xx.dtsi file,
* added clock sources for SPI1 and SPI2,
* set default clock rate of HCLK PLL to main osc rate multiplied by 16.

Also there are some non-functional changes:
* flatten board DTS files by exploiting device node labels,
* add 'partitions' device node for NAND SLC / MTD OF,
* correct Atmel vendor prefix to describe on board AT24 EEPROMs,
* rename board DTS files by adding SoC name prefix.

Since now DTS files of LPC32xx boards match "^lpc32[2345]0-" pattern.

* tag 'lpc32xx-dt-4.7' of git://github.com/vzapolskiy/linux-lpc32xx:
  ARM: dts: lpc32xx: phy3250: add SoC name prefix to board dts file
  ARM: dts: lpc32xx: phy3250: add NAND partitions device node
  ARM: dts: lpc32xx: phy3250: avoid extension of device nodes by absolute path
  ARM: dts: lpc32xx: ea3250: add SoC name prefix to board dts file
  ARM: dts: lpc32xx: ea3250: fix Atmel at24 eeprom vendor
  ARM: dts: lpc32xx: ea3250: add NAND partitions device node
  ARM: dts: lpc32xx: ea3250: avoid extension of device nodes by absolute path
  ARM: dts: lpc32xx: reparent SIC1 and SIC2 interrupts from MIC
  dt-bindings: interrupt-controllers: add description of SIC1 and SIC2
  ARM: dts: lpc32xx: disabled ssp0/spi1 & ssp1/spi2 by default
  ARM: dts: phy3250: enable ssp0
  ARM: dts: lpc32xx: add clock properties to spi nodes
  ARM: dts: lpc32xx: set default clock rate of HCLK PLL