| commit | 0f69c897f378bf975c519b1d2455c03d06477dfa | [log] [tgz] |
|---|---|---|
| author | Axel Lin <axel.lin@gmail.com> | Fri Oct 01 13:56:27 2010 +0800 |
| committer | Liam Girdwood <lrg@slimlogic.co.uk> | Sat Oct 02 14:19:45 2010 +0100 |
| tree | 18724ed7024cd3e2b7b45826a1091aea50664bf3 | |
| parent | e4a6376b3b2999d169b602a582a8819d95ff79bc [diff] |
regulator: max8649 - fix setting extclk_freq The SYNC bits are BIT6 and BIT7 of MAX8649_SYNC register. pdata->extclk_freq could be [0|1|2]. (MAX8649_EXTCLK_26MHZ|MAX8649_EXTCLK_13MHZ|MAX8649_EXTCLK_19MHZ) It requires to left shift 6 bits to properly set extclk_freq. Signed-off-by: Axel Lin <axel.lin@gmail.com> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>