commit d04533650f64fe3367e180f3e488d92205152cd3
author Ralf Baechle <ralf@linux-mips.org> Mon Oct 22 10:38:44 2007 +0100
committer Ralf Baechle <ralf@linux-mips.org> Mon Oct 22 22:09:00 2007 +0100
tree 5f183668d97d9655a8517e61afd46bfa2f80b101
parent 06d428d719dece96c01532b62df4140f4e69a308

[MIPS] time: SMP-proofing of Sibyte clockevent/clocksource code.

The BCM148 has 4 cores but there are also just 4 generic timers available
so use the ZBbus cycle counter instead of it.  In addition the ZBbus
counter also offers a much higher resolution and 64-bit counting so I'm
considering a later complete conversion to it once I figure out if all
members of the Sibyte SOC family support it - the docs seem to agree but
the headers files seem to disagree ...

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>