| /* |
| * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC |
| * applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35, |
| * AT91SAM9X25, AT91SAM9X35 SoC |
| * |
| * Copyright (C) 2012 Atmel, |
| * 2012 Nicolas Ferre <nicolas.ferre@atmel.com> |
| * |
| * Licensed under GPLv2 or later. |
| */ |
| |
| /include/ "skeleton.dtsi" |
| |
| / { |
| model = "Atmel AT91SAM9x5 family SoC"; |
| compatible = "atmel,at91sam9x5"; |
| interrupt-parent = <&aic>; |
| |
| aliases { |
| serial0 = &dbgu; |
| serial1 = &usart0; |
| serial2 = &usart1; |
| serial3 = &usart2; |
| gpio0 = &pioA; |
| gpio1 = &pioB; |
| gpio2 = &pioC; |
| gpio3 = &pioD; |
| tcb0 = &tcb0; |
| tcb1 = &tcb1; |
| }; |
| cpus { |
| cpu@0 { |
| compatible = "arm,arm926ejs"; |
| }; |
| }; |
| |
| memory@20000000 { |
| reg = <0x20000000 0x10000000>; |
| }; |
| |
| ahb { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| apb { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| aic: interrupt-controller@fffff000 { |
| #interrupt-cells = <2>; |
| compatible = "atmel,at91rm9200-aic"; |
| interrupt-controller; |
| interrupt-parent; |
| reg = <0xfffff000 0x200>; |
| }; |
| |
| pit: timer@fffffe30 { |
| compatible = "atmel,at91sam9260-pit"; |
| reg = <0xfffffe30 0xf>; |
| interrupts = <1 4>; |
| }; |
| |
| tcb0: timer@f8008000 { |
| compatible = "atmel,at91sam9x5-tcb"; |
| reg = <0xf8008000 0x100>; |
| interrupts = <17 4>; |
| }; |
| |
| tcb1: timer@f800c000 { |
| compatible = "atmel,at91sam9x5-tcb"; |
| reg = <0xf800c000 0x100>; |
| interrupts = <17 4>; |
| }; |
| |
| dma0: dma-controller@ffffec00 { |
| compatible = "atmel,at91sam9g45-dma"; |
| reg = <0xffffec00 0x200>; |
| interrupts = <20 4>; |
| }; |
| |
| dma1: dma-controller@ffffee00 { |
| compatible = "atmel,at91sam9g45-dma"; |
| reg = <0xffffee00 0x200>; |
| interrupts = <21 4>; |
| }; |
| |
| pioA: gpio@fffff400 { |
| compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| reg = <0xfffff400 0x100>; |
| interrupts = <2 4>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| interrupt-controller; |
| }; |
| |
| pioB: gpio@fffff600 { |
| compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| reg = <0xfffff600 0x100>; |
| interrupts = <2 4>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| interrupt-controller; |
| }; |
| |
| pioC: gpio@fffff800 { |
| compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| reg = <0xfffff800 0x100>; |
| interrupts = <3 4>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| interrupt-controller; |
| }; |
| |
| pioD: gpio@fffffa00 { |
| compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| reg = <0xfffffa00 0x100>; |
| interrupts = <3 4>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| interrupt-controller; |
| }; |
| |
| dbgu: serial@fffff200 { |
| compatible = "atmel,at91sam9260-usart"; |
| reg = <0xfffff200 0x200>; |
| interrupts = <1 4>; |
| status = "disabled"; |
| }; |
| |
| usart0: serial@f801c000 { |
| compatible = "atmel,at91sam9260-usart"; |
| reg = <0xf801c000 0x200>; |
| interrupts = <5 4>; |
| atmel,use-dma-rx; |
| atmel,use-dma-tx; |
| status = "disabled"; |
| }; |
| |
| usart1: serial@f8020000 { |
| compatible = "atmel,at91sam9260-usart"; |
| reg = <0xf8020000 0x200>; |
| interrupts = <6 4>; |
| atmel,use-dma-rx; |
| atmel,use-dma-tx; |
| status = "disabled"; |
| }; |
| |
| usart2: serial@f8024000 { |
| compatible = "atmel,at91sam9260-usart"; |
| reg = <0xf8024000 0x200>; |
| interrupts = <7 4>; |
| atmel,use-dma-rx; |
| atmel,use-dma-tx; |
| status = "disabled"; |
| }; |
| |
| macb0: ethernet@f802c000 { |
| compatible = "cdns,at32ap7000-macb", "cdns,macb"; |
| reg = <0xf802c000 0x100>; |
| interrupts = <24 4>; |
| status = "disabled"; |
| }; |
| |
| macb1: ethernet@f8030000 { |
| compatible = "cdns,at32ap7000-macb", "cdns,macb"; |
| reg = <0xf8030000 0x100>; |
| interrupts = <27 4>; |
| status = "disabled"; |
| }; |
| }; |
| |
| nand0: nand@40000000 { |
| compatible = "atmel,at91rm9200-nand"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = <0x40000000 0x10000000 |
| >; |
| atmel,nand-addr-offset = <21>; |
| atmel,nand-cmd-offset = <22>; |
| gpios = <&pioC 8 0 |
| &pioC 14 0 |
| 0 |
| >; |
| status = "disabled"; |
| }; |
| }; |
| |
| i2c@0 { |
| compatible = "i2c-gpio"; |
| gpios = <&pioA 30 0 /* sda */ |
| &pioA 31 0 /* scl */ |
| >; |
| i2c-gpio,sda-open-drain; |
| i2c-gpio,scl-open-drain; |
| i2c-gpio,delay-us = <2>; /* ~100 kHz */ |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c@1 { |
| compatible = "i2c-gpio"; |
| gpios = <&pioC 0 0 /* sda */ |
| &pioC 1 0 /* scl */ |
| >; |
| i2c-gpio,sda-open-drain; |
| i2c-gpio,scl-open-drain; |
| i2c-gpio,delay-us = <2>; /* ~100 kHz */ |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c@2 { |
| compatible = "i2c-gpio"; |
| gpios = <&pioB 4 0 /* sda */ |
| &pioB 5 0 /* scl */ |
| >; |
| i2c-gpio,sda-open-drain; |
| i2c-gpio,scl-open-drain; |
| i2c-gpio,delay-us = <2>; /* ~100 kHz */ |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| }; |