drm/msm/sde: enable proper support for split flush
Enable atomic hardware flushing of two data paths via a single
flush register. Previously, different data paths were flushed
separately from software, which could potentially result in
the flushes happening on different frames.
Change-Id: I858a0f737743d48404f47af85b407e1cddf0a0a7
Signed-off-by: Clarence Ip <cip@codeaurora.org>
diff --git a/drivers/gpu/drm/msm/sde/sde_encoder_phys_wb.c b/drivers/gpu/drm/msm/sde/sde_encoder_phys_wb.c
index 987f376..649805a 100644
--- a/drivers/gpu/drm/msm/sde/sde_encoder_phys_wb.c
+++ b/drivers/gpu/drm/msm/sde/sde_encoder_phys_wb.c
@@ -882,17 +882,6 @@
hw_res->needs_cdm);
}
-/**
- * sde_encoder_phys_wb_needs_ctl_start - Whether encoder needs ctl_start
- * @phys_enc: Pointer to physical encoder
- * @Return: Whether encoder needs ctl_start
- */
-static bool sde_encoder_phys_wb_needs_ctl_start(
- struct sde_encoder_phys *phys_enc)
-{
- return true;
-}
-
#ifdef CONFIG_DEBUG_FS
/**
* sde_encoder_phys_wb_init_debugfs - initialize writeback encoder debugfs
@@ -994,7 +983,7 @@
ops->wait_for_commit_done = sde_encoder_phys_wb_wait_for_commit_done;
ops->prepare_for_kickoff = sde_encoder_phys_wb_prepare_for_kickoff;
ops->handle_post_kickoff = sde_encoder_phys_wb_handle_post_kickoff;
- ops->needs_ctl_start = sde_encoder_phys_wb_needs_ctl_start;
+ ops->trigger_start = sde_encoder_helper_trigger_start;
}
/**