drm/msm/sde: enable proper support for split flush
Enable atomic hardware flushing of two data paths via a single
flush register. Previously, different data paths were flushed
separately from software, which could potentially result in
the flushes happening on different frames.
Change-Id: I858a0f737743d48404f47af85b407e1cddf0a0a7
Signed-off-by: Clarence Ip <cip@codeaurora.org>
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_ctl.h b/drivers/gpu/drm/msm/sde/sde_hw_ctl.h
index 46f9a24..2f9ff5b 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_ctl.h
+++ b/drivers/gpu/drm/msm/sde/sde_hw_ctl.h
@@ -72,6 +72,13 @@
void (*clear_pending_flush)(struct sde_hw_ctl *ctx);
/**
+ * Query the value of the cached pending_flush_mask
+ * No effect on hardware
+ * @ctx : ctl path ctx pointer
+ */
+ u32 (*get_pending_flush)(struct sde_hw_ctl *ctx);
+
+ /**
* OR in the given flushbits to the cached pending_flush_mask
* No effect on hardware
* @ctx : ctl path ctx pointer