| commit | 11e71007a5652dce2528a5d2451fe2697c6a370a | [log] [tgz] |
|---|---|---|
| author | Jon Hunter <jonathanh@nvidia.com> | Tue May 05 15:17:53 2015 +0100 |
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | Sun May 10 19:12:18 2015 +0200 |
| tree | 523bc8985b6aeb782d6787c16c35db250be9a506 | |
| parent | 245c0278ab2a2e3d0360296710b4c285291469b5 [diff] |
serial: tegra: Add delay after enabling FIFO mode For all tegra devices (up to t210), there is a hardware issue that requires software to wait for 3 UART clock periods after enabling the TX fifo, otherwise data could be lost. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>