tree 1ca10d18beab1474456bd81b6b84f4a305159293
parent 429d47d524b0c986d5354814077ac5beede5fb68
author Satheeshakrishna M <satheeshakrishna.m@intel.com> 1415890515 +0000
committer Daniel Vetter <daniel.vetter@ffwll.ch> 1415960284 +0100

drm/i915/skl: CD clock back calculation for SKL

Determine programmed cd clock for SKL.

v2: Fix the LCPLL1 enable warning logic

v3: Rebase over the hsw pll rework.

v4: Rebase on top of the per-platform split (Damien)

v5: Modified as per review comments from Paulo

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>