| commit | 139fd30943c3c8ed76d0ce08ff711cfff3b118ec | [log] [tgz] |
|---|---|---|
| author | Bill Huang <bilhuang@nvidia.com> | Thu Jun 18 17:28:35 2015 -0400 |
| committer | Thierry Reding <treding@nvidia.com> | Thu Dec 17 13:37:55 2015 +0100 |
| tree | e5d3d9bec2145062c1ad25c44f50d21ab95737bb | |
| parent | 0ef9db6cf24dbb58118818e64198d9a030e4697e [diff] |
clk: tegra: Add Super Gen5 Logic Super clock divider control and clock source mux of Tegra210 has changed a little against prior SoCs, this patch adds Gen5 logic to address those differences. Signed-off-by: Bill Huang <bilhuang@nvidia.com> Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>