tree e5d3d9bec2145062c1ad25c44f50d21ab95737bb
parent 0ef9db6cf24dbb58118818e64198d9a030e4697e
author Bill Huang <bilhuang@nvidia.com> 1434662915 -0400
committer Thierry Reding <treding@nvidia.com> 1450355875 +0100

clk: tegra: Add Super Gen5 Logic

Super clock divider control and clock source mux of Tegra210 has changed
a little against prior SoCs, this patch adds Gen5 logic to address those
differences.

Signed-off-by: Bill Huang <bilhuang@nvidia.com>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>