tree 2bfc238f089495e6d64d15e772ea354054f3a1d3
parent b8291ad07a7f3b5b990900f0001198ac23ba893e
author Josh Boyer <jwboyer@linux.vnet.ibm.com> 1210862626 +1000
committer Josh Boyer <jwboyer@linux.vnet.ibm.com> 1211207800 -0500

[POWERPC] 4xx: Workaround for CHIP_11 Errata

The PowerPC 440EP, 440GR, 440EPx, and 440GRx chips have an issue that
causes the PLB3-to-PLB4 bridge to wait indefinitely for transaction
requests that cross the end-of-memory-range boundary.  Since the DDR
controller only returns the valid portion of a read request, the bridge
will prevent other PLB masters from completing their transactions.

This implements the recommended workaround for this errata for chips that
use older versions of firmware that do not already handle it.  The last
4KiB of memory are hidden from the kernel to prevent the problem
transactions from occurring.

Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>